Search results for "registers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Faith Ellen, Panagiota Fatourou, Eric Ruppert	The space complexity of unbounded timestamps.	Distributed Comput.	2008	DBLP DOI BibTeX RDF	Obstruction-free, Lower bounds, Anonymous, Shared memory, Timestamps, Wait-free
31	Stéphane Demri, Ranko Lazic 0001, Arnaud Sangnier	Model Checking Freeze LTL over One-Counter Automata.	FoSSaCS	2008	DBLP DOI BibTeX RDF
31	Panagiota Fatourou, Nikolaos D. Kallimanis	Time-optimal, space-efficient single-scanner snapshots & multi-scanner snapshots using CAS.	PODC	2007	DBLP DOI BibTeX RDF	linearizable objects, single-scanner, wait-free implementations, distributed algorithms, asynchronous, snapshots, compare-and-swap (CAS)
31	Burkhard Englert	Adaptive Algorithms Using Bounded Memory Are Inherently Non-uniform.	ISPA	2006	DBLP DOI BibTeX RDF
31	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicitstate enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
31	Alban Douillet, José Nelson Amaral, Guang R. Gao	Fine-Grain Stacked Register Allocation for the Itanium Architecture.	LCPC	2002	DBLP DOI BibTeX RDF
31	Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen	Software-Directed Register Deallocation for Simultaneous Multithreaded Processors.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	architecture, register file, simultaneous multithreading, Multithreaded architecture
31	Hagit Attiya, Alla Gorbach, Shlomo Moran	Computing in Totally Anonymous Asynchronous Shared Memory Systems.	DISC	1998	DBLP DOI BibTeX RDF
31	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicit state enumeration.	ITC	1998	DBLP DOI BibTeX RDF
31	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
31	Yehuda Afek, Hagit Attiya, Danny Dolev, Eli Gafni, Michael Merritt, Nir Shavit	Atomic Snapshots of Shared Memory.	J. ACM	1993	DBLP DOI BibTeX RDF	consistent state, fault-tolerance, atomic, snapshot
31	Bernhard Eschermann, Hans-Joachim Wunderlich	Optimized synthesis techniques for testable sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
31	Henry G. Dietz, Chi-Hung Chi	CRegs: a new kind of memory for referencing arrays and pointers.	SC	1988	DBLP DOI BibTeX RDF
31	Thomas Philip	Using animated color graphics to illustrate software and hardware organizations (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
31	Yesh C. Pendarkar	The porting of XINU to the system 370 VM/CMS environment (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF	XINU, IBM System/370
31	Liina Repo, Brett Hashimoto, Veronika Laippala	In search of founding era registers: automatic modeling of registers from the corpus of Founding Era American English.	Digit. Scholarsh. Humanit.	2023	DBLP DOI BibTeX RDF
31	Xing Hu 0009, Sam Toueg	On implementing SWMR registers from SWSR registers in systems with Byzantine failures.	CoRR	2022	DBLP DOI BibTeX RDF
31	Xing Hu 0009, Sam Toueg	On Implementing SWMR Registers from SWSR Registers in Systems with Byzantine Failures.	DISC	2022	DBLP DOI BibTeX RDF
31	Jianfei Luo, Jing Xiang	Three Registers behind two Characters: an Analysis of the Words' Formation and their Registers.	CLSW	2017	DBLP DOI BibTeX RDF
31	Colette Johnen, Lisa Higham	Fault-Tolerant Implementations of Regular Registers by Safe Registers with Applications to Networks.	ICDCN	2009	DBLP DOI BibTeX RDF
31	Colette Johnen, Lisa Higham	Fault-tolerant implementations of atomic registers by safe registers in networks.	PODC	2008	DBLP DOI BibTeX RDF
30	Cezara Dragoi, Gheorghe Stefanescu	On Compiling Structured Interactive Programs with Registers and Voices.	SOFSEM	2008	DBLP DOI BibTeX RDF	structured rv-systems, registers and voices, programming languages, interactive systems, operational semantics, compiler correctness
30	Bard Bloom	Constructing Two-Writer Atomic Registers.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	two-writer, memory register, two-writer protocol, protocols, computer architecture, atomic registers, proof of correctness
30	C. L. Chen	Linear Dependencies in Linear Feedback Shift Registers.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	Linear feedback shift registers, test pattern generation, self-test
30	Alexis C. Arvillias, Dimitris G. Maritsas	Toggle-Registers Generating in Parallel k kth Decimations of m-Sequences xp + xk + 1 Design Tables.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	Tausworthe generators, linear feedback shift registers (FSR's), primitive trinomials, random number generators, Decimation, m-sequences, key generators
29	Nirmal R. Saxena, Edward J. McCluskey	Parallel Signatur Analysis Design with Bounds on Aliasing.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	aliasing probability bounds, parallel signature designs, multiple input signature registers (MISR), linear feedback shift registers, random testing, Signature analysis
29	Laung-Terng Wang, Edward J. McCluskey	Linear Feedback Shift Register Design Using Cyclic Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	feedback, codes, linear-feedback shift registers, shift registers, design technique, test patterns, cyclic codes, pseudoexhaustive testing
29	P. Golan, Ondrej Novák, Jan Hlavicka	Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	pseudoexhaustive test pattern generation, random access scan, scan addresses, logic testing, integrated circuit testing, feedback, linear feedback shift registers, shift registers
28	Minwook Ahn, Yunheung Paek	Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF	heterogeneous register architecture, register aliasing, compiler, code generation, register allocation, register coalescing
28	Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo	Handling don't-care conditions in high-level synthesis and application for reducing initialized registers.	DAC	2009	DBLP DOI BibTeX RDF	RTL symbolic simulation, don't-care (DC), synthesis
28	Elena Dubrova, Maxim Teslenko, Hannu Tenhunen	On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers.	DATE	2008	DBLP DOI BibTeX RDF
28	Andrew Lutomirski, Victor Luchangco	Efficient Large Almost Wait-Free Single-Writer Multireader Atomic Registers.	OPODIS	2008	DBLP DOI BibTeX RDF
28	Nainesh Agarwal, Nikitas J. Dimopoulos	Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction.	SAMOS	2007	DBLP DOI BibTeX RDF
28	Je-Hyung Lee, Jinpyo Park, Soo-Mook Moon	Securing More Registers with Reduced Instruction Encoding Architectures.	RTCSA	2007	DBLP DOI BibTeX RDF
28	Nainesh Agarwal, Nikitas J. Dimopoulos	Towards Automated Power Gating of Registers using CoDeL.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
28	Andrew Klapper	A Survey of Feedback with Carry Shift Registers.	SETA	2004	DBLP DOI BibTeX RDF
28	César Sánchez 0002, José Joaquín Rieta, Francisco Castells, Raúl Alcaraz 0001, José Millet	Wavelet Domain Blind Signal Separation to Analyze Supraventricular Arrhythmias from Holter Registers.	ICA	2004	DBLP DOI BibTeX RDF
28	Pradeep Varma	Wait-Free Publish/Subscribe Using Atomic Registers.	PPAM	2003	DBLP DOI BibTeX RDF
28	Andrew W. Appel, Lal George	Optimal Spilling for CISC Machines with Few Registers.	PLDI	2001	DBLP DOI BibTeX RDF
28	Markus Feldbach, Klaus D. Tönnies	Robust Line Detection in Historical Church Registers.	DAGM-Symposium	2001	DBLP DOI BibTeX RDF	text line detection, Handwriting recognition, document image processing
28	Markus Feldbach, Klaus D. Tönnies	Line Detection and Segmentation in Historical Church Registers.	ICDAR	2001	DBLP DOI BibTeX RDF
28	Chih-Yung Chang, Tzung-Shi Chen, Jang-Ping Sheu	Improving Memory Traffic by Assembly-Level Exploitation of Reuses for Vector Registers.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	vector register, partial reuse, vector compilers, vectorization, data dependence, supercomputer, reuse distance
28	Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal	Using an asymmetric error model to study aliasing in signature analysis registers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
28	Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò	Aliasing in signature analysis testing with multiple input shift registers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
28	Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke	Bounds and analysis of aliasing errors in linear feedback shift registers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
28	Bernhard Smeets	A Note On Sequences Generated by Clock Controlled Shift Registers.	EUROCRYPT	1985	DBLP DOI BibTeX RDF
28	Dieter Gollmann	Pseudo Random Properties of Cascade Connections of Clock Controlled Shift Registers.	EUROCRYPT	1984	DBLP DOI BibTeX RDF
27	Stefan Vijzelaar, Herbert Bos, Wan J. Fokkink	Brief announcement: a shared disk on distributed storage.	PODC	2010	DBLP DOI BibTeX RDF	probabilistic consensus, shared disk semantics, strict linearizability, consistency, redundancy, storage, atomic registers
27	Rainer Göttfert	Sequences of Period 2N-2.	SETA	2006	DBLP DOI BibTeX RDF	Periodic sequences, nonlinear feedback shift registers, minimal polynomial
27	Janusz Rajski, Jerzy Tyszer	Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	ring generators, linear feedback shift registers, primitive polynomials
27	Jovan Dj. Golic, Renato Menicocci	Correlation Attacks on Up/Down Cascades.	ACISP	1998	DBLP DOI BibTeX RDF	clock-controlled shift registers, up/down and stop/go cascades, cryptanalysis, Stream ciphers, correlation attacks
27	Albrecht P. Stroele	Test response compaction using arithmetic functions.	VTS	1996	DBLP DOI BibTeX RDF	arithmetic functions, combinational faults, underflow, feed back, logic testing, built-in self test, digital arithmetic, test pattern generation, adders, circuits, registers, aliasing probability, overflow, subtracters, test response compaction, arithmetic logic units
27	Hagit Attiya, Amotz Bar-Noy, Danny Dolev	Sharing Memory Robustly in Message-Passing Systems.	J. ACM	1995	DBLP DOI BibTeX RDF	processor and link failures, fault-tolerance, message passing, shared memory, emulation, atomic registers, wait-freedom
25	Shih-Hsu Huang, Chia-Ming Chang 0002, Yow-Tyng Nieh	Opposite-phase register switching for peak current minimization.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	peak current, sequential circuit synthesis, Logic synthesis, IC testing
25	Marcos Kawazoe Aguilera, Ram Swaminathan	Remote storage with byzantine servers.	SPAA	2009	DBLP DOI BibTeX RDF	distributed system, algorithms, digital signatures, distributed storage, byzantine failures
25	Ozgur Sinanoglu, Tsvetomir Petrov	Isolation Techniques for Soft Cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev	Reducing register pressure in SMT processors through L2-miss-driven early register release.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	register file, Simultaneous multithreading
25	Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001	Post-pass periodic register allocation to minimise loop unrolling degree.	LCTES	2008	DBLP DOI BibTeX RDF	embedded code optimisation, periodic register allocation, software pipelining, loop unrolling
25	Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi	A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors.	HASE	2008	DBLP DOI BibTeX RDF
25	Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda	REWIRED - Register Write Inhibition by Resource Dedication.	ASP-DAC	2008	DBLP DOI BibTeX RDF
25	Sid Ahmed Ali Touati	On the Periodic Register Need in Software Pipelining.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining
25	Pablo Montesinos, Wei Liu 0014, Josep Torrellas	Using Register Lifetime Predictions to Protect Register Files against Soft Errors.	DSN	2007	DBLP DOI BibTeX RDF
25	Jonathan K. Lee, Jens Palsberg, Fernando Magno Quintão Pereira	Aliased Register Allocation for Straight-Line Programs Is NP-Complete.	ICALP	2007	DBLP DOI BibTeX RDF
25	Joseph J. Sharkey, Dmitry V. Ponomarev	An L2-miss-driven early register deallocation for SMT processors.	ICS	2007	DBLP DOI BibTeX RDF	register files, simultaneous multithreading
25	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa	Pack instruction generation for media pUsing multi-valued decision diagram.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multi-valued decision diagram, SIMD instructions
25	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	optimization, Code generation, low-power design, graph partitioning, embedded processor, retargetable compilers, spill code, instruction encoding, register window
25	Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin	Compiler Directed Early Register Release.	IEEE PACT	2005	DBLP DOI BibTeX RDF
25	Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail	Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.	DSN	2005	DBLP DOI BibTeX RDF
25	Alban Douillet, Guang R. Gao	Register Pressure in Software-Pipelined Loop Nests: Fast Computation and Impact on Architecture Design.	LCPC	2005	DBLP DOI BibTeX RDF
25	Bogdan S. Chlebus, Dariusz R. Kowalski	Cooperative asynchronous update of shared memory.	STOC	2005	DBLP DOI BibTeX RDF	problem Write-All, read and write register, work efficiency, distributed algorithm, expander, asynchrony, disperser
25	Gadi Taubenfeld	The Black-White Bakery Algorithm and Related Bounded-Space, Adaptive, Local-Spinning and FIFO Algorithms.	DISC	2004	DBLP DOI BibTeX RDF
25	Ittai Abraham, Gregory V. Chockler, Idit Keidar, Dahlia Malkhi	Byzantine disk paxos: optimal resilience with byzantine shared memory.	PODC	2004	DBLP DOI BibTeX RDF	termination conditions, consensus, Byzantine failures, shared-memory emulations
25	Bernard Goossens	The Instruction Register File.	PaCT	2003	DBLP DOI BibTeX RDF
25	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
25	Stefan R. Meier, Mario Steinert, Steffen Buch	Testability of path history memories with register-exchange architecture used in Viterbi-decoders.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
25	Doaa A. Nassar, Aly E. Salama	A heuristic DSP BIST insertion algorithm with minimum area overhead.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
25	Andreas Kuehlmann, Jason Baumgartner	Transformation-Based Verification Using Generalized Retiming.	CAV	2001	DBLP DOI BibTeX RDF
25	Sid Ahmed Ali Touati	Register Saturation in Superscalar and VLIW Codes.	CC	2001	DBLP DOI BibTeX RDF
25	Shlomi Dolev, Ted Herman	Dijkstra's Self-Stabilizing Algorithm in Unsupportive Environments.	WSS	2001	DBLP DOI BibTeX RDF
25	Ihn-Han Bae	A Quorum-Based Dynamic Location Management Method for Mobile Computings.	RTCSA	1999	DBLP DOI BibTeX RDF	location management, quorum, mobile computing systems
25	Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors.	LCPC	1999	DBLP DOI BibTeX RDF
25	Faith E. Fich, Maurice Herlihy, Nir Shavit	On the Space Complexity of Randomized Synchronization.	J. ACM	1998	DBLP DOI BibTeX RDF	lower bounds, consensus, space complexity
25	Kazuhito Ito, Keshab K. Parhi	A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
25	Joseph D. Oldham, V. Wiktor Marek, Miroslaw Truszczynski	Intelligent Computation of Presentation Documents.	ISMIS	1997	DBLP DOI BibTeX RDF
25	Keith I. Farkas, Norman P. Jouppi, Paul Chow	Register File Design Considerations in Dynamically Scheduled Processors.	HPCA	1996	DBLP DOI BibTeX RDF	dynamic scheduling, register files, register renaming
25	Steven L. Scott	Synchronization and Communication in the T3E Multiprocessor.	ASPLOS	1996	DBLP DOI BibTeX RDF
25	Nam Sung Woo	A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System.	DAC	1990	DBLP DOI BibTeX RDF
25	Lefteris M. Kirousis, Evangelos Kranakis, Paul M. B. Vitányi	Atomic Multireader Register.	WDAG	1987	DBLP DOI BibTeX RDF	regular, atomic, Register, reader, writer, shared register
22	Andreas Larsson, Anders Gidenstam, Phuong Hoai Ha, Marina Papatriantafilou, Philippas Tsigas	Multiword atomic read/write registers on multiprocessor systems.	ACM J. Exp. Algorithmics	2008	DBLP DOI BibTeX RDF	synchronization, wait-free, Atomic register
22	François Arnault, Thierry P. Berger	Correction to "Feedback With Carry Shift Registers Synthesis With the Euclidean Algorithm" [May 04 910-917].	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
22	Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert	Mutually Clock-Controlled Feedback Shift Registers Provide Resistance to Algebraic Attacks.	Inscrypt	2007	DBLP DOI BibTeX RDF	stream cipher, algebraic attacks, clock-control
22	Qunfeng Dong, Suman Banerjee 0001, Jia Wang, Dheeraj Agrawal	Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	rule cache, rule evolution, packet classification
22	Cédric Lauradoux	From Hardware to Software Synthesis of Linear Feedback Shift Registers.	IPDPS	2007	DBLP DOI BibTeX RDF
22	Jie Li, John C. Lach	Negative-skewed shadow registers for at-speed delay variation characterization.	ICCD	2007	DBLP DOI BibTeX RDF
22	Hai Lin 0004, Yunsi Fei	Utilizing custom registers in application-specific instruction set processors for register spills elimination.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	custom register, ASIP, register file
22	Mark Goresky, Andrew Klapper	Pseudonoise sequences based on algebraic feedback shift registers.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
22	William R. Roberts, Dimitrios Velenis	Power supply variation effects on timing characteristics of clocked registers.	ISCAS	2006	DBLP DOI BibTeX RDF
22	William R. Roberts, Dimitrios Velenis	Effects of process and environmental variations on timing characteristics of clocked registers.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
22	William R. Roberts, Dimitrios Velenis	Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers.	PATMOS	2005	DBLP DOI BibTeX RDF