Search results for "timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
38	Yuhua Chen, Wenkuo Liu, Hongwei Wang, Jilin Xie, Timing Zhang, Limeng Yin, Yongde Huang	Effect of Ti Content on the Microstructure and Properties of CoCrFeNiMnTix High Entropy Alloy.	Entropy	2022	DBLP DOI BibTeX RDF
38	Yufan Yan, Timing Qu, Francesco Grilli	Numerical Modeling of AC Loss in HTS Coated Conductors and Roebel Cable Using T-A Formulation and Comparison With H Formulation.	IEEE Access	2021	DBLP DOI BibTeX RDF
38	Timing Li, Lei Yang, Kewen Li, Jiannan Zhai	An Intelligent Fusion Algorithm and Its Application Based on Subgroup Migration and Adaptive Boosting.	Symmetry	2021	DBLP DOI BibTeX RDF
38	Timing Li, Yongzhe Zhang, Kewen Li, Yongqi Liang, Xiangbo Ma	A multi-objective optimization algorithm based on subgroup stratified coarse-grained model and its application.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
38	Yimin Dou, Kewen Li, Jianbing Zhu, Timing Li, Shaoquan Tan, Zongchao Huang	Efficient Training of 3D Seismic Image Fault Segmentation Network under Sparse Labels by Weakening Anomaly Annotation.	CoRR	2021	DBLP BibTeX RDF
38	Zhengqiu Weng, Timing Chen, Tiantian Zhu, Hang Dong, Dan Zhou, Osama Alfarraj	TLSmell: Direct Identification on Malicious HTTPs Encryption Traffic with Simple Connection-Specific Indicators.	Comput. Syst. Sci. Eng.	2021	DBLP DOI BibTeX RDF
38	Kewen Li, Mingxiao Yu, Lu Liu, Timing Li, Jiannan Zhai	Feature Selection Method Based on Weighted Mutual Information for Imbalanced Data.	Int. J. Softw. Eng. Knowl. Eng.	2018	DBLP DOI BibTeX RDF
38	Kewen Li, Lu Liu, Jiannan Zhai, Taghi M. Khoshgoftaar, Timing Li	The improved grey model based on particle swarm optimization algorithm for time series prediction.	Eng. Appl. Artif. Intell.	2016	DBLP DOI BibTeX RDF
38	Navin Kashyap, David L. Neuhoff	Data Synchronization With Timing: The Variable-Rate Case.	IEEE Trans. Inf. Theory	2009	DBLP DOI BibTeX RDF
38	Seung Joon Lee, Norman C. Beaulieu	A Novel Pulse Designed to Jointly Optimize Symbol Timing Estimation Performance and the Mean Squared Error of Recovered Data.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
38	Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong	Interconnect Power Optimization Based on Timing Analysis.	ISVLSI	2007	DBLP DOI BibTeX RDF
38	Yinglong Ma, Beihong Jin, Yuancheng Li, Kehe Wu	A Timing Analysis Model for Ontology Evolutions Based on Distributed Environments.	PAKDD	2007	DBLP DOI BibTeX RDF
38	Zhi Tian, Georgios B. Giannakis	A GLRT approach to data-aided timing acquisition in UWB radios-Part II: training sequence design.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
38	Ken Tseng, Mark Horowitz	False coupling exploration in timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
38	Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu	Static statistical timing analysis for latch-based pipeline designs.	ICCAD	2004	DBLP DOI BibTeX RDF
38	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak	Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.	ITC	2003	DBLP DOI BibTeX RDF
38	Rita Yu Chen, Paul Yip, Georgios K. Konstadinidis, Andrew Demas, Fabian Klass, Robert E. Mains, Margaret Schmitt, Dina Bistry	Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design.	ICCD	2002	DBLP DOI BibTeX RDF
38	Cho W. Moon, Harish Kriplani, Krishna P. Belkhale	Timing model extraction of hierarchical blocks by graph reduction.	DAC	2002	DBLP DOI BibTeX RDF
38	Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin	A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
38	Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita	Speeding up technology-independent timing optimization by network partitioning.	ICCAD	1997	DBLP DOI BibTeX RDF
38	Louise E. Moser, P. M. Melliar-Smith	Analysis of Timing Hazards in Ada Programs.	ACM Conference on Computer Science	1993	DBLP DOI BibTeX RDF	Ada
38	Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa	ACTAS: an accurate timing analysis system for VLSI.	DAC	1985	DBLP DOI BibTeX RDF
38	Thomas Lundqvist, Per Stenström	Timing Anomalies in Dynamically Scheduled Microprocessors.	RTSS	1999	DBLP DOI BibTeX RDF	timing anomaly, Real-time systems, resource allocation, timing analysis, worst-case execution time, out-of-order execution, dynamically scheduled processor
38	Hakan Yalcin, John P. Hayes	Hierarchical timing analysis using conditional delays.	ICCAD	1995	DBLP DOI BibTeX RDF	Hierarchical timing analysis, conditional delays, symbolic analysis, timing modeling, path sensitization, high-level modeling
38	Aaron J. Gordon, Raphael A. Finkel	Handling Timing Errors in Distributed Programs.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	postmortem debugger, history-keeping mechanism, distributed processing, software tools, program testing, directed graph, directed graphs, distributed programs, interprocess communication, TAP, timing errors, timing graph
37	Benjamin Carrión Schäfer, Taewhan Kim	Hotspots Elimination and Temperature Flattening in VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
37	Michel Raynal, Gadi Taubenfeld	The notion of a timed register and its application to indulgent synchronization.	SPAA	2007	DBLP DOI BibTeX RDF	test&set, timing assumption, universal object, wait-free implementation, consensus, mutual exclusion, timing constraint, contention manager, process crash, simplicity, atomic register, renaming, concurrent object, asynchronous shared memory system
36	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
36	Anders Edman, Christer Svensson	Timing closure through a globally synchronous, timing partitioned design methodology.	DAC	2004	DBLP DOI BibTeX RDF	wire delays, clock skew, timing closure
36	Johan Nordlander, Rolf Johansson, Risat Mahmud Pathan	Unambiguous semantics in automotive timing modeling.	EDCC-CARS	2010	DBLP DOI BibTeX RDF	modeling, synchronization, delay constraints, timing semantics
36	Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan	TSV stress aware timing analysis with applications to 3D-IC layout optimization.	DAC	2010	DBLP DOI BibTeX RDF	mobility variation, timing analysis, stress, TSV, 3DIC
36	Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele	Cache-aware timing analysis of streaming applications.	Real Time Syst.	2009	DBLP DOI BibTeX RDF	Timing analysis, Instruction cache, Streaming applications
36	Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls	Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Timing recovery, FPGA, Synchronization, SDR, Feedback loop
36	Yusuke Okuno, Takayuki Kanda 0001, Michita Imai, Hiroshi Ishiguro, Norihiro Hagita	Providing route directions: design of robot's utterance, gesture, and timing.	HRI	2009	DBLP DOI BibTeX RDF	gesture, timing, route directions
36	David D. Ling, Chandu Visweswariah, Peter Feldmann, Soroush Abbaspour	A moment-based effective characterization waveform for static timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	timing analysis, current source model
36	Keith So	Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals.	FPGA	2008	DBLP DOI BibTeX RDF	lexicographic search, negotiated congestion, timing-driven routing, FPGA
36	Wenyuan Xu 0001, Wade Trappe, Yanyong Zhang	Anti-jamming timing channels for wireless networks.	WISEC	2008	DBLP DOI BibTeX RDF	jamming, timing channel, radio interference
36	Xiaoxiao Liu, Guangsheng Ma, Qiang Sun	An Advanced Timing Characterization Method Considering Global False Path.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF	functional (mode) dependency, timing analysis, false path, Circuit delay
36	Joseph Bonneau, Ilya Mironov	Cache-Collision Timing Attacks Against AES.	CHES	2006	DBLP DOI BibTeX RDF	cache, cryptanalysis, AES, side-channel attack, timing attack
36	Shuhua Wang, Grace Tsai	Specification and Timing Analysis of Real-Time Systems.	Real Time Syst.	2004	DBLP DOI BibTeX RDF	functional and timing requirements, real-time systems, specification, schedulability analysis, allocation
36	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Capturing crosstalk-induced waveform for accurate static timing analysis.	ISPD	2003	DBLP DOI BibTeX RDF	capacitive coupling noise, delay calculation, slope propagation, static timing analysis, crosstalk noise
36	Sheng-Tzong Cheng, Ashok K. Agrawala	Allocation and scheduling of real-time periodic tasks with relative timing constraints.	RTCSA	1995	DBLP DOI BibTeX RDF	real-time periodic tasks, scheduling, scheduling, real-time systems, real-time systems, resource allocation, task scheduling, processor scheduling, timing constraints, communication scheduling
36	Jing Zeng, Magdy S. Abadir, Jacob A. Abraham	False timing path identification using ATPG techniques and delay-based information.	DAC	2002	DBLP DOI BibTeX RDF	false timing paths, timing slack, ATPG, static timing analysis
36	Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang 0046	Foresighted Instruction Scheduling Under Timing Constraints.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	foresighted instruction scheduling, minimum timing information, foresighted compaction, data dependency graph arcs, data dependency information, maximum timing information, greedy compaction algorithms, scheduling, parallel algorithms, parallel programming, graph theory, timing constraints, programming theory, list scheduling, look ahead
35	Yu-Sheng Huang, Chih-wen Hsueh	Minimizing the maximum end-to-end delay on tree structure using the distributed pinwheel model.	RTCSA	2000	DBLP DOI BibTeX RDF	maximum end-to-end delay minimisation, distributed pinwheel model, end-to-end timing requirements, tight maximum delay bound, quality of service, Internet, computational complexity, timing, computer networks, heuristic algorithm, processor scheduling, timing constraints, simulation result, distributed real-time systems, tree structure, heuristic programming, NP-hard problems, linear-time algorithm, pipeline structure
35	Gary S. H. Tan, Yong Meng Teo	Experiences in simulating a declarative multiprocessor.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	declarative multiprocessor simulation, declarative programming languages, Flagship parallel reduction machine, packet-based graph reduction model, executional units, timing characteristics, event-driven timing scheme, tightly-coupled processor-store pairs, performance evaluation, performance evaluation, parallel architectures, virtual machines, timing, parallel machines, synchronisation, synchronisation, parallel languages, functional languages, functional languages, functional simulator, parallel computer architectures, MIMD architecture, delta network
35	Douglas Niehaus, John A. Stankovic, Krithi Ramamritham	A real-time system description language.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	real-time system description language, system design specification, automatic calculation, automatic analysis environment, design and analysis environment, specification changes, layered abstractions, concealed implementation details, timing correctness, robotic pick-and-place circuit board assembly, distributed real-time scheduling simulation, ease of modification, automatic loading, real-time systems, timing, specification languages, timing analysis, SDL, automatic linking, flexible manufacturing
35	Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten	Performance driven standard-cell placement using the genetic algorithm.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement
35		It's All in the Timing, Papers from the 2010 AAAI Spring Symposium, Technical Report SS-10-06, Stanford, California, USA, March 22-24, 2010	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Bastian Hartmann, Ingo Schwab, Norbert Link	Prototype Optimization for Temporarily and Spatially Distorted Time Series.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Javier Snaider, Ryan James McCall, Stan Franklin	The Immediate Present Train Model Time Production and Representation for Cognitive Agents.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Julie A. Shah, Brian Charles Williams, Cynthia Breazeal	Dynamic Execution of Temporal Plans for Temporally Fluid Human-Robot Teaming.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Jonathan K. Alt, Stephen Lieberman, Ahmed Al Rowaei	Exploring the Implications of Time in Discrete Event Social Simulations.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Frank Förster, Chrystopher L. Nehaniv	Representations of Time in Symbol Grounding Systems.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Pinar Wennerberg, Klaus U. Schulz	An Ontology of Socio-Cultural Time Expressions.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Eric M. Meisner, Selma Sabanovic	Grounding Communication Without Prior Structure.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Guy Hoffman	Anticipation in Human-Robot Interaction.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Ian Horswill, Karl Cheng-Heng Fua, Andrew Ortony	Conflict and Hesitancy in Virtual Actors.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	H. Joe Steinhauer, Sook-Ling Chua, Hans Werner Guesgen, Stephen Marsland	Utilising Temporal Information in Behaviour Recognition.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Sonia Chernova, Cynthia Breazeal	Learning Temporal Plans from Observation of Human Collaborative Behavior.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Hartmut Messerschmidt	Separating Moving Objects from Landmarks.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	Richard Veale, Matthias Scheutz	Who Needs Time? Implicit Time Is Sufficient for Some HRI Tasks.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	David V. Lu, Annamaria Pileggi, Chris Wilson, William D. Smart	What Can Actors Teach Robots About Interaction?	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
35	David P. LaPotin, Charles J. Alpert, John Lillis (eds.)	Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP BibTeX RDF
35	Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga	The statistical longest path problem and its application to delay analysis of logical circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
35	Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili	Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	VLSI, clock distribution network, zero skew
35	Himanshu Kaul, Dennis Sylvester, David T. Blaauw	Active shielding of RLC global interconnects.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
35	Sangyun Kim 0001, Sunan Tugsinavisut, Peter A. Beerel	Reducing probabilistic timed petri nets for asynchronous architectural analysis.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
35	Jun Chen 0008, Lei He 0001	Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	interconnect design
35	Min Zhao 0001, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal	Worst case clock skew under power supply variations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	clock skew, power supply noise, clock network
35	Paul I. Pénzes, Mika Nyström, Alain J. Martin	Transistor sizing of energy-delay--efficient circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
35	Brian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, Kenneth K. O	Wireless interconnects for clock distribution.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	integrated antenna, wireless interconnect, wireless communication, interconnect, clock distribution, RF CMOS
35	Joni Dambre, Dirk Stroobandt, Jan Van Campenhout	A probabilistic approach to clock cycle prediction.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	clock cycle prediction, performance modeling, interconnect prediction
35	Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang	Aggressive crunching of extracted RC netlists.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	RC reduction, TICER, crunching, node elimination, resistor shorting, time constants, interconnect modeling, elmore delay
35	Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan	PERI: a technique for extending delay and slew metrics to ramp inputs.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	Elmore, slew, delay, interconnects, PDF, moments, median, skewness, standard deviation
35	V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine	A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.	PATMOS	2007	DBLP DOI BibTeX RDF
35	Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen	Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
35	Alexander Maili, Damian Dalton, Christian Steger	A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.	PATMOS	2004	DBLP DOI BibTeX RDF
35	Per Arne Karlsen, Per Torstein Røine	A Timing Verifier and Timing Profiler for Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
35	Jeffrey J. P. Tsai, Stephen J. H. Yang, Yao-Hsiung Chang, Eric Y. T. Juan	Verifying Timing Properties for Distributed Real-Time Systems Using Timing Constraint Petri Nets.	COMPSAC	1996	DBLP DOI BibTeX RDF
35	Tatsuya Susa, Masahiro Murakawa, Eiichi Takahashi, Tatsumi Furuya, Tetsuya Higuchi	Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins.	HIS	2008	DBLP DOI BibTeX RDF	Post-fabrication Clock-timing Adjustment, Timing Margin, Digital LSI, Genetic Algorithm, Process Variation
34	Marc Schlickling, Markus Pister 0002	Semi-automatic derivation of timing models for WCET analysis.	LCTES	2010	DBLP DOI BibTeX RDF	vhdl, worst-case execution time, hard real-time
34	Xiao Li, Yik-Chung Wu, Erchin Serpedin	Timing Synchronization in Decode-and-Forward Cooperative Communication Systems.	IEEE Trans. Signal Process.	2009	DBLP DOI BibTeX RDF
34	Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu	Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
34	Pawel A. Dmochowski, Peter J. McLane	Timing error detector design and analysis for orthogonal space-time block code receivers.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
34	Christian R. Berger, Shengli Zhou, Zhi Tian, Peter K. Willett	Performance analysis on an MAP fine timing algorithm in UWB multiband OFDM.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
34	Daniel Kästner, Reinhard Wilhelm, Reinhold Heckmann, Marc Schlickling, Markus Pister 0002, Marek Jersak, Kai Richter 0001, Christian Ferdinand	Timing Validation of Automotive Software.	ISoLA	2008	DBLP DOI BibTeX RDF
34	Yibo Chen, Jin Ouyang, Yuan Xie 0001	ILP-based scheme for timing variation-aware scheduling and resource binding.	SoCC	2008	DBLP DOI BibTeX RDF
34	Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu	Elastic Timing Scheme for Energy-Efficient and Robust Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Elstic, Razor, Pipeline, Boosting
34	Yasamin Mostofi, Donald C. Cox	A robust timing synchronization design in OFDM systems - part I: low-mobility cases.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
34	Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001	Statistical Timing Yield Optimization by Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
34	Gadi Taubenfeld	Computing in the Presence of Timing Failures.	ICDCS	2006	DBLP DOI BibTeX RDF
34	Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang	Width and Timing-Constrained Wire Sizing for Critical Area Minimization.	APCCAS	2006	DBLP DOI BibTeX RDF
34	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-factor based loop RLC modeling for efficient timing analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VGTA: Variation Aware Gate Timing Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
34	Ingomar Wenzel, Raimund Kirner, Peter P. Puschner, Bernhard Rieder	Principles of Timing Anomalies in Superscalar Processors.	QSIC	2005	DBLP DOI BibTeX RDF
34	Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng	Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.	FPL	2004	DBLP DOI BibTeX RDF
34	Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng	A path-based methodology for post-silicon timing validation.	ICCAD	2004	DBLP DOI BibTeX RDF
34	Anirudh Devgan, Chandramouli V. Kashyap	Block-based Static Timing Analysis with Uncertainty.	ICCAD	2003	DBLP DOI BibTeX RDF
34	David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran	Slope propagation in static timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF