Search results for "DRAMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	A. F. Tasch Jr., Laureen H. Parker	Memory cell and technology issues for 64- and 256-Mbit one-transistor cell MOSD DRAMs.	Proc. IEEE	1989	DBLP DOI BibTeX RDF
21	W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle	Fast Automatic Failbit Analysis for DRAMs.	ITC	1989	DBLP DOI BibTeX RDF
21	Rainer Kraus, Oskar Kowarik, Kurt Hoffmann, Dieter Oberle	Design for Test of Mbit DRAMs.	ITC	1989	DBLP DOI BibTeX RDF
15	Banit Agrawal, Timothy Sherwood	High-bandwidth network memory system through virtual pipelines.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	VPNM, bank conflicts, mean time to stall, packet reassembly, virtual pipeline, network, memory, DRAM, universal hashing, memory controller, MTS, packet buffering
15	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
15	Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin	Fault models for embedded-DRAM macros.	DAC	2009	DBLP DOI BibTeX RDF	memory testing, embedded DRAM
15	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Eugene Gorbatov, Howard David, Zhichun Zhu	Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.	MICRO	2008	DBLP DOI BibTeX RDF
15	Ibrahim Hur, Calvin Lin	A comprehensive approach to DRAM power management.	HPCA	2008	DBLP DOI BibTeX RDF
15	Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik	An approach for adaptive DRAM temperature and power management.	ICS	2008	DBLP DOI BibTeX RDF	power, temperature, DRAM
15	Maurizio Skerlj, Paolo Ienne	Error Protected Data Bus Inversion Using Standard DRAM Components.	ISQED	2008	DBLP DOI BibTeX RDF	bus inversion, reliability, low power, memory, ECC, DRAM, error protection
15	Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik	A power and temperature aware DRAM architecture.	DAC	2008	DBLP DOI BibTeX RDF	page hit aware write buffer, power, temperature, DRAM
15	Andrew G. Schmidt, Ron Sass	Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores.	FPL	2007	DBLP DOI BibTeX RDF
15	Betty Prince	Nanotechnology and emerging memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory
15	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev	Optimizing Test Length for Soft Faults in DRAM Devices.	VTS	2007	DBLP DOI BibTeX RDF	DRAM testing, test length optimization, circuit design, memory layout, delay time, soft faults
15	Shantanu A. Bhalerao, Abhishek V. Chaudhary, Rajendra M. Patrikar	A CMOS Low Voltage Charge Pump.	VLSI Design	2007	DBLP DOI BibTeX RDF
15	Jung Ho Ahn, William J. Dally	Data parallel address architecture.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
15	Jike Chong, Chidamber Kulkarni, Gordon J. Brebner	Building a flexible and scalable DRAM interface for networking applications on FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
15	Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg	Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM.	HPCA	2006	DBLP DOI BibTeX RDF
15	Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson	DDR2 DRAM Output Timing Optimization.	MTDT	2006	DBLP DOI BibTeX RDF
15	Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca	A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	memory bandwidth, memory wall, processing-in-memory
15	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
15	John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott	Test and Characterization of a Variable-Capacity Multilevel DRAM.	VTS	2005	DBLP DOI BibTeX RDF
15	Kiyoo Itoh 0001, Kenichi Osada, Takayuki Kawahara	Low-Voltage Embedded RAMs - Current Status and Future Trends.	PATMOS	2004	DBLP DOI BibTeX RDF
15	Zaid Al-Ars, Ad J. van de Goor	Soft Faults and the Importance of Stresses in Memory Testing.	DATE	2004	DBLP DOI BibTeX RDF	stress application, Fault modeling, memory testing, defect simulation, soft faults
15	Yoonseo Choi, Taewhan Kim	Memory access driven storage assignment for variables in embedded system design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
15	Guido Appenzeller, Isaac Keslassy, Nick McKeown	Sizing router buffers.	SIGCOMM	2004	DBLP DOI BibTeX RDF	TCP, buffer size, internet router, bandwidth delay product
15	Jahangir Hasan, Satish Chandra 0001, T. N. Vijaykumar	Efficient Use of Memory Bandwidth to Improve Network Processor Throughput.	ISCA	2003	DBLP DOI BibTeX RDF
15	Richard H. Stern	FTC Piles onto Rambus' Standardization Skullduggery.	IEEE Micro	2002	DBLP DOI BibTeX RDF
15	Zaid Al-Ars, Ad J. van de Goor	DRAM Specific Approximation of the Faulty Behavior of Cell Defects.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	memory specific fault analysis, approximating dynamic behavior, memory testing, DRAM
15	Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka	Efficient Power Reduction Techniques for Time Multiplexed Address Buses.	ISSS	2002	DBLP DOI BibTeX RDF	address encoding techniques, time-multiplexed addressing, low power
15	Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai	CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
15	Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim	Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip.	ASAP	2002	DBLP DOI BibTeX RDF
15	Rina Panigrahy, Samar Sharma	Reducing TCAM Power Consumption and Increasing Throughput.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
15	Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin	Hardware and Software Techniques for Controlling DRAM Power Modes.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	low power compilation, software-directed energy management, low power, Memory architecture
15	Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik	Compressed Bit Fail Maps for Memory Fail Pattern Classification.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	bit fail map, compressed bit fail map, catch ram, memory, DRAM
15	Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin	DRAM Energy Management Using Software and Hardware Directed Power Mode Control.	HPCA	2001	DBLP DOI BibTeX RDF	Low Power Compilation, Software-Directed Energy Management, Low Power, Memory Architecture
15	Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter	A Memory Specific Notation for Fault Modeling.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	memory specific fault analysis, memory testing, DRAM, functional fault models, fault primitives
15	Matthias Klaus, Ad J. van de Goor	Tests for Resistive and Capacitive Defects in Address Decoders.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	address decoders, test conditions, Defects, opens, dynamic faults, capacitive coupling
15	Shyue-Kung Lu, Chih-Hsien Hsu	Built-In self-repair for divided word line memory.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
15	Yasunao Katayama, Sumio Morioka	One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems.	DSN	2000	DBLP DOI BibTeX RDF
15	Mary W. Hall, Craig S. Steele	Memory Management in a PIM-Based Architecture.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
15	Chengqiang Zhang, Sally A. McKee	Hardware-only stream prefetching and dynamic access ordering.	ICS	2000	DBLP DOI BibTeX RDF
15	Brian Davis, Bruce L. Jacob, Trevor N. Mudge	The New DRAM Interfaces: SDRAM, RDRAM and Variants.	ISHPC	2000	DBLP DOI BibTeX RDF
15	Matthias Gries	The Impact of Recent DRAM Architectures on Embedded Systems Performance.	EUROMICRO	2000	DBLP DOI BibTeX RDF
15	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF
15	Kiyoshi Nikawa, Shoji Inoue, Kazuyuki Morimoto, Shinya Sone	Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
15	Norbert Wehn, Søren Hein	Embedded DRAM Architectural Trade-Offs.	DATE	1998	DBLP DOI BibTeX RDF	embedded logic, embedded DRAM
15	Said Hamdioui, Ad J. van de Goor	Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
15	Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann 0001, Ulrich Nageldinger	Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators.	FPL	1998	DBLP DOI BibTeX RDF
15	Liuxi Yang, Josep Torrellas	Speeding up the Memory Hierarchy in Flat COMA Multiprocessors.	HPCA	1997	DBLP DOI BibTeX RDF	cache-only memory architectures, cache coherence protocols, cache hierarchies, scalable shared-memory multiprocessors
15	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
15	Ad J. van de Goor, Issam B. S. Tlili	Disturb Neighborhood Pattern Sensitive Fault.	VTS	1997	DBLP DOI BibTeX RDF	Memory fault models, disturb coupling fault model, neighborhood pattern sensitive faults, test algorithms
15	Thomas Alexander, Gershon Kedem	Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems.	HPCA	1996	DBLP DOI BibTeX RDF	Prefetch-buffer, cache, prediction, memory
15	Michihiro Inoue, Toshio Yamada, Atsushi Fujiwara	A New Testing Acceleration Chip for Low-Cost Memory Tests.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
15	G. Jack Lipovski	A four megabit Dynamic Systolic Associative Memory chip.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
15	Wolfgang Bergner, Roland Kircher	SITAR-an efficient 3-D simulator for optimization of nonplanar trench structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
15	Shigeharu Momoi, Shigeo Shimada, Masamitsu Kobayashi, Tsutomu Ishikawa	Hierarchical Array Processor System (HAP).	CONPAR	1986	DBLP DOI BibTeX RDF