Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Runbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu 0001, Hayden Kwok-Hay So, Caiwen Ding	FTDL: An FPGA-tailored Architecture for Deep Learning Systems.	FPGA	2020	DBLP DOI BibTeX RDF
1	Oron Port, Yoav Etsion	Hardware Description Beyond Register-Transfer Level Languages.	FPGA	2020	DBLP DOI BibTeX RDF
1	Lana Josipovic, Andrea Guerrieri, Paolo Ienne	Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits.	FPGA	2020	DBLP DOI BibTeX RDF
1	Shulin Zeng, Guohao Dai, Kai Zhong, Hanbo Sun, Guangjun Ge, Kaiyuan Guo, Yu Wang 0002, Huazhong Yang	Enable Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud.	FPGA	2020	DBLP DOI BibTeX RDF
1	Vladimir Rybalkin, Norbert Wehn	When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network.	FPGA	2020	DBLP DOI BibTeX RDF
1	Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia	MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows.	FPGA	2020	DBLP DOI BibTeX RDF
1	Andrew Putnam	What To Do With Datacenter FPGAs Besides Deep Learning.	FPGA	2020	DBLP DOI BibTeX RDF
1	Sameh Attia, Vaughn Betz	StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging.	FPGA	2020	DBLP DOI BibTeX RDF
1	Taesu Kim, Daehyun Ahn, Jae-Joon Kim	V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning.	FPGA	2020	DBLP DOI BibTeX RDF
1	Shanquan Tian, Wenjie Xiong 0001, Ilias Giechaskiel, Kasper Rasmussen, Jakub Szefer	Fingerprinting Cloud FPGA Infrastructures.	FPGA	2020	DBLP DOI BibTeX RDF
1	Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella	Buffer Placement and Sizing for High-Performance Dataflow Circuits.	FPGA	2020	DBLP DOI BibTeX RDF
1	Patrick Koeberl	Multi-tenant FPGA Security: Challenges and Opportunities.	FPGA	2020	DBLP DOI BibTeX RDF
1	Jiajie Li, Yuze Chi, Jason Cong	HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration.	FPGA	2020	DBLP DOI BibTeX RDF
1	Yue Niu 0001, Rajgopal Kannan, Ajitesh Srivastava, Viktor K. Prasanna	Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN Acceleration.	FPGA	2020	DBLP DOI BibTeX RDF
1	Nils Voss, Tobias Becker, Simon Tilbury, Georgi Gaydadjiev, Oskar Mencer, Anna Maria Nestorov, Enrico Reggiani, Wayne Luk	Performance Portable FPGA Design.	FPGA	2020	DBLP DOI BibTeX RDF
1	Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar	Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion.	FPGA	2020	DBLP DOI BibTeX RDF
1	Atsushi Koshiba, Kouki Watanabe, Takaaki Miyajima, Kentaro Sano	Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGA.	FPGA	2020	DBLP DOI BibTeX RDF
1	Aman Arora, Zhigang Wei, Lizy K. John	The Case for Hard Matrix Multiplier Blocks in an FPGA.	FPGA	2020	DBLP DOI BibTeX RDF
1	Stephen M. Williams, Mingjie Lin	Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni 0001, Mirjana Stojilovic	Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Juan Escobedo, Mingjie Lin	DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative Stencils.	FPGA	2020	DBLP DOI BibTeX RDF
1	Yun Zhou, Dries Vercruyce, Dirk Stroobandt	On the Exploration of Connection-aware Partitioning for Parallel FPGA Routing.	FPGA	2020	DBLP DOI BibTeX RDF
1	Atefeh Sohrabizadeh, Jie Wang 0022, Jason Cong	End-to-End Optimization of Deep Learning Applications.	FPGA	2020	DBLP DOI BibTeX RDF
1	Hanqing Zeng, Viktor K. Prasanna	GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms.	FPGA	2020	DBLP DOI BibTeX RDF
1	Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim	Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping.	FPGA	2020	DBLP DOI BibTeX RDF
1	Ruihao Li 0002, Ke Liu, Mengying Zhao, Zhaoyan Shen, Xiaojun Cai, Zhiping Jia	Maximizing CNN Throughput on FPGA Clusters.	FPGA	2020	DBLP DOI BibTeX RDF
1	Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang	Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement.	FPGA	2020	DBLP DOI BibTeX RDF
1	Stefan Nikolic 0001, Grace Zgheib, Paolo Ienne	Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing.	FPGA	2020	DBLP DOI BibTeX RDF
1	Yu Zou, Mingjie Lin	Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization.	FPGA	2020	DBLP DOI BibTeX RDF
1	Mathew Hall, Vaughn Betz	HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Qiuyue Sun, Amir Taherin, Yawo Siatitse, Yuhao Zhu 0001	Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-Design.	FPGA	2020	DBLP DOI BibTeX RDF
1	Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau 0001, Royson Lee, Hyeji Kim, Nicholas D. Lane	Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search.	FPGA	2020	DBLP DOI BibTeX RDF
1	Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic	CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors.	FPGA	2020	DBLP DOI BibTeX RDF
1	Prashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai	A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow.	FPGA	2020	DBLP DOI BibTeX RDF
1	Rupesh S. Shelar	An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops.	FPGA	2020	DBLP DOI BibTeX RDF
1	Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois	Unleashing the Power of FPGAs as Programmable Switches.	FPGA	2020	DBLP DOI BibTeX RDF
1	Stephen Neuendorffer, Lesley Shannon (eds.)	FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 23-25, 2020	FPGA	2020	DBLP DOI BibTeX RDF
1	Samuel Dewan, Paulo Garcia	Programming Abstractions for Configurable Hardware: Survey and Research Directions.	FPGA	2020	DBLP DOI BibTeX RDF
1	Vinod Kathail	Xilinx Vitis Unified Software Platform.	FPGA	2020	DBLP DOI BibTeX RDF
1	Han Chen, Sergey Madaminov, Michael Ferdman, Peter A. Milder	FPGA-Accelerated Samplesort for Large Data Sets.	FPGA	2020	DBLP DOI BibTeX RDF
1	Jakub Szefer	Thermal and Voltage Side and Covert Channels and Attacks in Cloud FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Seyedramin Rasoulinezhad, Siddhartha 0003, Hao Zhou 0008, Lingli Wang, David Boland, Philip H. W. Leong	LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations.	FPGA	2020	DBLP DOI BibTeX RDF
1	Rachit Rajat, Yuan Meng, Sanmukh R. Kuppannagari, Ajitesh Srivastava, Viktor K. Prasanna, Rajgopal Kannan	QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning Accelerators.	FPGA	2020	DBLP DOI BibTeX RDF
1	Johannes de Fine Licht, Grzegorz Kwasniewski, Torsten Hoefler	Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis.	FPGA	2020	DBLP DOI BibTeX RDF
1	Oscar Rahnama, Tommaso Cavallari, Philip H. S. Torr, Stuart Golodetz	Scalable FPGA Median Filtering using Multiple Efficient Passes.	FPGA	2020	DBLP DOI BibTeX RDF
1	Jincheng Yu, Zhilin Xu, Shulin Zeng, Chao Yu 0005, Jiantao Qiu, Chaoyang Shen, Yuanfan Xu, Guohao Dai, Yu Wang 0002, Huazhong Yang	INCAME: INterruptible CNN Accelerator for Multi-robot Exploration.	FPGA	2020	DBLP DOI BibTeX RDF
1	Parnian Mokri, Maziar Amiraskari, Yuelin Liu, Mark Hempstead	Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree.	FPGA	2020	DBLP DOI BibTeX RDF
1	Yann Herklotz, John Wickerson	Finding and Understanding Bugs in FPGA Synthesis Tools.	FPGA	2020	DBLP DOI BibTeX RDF
1	Yunxuan Yu, Tiandong Zhao, Kun Wang 0005, Lei He 0001	Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks.	FPGA	2020	DBLP DOI BibTeX RDF
1	Chen Wu, Mingyu Wang, Xinyuan Chu, Kun Wang 0005, Lei He 0001	Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration.	FPGA	2020	DBLP DOI BibTeX RDF
1	Lee W. Lerner	Establishing Trust in Microelectronics.	FPGA	2020	DBLP DOI BibTeX RDF
1	Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang 0036, Jinmei Lai	INTB: A New FPGA Interconnect Model for Architecture Exploration.	FPGA	2020	DBLP DOI BibTeX RDF
1	Martin Langhammer, Sergey Gribok, Gregg Baeckler	High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA.	FPGA	2020	DBLP DOI BibTeX RDF
1	Tianyu Zhang, Tiantian Han, Lu Tian, Yi Li, Xijie Jia, Guangdong Liu, Pingbo An, Yingran Tan, Lingzhi Sui, Shaoxia Fang, Dongliang Xie, Michaela Blott, Yi Shan	LPAC: A Low-Precision Accelerator for CNN on FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Endri Bezati, Mahyar Emami, James R. Larus	Advanced Dataflow Programming using Actor Machines for High-Level Synthesis.	FPGA	2020	DBLP DOI BibTeX RDF
1	Tanner Young-Schultz, Lothar Lilge, Stephen Brown, Vaughn Betz	Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator.	FPGA	2020	DBLP DOI BibTeX RDF
1	Ang Li, David Wentzlaff	Cycle-Free FPGA Routing Graphs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Yang Yang 0080, Chao Wang 0003, Lei Gong, Xuehai Zhou	ConvCloud: An Adaptive Convolutional Neural Network Accelerator on Cloud FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Steven McNeil	FPGA / SoC Security: Arms Race in the Cloud.	FPGA	2020	DBLP DOI BibTeX RDF
1	Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka	Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Unai Martinez-Corral, Guillermo Callaghan, Konstantinos Iordanou, Cosmin Gorgovan, Koldo Basterretxea, Mikel Luján	DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle	Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach.	FPGA	2020	DBLP DOI BibTeX RDF
1	Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson	Combining Dynamic & Static Scheduling in High-level Synthesis.	FPGA	2020	DBLP DOI BibTeX RDF
1	Zhenhao He, Zeke Wang, Gustavo Alonso	BiS-KM: Enabling Any-Precision K-Means on FPGAs.	FPGA	2020	DBLP DOI BibTeX RDF
1	Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim	Productive Hardware Designs using Hybrid HLS-RTL Development.	FPGA	2020	DBLP DOI BibTeX RDF
1	Tuan D. A. Nguyen, Akash Kumar 0001	Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment.	FPGA	2020	DBLP DOI BibTeX RDF
1	Anish Singhani, Alexander Morrow	Real-Time Spatial 3D Audio Synthesis on FPGAs for Blind Sailing.	FPGA	2020	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk	R2CNN: Recurrent Residual Convolutional Neural Network on FPGA.	FPGA	2020	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis 0001, Panagiotis Skrimponis, Emmanouil Pissadakis, Sundeep Rangan, Dionisios N. Pnevmatikatos	Near-memory Acceleration for Scalable Phylogenetic Inference.	FPGA	2020	DBLP DOI BibTeX RDF
1	Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong	CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time.	FPGA	2020	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy 0001, Debbie Marr, Sergey Gribok, Bogdan Pasca 0001, Martin Langhammer, Aravind Dasu	Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.	FPGA	2019	DBLP DOI BibTeX RDF
1	Chris Lavin, Alireza Kaviani	Build Your Own Domain-specific Solutions with RapidWright: Invited Tutorial.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yu Xing, Shuang Liang 0010, Lingzhi Sui, Zhen Zhang, Jiantao Qiu, Xijie Jia, Xin Liu, Yushun Wang, Yi Shan, Yu Wang 0002	DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN Accelerators.	FPGA	2019	DBLP DOI BibTeX RDF
1	Zheming Jin, Hal Finkel	Base64 Encoding on OpenCL FPGA Platform.	FPGA	2019	DBLP DOI BibTeX RDF
1	Xin He, Liu Ke 0001, Xuan Zhang 0001	SparseBNN: Joint Algorithm/Hardware Optimization to Exploit Structured Sparsity in Binary Neural Network.	FPGA	2019	DBLP DOI BibTeX RDF
1	Jie Liu, Jason Cong	Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis.	FPGA	2019	DBLP DOI BibTeX RDF
1	David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic	FASED: FPGA-Accelerated Simulation and Evaluation of DRAM.	FPGA	2019	DBLP DOI BibTeX RDF
1	Martin Langhammer, Gregg Baeckler, Sergey Gribok	Fractal Synthesis: Invited Tutorial.	FPGA	2019	DBLP DOI BibTeX RDF
1	Stephen Ibanez, Gordon J. Brebner, Nick McKeown, Noa Zilberman	The P4->NetFPGA Workflow for Line-Rate Packet Processing.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yifan Yang, Qijing Huang 0001, Bichen Wu, Tianjun Zhang, Liang Ma 0003, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer	Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Sahithi Rampalli, Natasha Sehgal, Ishita Bindlish, Tanya Tyagi, Pawan Kumar 0001	Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS.	FPGA	2019	DBLP DOI BibTeX RDF
1	Zhe Chen, Hugh T. Blair, Jason Cong	LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization.	FPGA	2019	DBLP DOI BibTeX RDF
1	Fan Yang, Zhan Wang, Xiaoxiao Ma 0004, Guojun Yuan, Xuejun An	SwitchAgg: A Further Step Towards In-Network Computation.	FPGA	2019	DBLP DOI BibTeX RDF
1	Nima Karimpour Darav, Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu	Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer.	FPGA	2019	DBLP DOI BibTeX RDF
1	Ramtin Zand, Ronald F. DeMara	HSC-FPGA.	FPGA	2019	DBLP DOI BibTeX RDF
1	Kia Bazargan, Stephen Neuendorffer (eds.)	Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019	FPGA	2019	DBLP DOI BibTeX RDF
1	Liang Feng 0001, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang 0012	A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.	FPGA	2019	DBLP DOI BibTeX RDF
1	Hui Yan, Zhaoshi Li, Leibo Liu, Shouyi Yin, Shaojun Wei	Constructing Concurrent Data Structures on FPGA with Channels.	FPGA	2019	DBLP DOI BibTeX RDF
1	Sahan Bandara, Alan Ehret, Donato Kava, Michel A. Kinsy	BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yanjie Gu, Jian Yu, Tieli Sun, Chen Pan, Zhenhao Feng, Liewei Xu, Chang Wu	Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions.	FPGA	2019	DBLP DOI BibTeX RDF
1	Weijie You, Chang Wu	A Reconfigurable Accelerator for Sparse Convolutional Neural Networks.	FPGA	2019	DBLP DOI BibTeX RDF
1	Weiwen Jiang, Xinyi Zhang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Lei Yang 0018, Yiyu Shi 0001, Jingtong Hu	XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI.	FPGA	2019	DBLP DOI BibTeX RDF
1	Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang 0036, Jinmei Lai	Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits.	FPGA	2019	DBLP DOI BibTeX RDF
1	Deming Chen	FPGAs in Supercomputers: Opportunity or Folly?	FPGA	2019	DBLP DOI BibTeX RDF
1	Feng Shi 0006, Haochen Li, Yuhe Gao, Benjamin Kuschner, Song-Chun Zhu	Sparse Winograd Convolutional Neural Networks on Small-scale Systolic Arrays.	FPGA	2019	DBLP DOI BibTeX RDF
1	Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow	A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center.	FPGA	2019	DBLP DOI BibTeX RDF
1	Sajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau	AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yun Zhou, Dries Vercruyce, Dirk Stroobandt	MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement.	FPGA	2019	DBLP DOI BibTeX RDF
1	Sebastian Vogel, Jannik Springer, Andre Guntoro, Gerd Ascheid	Efficient Acceleration of CNNs for Semantic Segmentation on FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Shanquan Tian, Jakub Szefer	Temporal Thermal Covert Channels in Cloud FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF

Publications at "FPGA"( http://dblp.L3S.de/Venues/FPGA )