Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres	A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.	FPL	2011	DBLP DOI BibTeX RDF	ElectroMagnetic Analysis (EMA), Process Characterisation, Field-Programmable Gate Arrays (FPGAs), Ring Oscillator
25	Frantz Iwu	Scalable Fualt Detection for FPGAs.	HASE	2010	DBLP DOI BibTeX RDF	FPGAs, Analysis, Component-based design
25	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
25	Adrian Ludwin, Vaughn Betz, Ketan Padalia	High-quality, deterministic parallel placement for FPGAs on commodity hardware.	FPGA	2008	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement
25	Paulo Sérgio Brandão do Nascimento, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Abner Corrêa Barros, Manoel Eusébio de Lima	A Temporal Partitioning Methodology for Reconfigurable High Performance Computers.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable Computers, Temporal Partitioning
25	Juan Antonio Clemente, Carlos González 0002, Javier Resano, Daniel Mozos	A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems.	ReConFig	2008	DBLP DOI BibTeX RDF	Hardware multitasking, FPGAs, Reconfigurable architectures, Task scheduling
25	Zobeida Jezabel Guzman-Zavaleta, Claudia Feregrino Uribe, René Cumplido	A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation.	ReConFig	2008	DBLP DOI BibTeX RDF	Radiological Medical Images, FPGAs, Hardware Implementation, Reversible Data Hiding
25	Tom Degryse, Karel Bruneel, Harald Devos, Dirk Stroobandt	Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead.	ReConFig	2008	DBLP DOI BibTeX RDF	Dynamic hardware generation, FPGAs, Matrix multiplications, Loop transformations
25	Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson	Challenges and Promising Results in NoC Prototyping Using FPGAs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	FPGAs, interconnection network, network on chip, computer systems organization, computer system implementation
25	Heidi E. Ziegler, Mary W. Hall	Evaluating heuristics in automatically mapping multi-loop applications to FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	high-level and architectural synthesis, parallelizing compiler analysis techniques, synthesis techniques for configurable computing, FPGAs, pipelining, rapid prototyping, hardware design
25	Oskar Mencer, Wayne Luk	Parameterized High Throughput Function Evaluation for FPGAs.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	FPGAs, function approximation, CORDIC, lookup table, rational approximation
25	Jason Helge Anderson, Farid N. Najm, Tim Tuan	Active leakage power optimization for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	optimization, FPGAs, field-programmable gate arrays, low-power design, power, leakage
25	Jason Helge Anderson, Farid N. Najm	Switching activity analysis and pre-layout activity prediction for FPGAs.	SLIP	2003	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, power, estimation
25	Pedro C. Diniz, Joonseok Park	Data reorganization engines for the next generation of system-on-a-chip FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
25	Douglas Chang, Malgorzata Marek-Sadowska	Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Dynamically reconfigurable FPGAs, time-mulitplexed FPGA, Dharma, DPGA, field programmable gate array, partitioning, reconfigurable computing, sequential circuit, force directed scheduling
25	José Carlos Alves, João Canas Ferreira, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos	FAFNER-Accelerating Nesting Problems with FPGAs.	FCCM	1999	DBLP DOI BibTeX RDF	Custom computing, nesting problems, FPGAs
25	Zeljko Zilic, Zvonko G. Vranesic	Using Decision Diagrams to Design ULMs for FPGAs.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	ULMs, classification of logic functions, synthesis of logic functions, FPGAs, BDDs
25	Peichen Pan, C. L. Liu 0001	Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance.	FPGA	1996	DBLP DOI BibTeX RDF	FPGAs, sequential circuits, retiming, technology mapping, look-up table, logic replication, clock period
25	Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami	A fast-multiplier generator for FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips
23	Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta	High-performance, energy-efficient platforms using in-socket FPGA accelerators.	FPGA	2009	DBLP DOI BibTeX RDF	in-socket accelerator, fpga, agility
23	Falk Salewski, Stefan Kowalewski	Hardware/Software Design Considerations for Automotive Embedded Systems.	IEEE Trans. Ind. Informatics	2008	DBLP DOI BibTeX RDF
23	Ling Zhuo, Viktor K. Prasanna	Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
23	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck	Fpga-based data acquisition system for a positron emission tomography (PET) scanner.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, positron emission tomography
23	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst	Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.	FPL	2008	DBLP DOI BibTeX RDF
23	Pongstorn Maidee, Nagib Hakim, Kia Bazargan	FPGA family composition and effects of specialized blocks.	FPL	2008	DBLP DOI BibTeX RDF
23	John Curreri, Seth Koehler, Brian Holland, Alan D. George	Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing.	FCCM	2008	DBLP DOI BibTeX RDF
23	Sandeep S. Kumar, Jorge Guajardo, Roel Maes, Geert Jan Schrijen, Pim Tuyls	The Butterfly PUF: Protecting IP on every FPGA.	HOST	2008	DBLP DOI BibTeX RDF
23	Jin Cui, Zonghua Gu 0001, Weichen Liu, Qingxu Deng	An Efficient Algorithm for Online Soft Real-Time Task Placement on Reconfigurable Hardware Devices.	ISORC	2007	DBLP DOI BibTeX RDF
23	Abdel Ejnioui	FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline.	ISVLSI	2007	DBLP DOI BibTeX RDF
23	Shiv Balakrishnan, Chris Eddington	Efficient DSP algorithm development for FPGA and ASIC technologies.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
23	Nan Guan, Zonghua Gu 0001, Qingxu Deng, Weichen Liu, Ge Yu 0001	Improved Schedulability Analysis of EDF Scheduling on Reconfigurable Hardware Devices.	IPDPS	2007	DBLP DOI BibTeX RDF
23	Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong	FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.	FPL	2006	DBLP DOI BibTeX RDF
23	Young-Su Kwon, Chong-Min Kyung	Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
23	Roman L. Lysecky, Frank Vahid	A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.	DATE	2005	DBLP DOI BibTeX RDF
23	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A function generator-based reconfigurable system.	ASP-DAC	2005	DBLP DOI BibTeX RDF
23	Marcelo Götz, Achim Rettberg, Carlos Eduardo Pereira	A Run-Time Partitioning Algorithm for RTOS on Reconfigurable Hardware.	EUC	2005	DBLP DOI BibTeX RDF
23	Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano	Structured/platform ASIC apprentices: which platform will survive your board room?	DAC	2005	DBLP DOI BibTeX RDF	programmable ASIC platforms, digital design
23	François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel	Power Analysis Attacks Against FPGA Implementations of the DES.	FPL	2004	DBLP DOI BibTeX RDF
23	Heiko Kalte, Mario Porrmann, Ulrich Rückert 0001	System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement.	IPDPS	2004	DBLP DOI BibTeX RDF
23	Keith D. Underwood, K. Scott Hemmert	Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance.	FCCM	2004	DBLP DOI BibTeX RDF	IEEE floating point, re-configurable computing, FPGA, arithmetic
23	Kees A. Vissers	Programming models and architectures for FPGA platforms.	CASES	2004	DBLP DOI BibTeX RDF
23	Fei Li 0003, Yan Lin 0001, Lei He 0001	FPGA power reduction using configurable dual-Vdd.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, low power, configurable, power efficient, dual-Vdd
23	Shih-Lien Lu, Konrad Lai	Implementation of HW$im - A Real-Time Configurable Cache Simulator.	FPL	2003	DBLP DOI BibTeX RDF
23	Siddika Berna Örs, Elisabeth Oswald, Bart Preneel	Power-Analysis Attacks on an FPGA - First Experimental Results.	CHES	2003	DBLP DOI BibTeX RDF
23	Patrick Lysaght	Field Programmable Systems.	HiPC	2002	DBLP DOI BibTeX RDF
23	Reiner W. Hartenstein	Reconfigurable Computing: A New Business Model and its Impact on SoC Design.	DSD	2001	DBLP DOI BibTeX RDF
23	Artur Chojnacki, Lech Józwiak	High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures.	ISQED	2001	DBLP DOI BibTeX RDF
23	Hyun-Kyu Yun, Aaron Smith, Harvey F. Silverman	Speech recognition HMM training on reconfigurable parallel processor.	FCCM	1997	DBLP DOI BibTeX RDF
23	Vaughn Betz, Jonathan Rose	Using Architectural "Families" to Increase FPGA Speed and Density.	FPGA	1995	DBLP DOI BibTeX RDF
21	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
21	Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	mtbf, fpga, metastability
21	Kuen Hung Tsoi, Wayne Luk	Axel: a heterogeneous cluster with FPGAs and GPUs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, heterogeneous cluster
21	Kaveh Elizeh, Nicola Nicolici	Embedded memory binding in FPGAs.	DAC	2010	DBLP DOI BibTeX RDF	FPGA, memory, binding
21	Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung	Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	2D filter design, FPGA, Singular Value Decomposition, reconfigurable logic
21	Tian Song, Dongsheng Wang 0002, Zhizhong Tang	A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	network intrusion prevention, network security, pattern matching, network intrusion detection
21	Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu	N-port memory mapping for LUT-based FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	logical-to-physical mapping, n-port memory, fpga, hierarchy
21	Cristinel Ababei	Parallel placement for FPGAs revisited.	FPGA	2009	DBLP DOI BibTeX RDF	fpga placement, multithreading, parallel simulated annealing
21	Christopher T. Johnston, Paul J. Lyons, Donald G. Bailey	User evaluation and overview of a visual language for real time image processing on FPGAs.	CHINZ	2009	DBLP DOI BibTeX RDF	FPGA, image processing, visual programming language, HDL
21	Julien Lamoureux, Tony Field, Wayne Luk	Accelerating a Virtual Ecology Model with FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF
21	Shantanu Dutt, Vinay Verma, Vishal Suthar	Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
21	Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Gian Carlo Cardarilli, Fabrizio Lombardi, Adelio Salsano	Analysis and Evaluations of Reliability of Reconfigurable FPGAs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	FPGA, Reliability, Fault model, Defect tolerance
21	Daniel Ziener, Jürgen Teich	Power Signature Watermarking of IP Cores for FPGAs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	IPP, FPGA, watermarking, signature, power analysis, IP cores
21	Leos Kafka	Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs.	DDECS	2008	DBLP DOI BibTeX RDF
21	Kostas Siozios, Dimitrios Soudris	An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.	PATMOS	2008	DBLP DOI BibTeX RDF	P? CAD Algorithm, FPGA, Management, Power, 3D
21	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, routing, variation, yield enhancement
21	Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001	Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs.	DATE	2008	DBLP DOI BibTeX RDF
21	Etienne Bergeron, Marc Feeley, Jean-Pierre David	Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs.	CC	2008	DBLP DOI BibTeX RDF
21	L. Musa	FPGAS in high energy physics experiments at CERN.	FPL	2008	DBLP DOI BibTeX RDF
21	Martin Langhammer	Floating point datapath synthesis for FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
21	Ahmad Sghaier, Shawki Areibi, Robert D. Dony	IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration.	FPL	2008	DBLP DOI BibTeX RDF
21	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
21	Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer	Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.	ISPASS	2008	DBLP DOI BibTeX RDF
21	Günter Knittel	Pipelined Bus-Invert Coding for FPGAs Driving High-Speed DDR-Channels.	ITNG	2008	DBLP DOI BibTeX RDF	Bus-Invert Coding, Dual-Data-Rate, FPGA
21	Hooman Shayani, Peter J. Bentley, Andy M. Tyrrell	A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs.	ICES	2008	DBLP DOI BibTeX RDF	Dendrite and Axon Growth, Synapse Formation, Digital Spiking Neuron Model, FPGA, Evolvable Hardware, Cellular
21	Falk Salewski, Stefan Kowalewski	The effect of real-time software reuse in FPGAs and microcontrollers with respect to software faults.	SIES	2008	DBLP DOI BibTeX RDF
21	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk	Global interconnections in FPGAs: modeling and performance analysis.	SLIP	2008	DBLP DOI BibTeX RDF	FPGA, throughput, interconnection, wave-pipelined
21	Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser	MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs.	ESTIMedia	2008	DBLP DOI BibTeX RDF
21	Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao	Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs.	ICCD	2008	DBLP DOI BibTeX RDF
21	Massimo Alioto, Luca Fondelli, Santina Rocchi	Analysis and performance evaluation of area-efficient true random bit generators on FPGAs.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Jie Shao, Ning Ye, Xiao-Yan Zhang	An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.	CSSE (4)	2008	DBLP DOI BibTeX RDF
21	Waleed K. Al-Assadi, Sindhu Kakarla	A BIST Technique for Crosstalk Noise Detection in FPGAs.	DFT	2008	DBLP DOI BibTeX RDF
21	Jason Meyer, Fatih Kocan	Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	K. Scott Hemmert, Keith D. Underwood	Floating-Point Divider Design for FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow	Routability of Network Topologies in FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Chang Woo Kang, Ali Iranli, Massoud Pedram	A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Eze Kamanu, Pratapa Reddy, Kenneth Hsu, Marcin Lukowiak	A New Architecture for Single-Event Detection & Reconfiguration of SRAM-based FPGAs.	HASE	2007	DBLP DOI BibTeX RDF
21	Michael Hübner 0001, Lars Braun, Jürgen Becker 0001, Christopher Claus, Walter Stechele	Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.	ISVLSI	2007	DBLP DOI BibTeX RDF
21	Luca Sterpone, Massimo Violante	Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.	ETS	2007	DBLP DOI BibTeX RDF
21	Katarina Paulsson, Michael Hübner 0001, Günther Auer, Michael Dreschmann, Jürgen Becker 0001	Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
21	Jérémie Detrey, Florent de Dinechin	Floating-Point Trigonometric Functions for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
21	Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim Tuyls	Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection.	FPL	2007	DBLP DOI BibTeX RDF
21	Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz	RAMP Blue: A Message-Passing Manycore System in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
21	Walid A. Najjar	Compiling code accelerators for FPGAs.	CODES+ISSS	2007	DBLP DOI BibTeX RDF
21	Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.	ISLPED	2007	DBLP DOI BibTeX RDF	post-placement optimization, scheduling, field-programmable gate array, leakage
21	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Andrew McCormick	An Engineering Approach to Solving HPC Problems using FPGAs.	AHS	2007	DBLP DOI BibTeX RDF
21	Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio	SEU mitigation for sram-based fpgas through dynamic partial reconfiguration.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault detection, SEU, partial dynamic reconfiguration
21	Steven Trimberger	Trusted Design in FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
21	Oskar Mencer	ASC: a stream compiler for computing with FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Jason A. Cheatham, John Marty Emmert, Stanley Baumgart	A survey of fault tolerant methodologies for FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	fault tolerance, FPGA, self test