Search results for "PI-Bus"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Kei Hirose, Hiroto Yasuura	A Bus Delay Reduction Technique Considering Crosstalk.	DATE	2000	DBLP DOI BibTeX RDF
36	A. V. Hariharakrishnan, Simon Johney	Validation Platform for a P1394a OHCI-Link Layer Synthesizable Core (With a PCI Bus Interface).	EUROMICRO	2000	DBLP DOI BibTeX RDF
36	Vijay Sundararajan, Keshab K. Parhi	Reducing bus transition activity by limited weight coding with codeword slimming.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
36	Marios G. Scottis, Marwan Krunz, Max M.-K. Liu	Enhancing the PCI bus to support real-time streams.	IPCCC	1999	DBLP DOI BibTeX RDF
36	Constantine Katsinis	Performance Analysis and Simulation of the SOME-Bus Architecture Using Message Passing.	ICCCN	1998	DBLP DOI BibTeX RDF	simulation, performance analysis, Interconnection networks
36	Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki	A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor.	HPCA	1996	DBLP DOI BibTeX RDF
36	Biswanath Mukherjee	Performance of a Dual-Bus Unidirectional Broadcast Network Operating Under a Probabilistic Scheduling Strategy.	SIGMETRICS	1989	DBLP DOI BibTeX RDF
36	Susan J. Eggers, Randy H. Katz	The Effect of Sharing on the Cache and Bus Performance of Parallel Programs.	ASPLOS	1989	DBLP DOI BibTeX RDF
35	Satoshi Komatsu, Masahiro Fujita	An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Deni Torres, J. Gonzalez, Manuel Guzman, L. Nuñez	A new bus assignment in a designed shared bus switch fabric.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
33	Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan, Srimat T. Chakradhar	SECA: security-enhanced communication architecture.	CASES	2005	DBLP DOI BibTeX RDF	AMBA Bus, security-aware design, small embedded systems, security, communication, access control, architecture, intrusion detection, system-on-chip (SoC), attacks, bus, digital rights management (DRM)
33	Pi-Rong Sheu, Charng-Maw Lin	A fast optimal slot reuse scheme for CRMA high speed networks.	LCN	1997	DBLP DOI BibTeX RDF	CRMA high speed networks, cyclic-reservation multiple-access, fast optimal slot reuse scheme, high-speed local area networks, high-speed metropolitan area networks, folded-bus configurations, dual-bus configurations, reserve command generation, empty slots reservation, average cycle length, average throughput, average MAC delay, performance measurements, time complexity, computer simulations, NP-complete problem, metropolitan area networks, access delay
32	Ying Zhang 0040, Huawei Li 0001, Xiaowei Li 0001, Yu Hu 0001	Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.	VTS	2008	DBLP DOI BibTeX RDF	Codeword Selection, Crosstalk Avoidance, Reliable Bus
32	Dimitrios Lymberopoulos, Nissanka Bodhi Priyantha, Feng Zhao 0001	mPlatform: a reconfigurable architecture and efficient data sharing mechanism for modular sensor nodes.	IPSN	2007	DBLP DOI BibTeX RDF	high speed data bus, reconfigurable sensor node, CPLD, modular architecture
32	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for system-on-chip networks: a unified framework.	DAC	2004	DBLP DOI BibTeX RDF	bus coding, crosstalk avoidance, low-power, error-correcting codes, low-swing
32	Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai	Compiler optimization on VLIW instruction scheduling for low power.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers
32	Michael Gasteier, Manfred Glesner	Bus-based communication synthesis on system level.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	bus generation, bus without arbitration, statically scheduled systems, transfer scheduling, communication synthesis
32	Yean-Shiang Leu, David Hung-Chang Du	Cycle Compensation Protocol: A Fair Protocol for the Unidirectional Twin-Bus Architecture.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	cycle compensation protocol, fair protocol, unidirectional twin-bus architecture, IEEE 802.6 Standard, Distributed Queue Dual Bus, channel bandwidth, unfairness problem, protocols, standards, local area networks, metropolitan area networks, metropolitan area networks, channel utilization
32	Jie-Yong Juang, Benjamin W. Wah	A Contention-Based Bus-Control Scheme for Multiprocessor Systems.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	bus-control schemes, scheduling processors, scheduling, computational complexity, multiprocessor interconnection networks, multiprocessing systems, contention-based, bit-parallel, shared bus
32	Giovanni Chiola, Marco Ajmone Marsan, Gianfranco Balbo	Product-Form Solution Techniques for the Performance Analysis of Multiple-Bus Multiprocessor Systems with Nonuniform Memory References.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	local balance property, multiple-bus multiprocessor systems, nonuniform memory references, steady-state probability distribution, queuing models with passive resources, recursive solution, processor access rates, memory selection probabilities, first-come-first-served bus scheduling policy, scheduling, performance evaluation, performance analysis, multiprocessor interconnection networks, queueing theory, numerical analysis, product-form solution, exact computation
32	Haklin Kimm, Sung Y. Shin, Ho-sang Ham, Chang Oan Sung	Failure management development for integrated automotive safety-critical software systems.	SAC	2009	DBLP DOI BibTeX RDF
32	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.	ISCA	2009	DBLP DOI BibTeX RDF	bandwidth decoupling, decoupled DIMM, DRAM memories
32	Gunar Schirner, Rainer Dömer	Quantitative analysis of the speed/accuracy trade-off in transaction level modeling.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	system-on-chip, System level design, transaction level modeling
32	T. Venkata Kalyan, Madhu Mutyam, Vijaya Sankara Rao Pasupureddi	Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
32	Prassanna Sithambaram, Alberto Macii, Enrico Macii	New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.	PATMOS	2007	DBLP DOI BibTeX RDF
32	M. Omar Faruque Sarker, ChangHwan Kim, Seungheon Back, Bum-Jae You	An IEEE-1394 Based Real-time Robot Control System for Efficient Controlling of Humanoids.	IROS	2006	DBLP DOI BibTeX RDF
32	Federico Rota, Shantanu Dutt, Sahithi Krishna	Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream.	DFT	2006	DBLP DOI BibTeX RDF
32	Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001	Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
32	Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
32	Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu	Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding.	ISMVL	2004	DBLP DOI BibTeX RDF
32	Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001	Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.	ISLPED	2004	DBLP DOI BibTeX RDF
32	E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi	Power Comparison of Throughput Optimized IC Busses.	ISVLSI	2003	DBLP DOI BibTeX RDF
32	K. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir	Power protocol: reducing power dissipation on off-chip data buses.	MICRO	2002	DBLP DOI BibTeX RDF
32	Flavien Balbo, Suzanne Pinson	Toward a Multi-agent Modelling Approach for Urban Public Transportation Systems.	ESAW	2001	DBLP DOI BibTeX RDF	Multi-agent system, interaction, Decision Support System, dynamic systems, environment, transportation system
32	Diana Hecht, Constantine Katsinis	Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
32	Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou	Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing.	IJCNN (4)	2000	DBLP DOI BibTeX RDF
31	Ana Carolina Olivera, Mariano Frutos, Jessica Andrea Carballido, Ignacio Ponzoni, Nélida Beatriz Brignole	Bus Network Scheduling Problem: GRASP + EAs with PISA * Simulation.	IWANN (1)	2009	DBLP DOI BibTeX RDF	Memetic Evolutionary Algorithms, Bus-Network Scheduling Problem, PISA, Optimization
31	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based communication architectures at the CCATB abstraction.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus
31	Dirk Krechel, Markus Hartbauer	The LENUS Master Patient Index: Combining Hospital Content Management with a Healthcare Service Bus.	CBMS	2008	DBLP DOI BibTeX RDF	master patient index, healthcare bus, enterprise content management
31	Günter Knittel	Pipelined Bus-Invert Coding for FPGAs Driving High-Speed DDR-Channels.	ITNG	2008	DBLP DOI BibTeX RDF	Bus-Invert Coding, Dual-Data-Rate, FPGA
31	Yi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang	A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer.	DAC	2008	DBLP DOI BibTeX RDF	AMBA AHB, backward trace, bus tracer, circular buffer, forward trace, compression
31	Oto Pobiecky, Ivan Kotuliak, Daniel Popa, Tülin Atmaca, Gérard Hébuterne	LOCOMOTIVE: A Hybrid Access Protocol for Bus-Based Passive Optical Networks.	MASCOTS	2007	DBLP DOI BibTeX RDF	Asynchronous optical CSMA/CA, variable length packet, bandwidth fragmentation performance, shared bus
31	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	bit transitions, bus-encoding scheme, high impedance state, simultaneous switching noise (SSN), spatial and temporal redundancy, low power, delay, encoder, decoder, crosstalk noise, inductive coupling
31	Tarek Guesmi, Houria Rezig	Design and implementation of a real-time notification service within the context of embedded ORB and the CAN bus.	SAC	2006	DBLP DOI BibTeX RDF	embedded ORB, priority queuing, real-time CORBA, notification service, CAN bus
31	Mohammad Reza Selim, Takumi Endo, Yuichi Goto, Jingde Cheng	A Comparative Study Between Soft System Bus and Traditional Middlewares.	OTM Workshops (2)	2006	DBLP DOI BibTeX RDF	Soft System Bus, Data/Instruction Station, Middleware
31	Donghai Li, Guang-Sheng Ma, Gang Feng	Optimized Design of Interconnected Bus on Chip for Low Power.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF	self transition, coupled transition, interconnected bus, power optimization
31	Sujan Pandey, Manfred Glesner	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.	DAC	2006	DBLP DOI BibTeX RDF	communication bus synthesis, voltage scaling
31	P. Subrahmanya, R. Manimegalai, V. Kamakoti 0001, Madhu Mutyam	A Bus Encoding Technique for Power and Cross-talk Minimization.	VLSI Design	2004	DBLP DOI BibTeX RDF	Cross-talk, Limited Weight Codes, Transition Signalling, Encoding techniques, memoryless bus encoding, pipelining, Low Power Design
31	Vittorio Ricchiuti	Power Bus Signal Integrity Improvement and EMI Mitigation on Multilayer High-Speed Digital PCBs with Embedded Capacitance.	IEEE Trans. Mob. Comput.	2003	DBLP DOI BibTeX RDF	Embedded capacitance, power bus, power/ground layers, power supply decoupling, electric field strength, S-parameters
31	Vikram Iyengar, Krishnendu Chakrabarty	Test Bus Sizing for System-on-a-Chip.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Core-based systems, integer linear programming, linearization, test access mechanism (TAM), testing time, embedded core testing, test bus
31	Michele Favalli, Cecilia Metra	Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	bus based systems, on-line testing, two-rail checker
31	Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto	System-Level Design of IEEE1394 Bus Segment Bridge.	ISSS	2002	DBLP DOI BibTeX RDF	HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL
31	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	ALBORZ: Address Level Bus Power Optimization.	ISQED	2002	DBLP DOI BibTeX RDF	Low power bus encoding, limited-weight codes, codebook-based codes
31	Michael M. Gorlick	Electric Suspenders: A Fabric Power Bus and Data Network for Wearable Digital Devices.	ISWC	1999	DBLP DOI BibTeX RDF	conductive fabric, wearable power bus, PAN, personal area network
31	Horng-Ren Tsai, Shi-Jinn Horng, Shun-Shan Tsai, Tzong-Wann Kao, Shung-Shing Lee	Solving an Algebraic Path Problem and Some Related Graph Problems on a Hyper-Bus Broadcast Network.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Hyper-bus broadcast network, matrix multiplication operation, minimum-weight spanning tree, parallel algorithm, graph theory, connectivity, transitive closure, connected component, bridge, biconnected component, all-pair shortest paths, articulation point, algebraic path problem
31	Hossam A. ElGindy, Arun K. Somani, Heiko Schröder 0001, Hartmut Schmeck, Andrew Spray	RMB - A Reconfigurable Multiple Bus Network.	HPCA	1996	DBLP DOI BibTeX RDF	Reconfigurable Multiple Bus Network, Multiprocessor systems, Permutation Routing, Interconnection Structure
31	Shung-Shing Lee, Shi-Jinn Horng, Horng-Ren Tsai, Yu-Hua Lee	Some Image Processing Algorithms on a RAP with Wider Bus Networks.	IPPS	1996	DBLP DOI BibTeX RDF	wider bus networks, reconfigurable array of processors, base-m number system, parallel algorithms, parallel algorithms, image processing, image segmentation, image segmentation, parallel architectures, multiprocessor interconnection networks, reconfigurable architectures, histogram, system buses, computation power, image processing algorithms, image labeling, constant time, RAP
31	Edward David Moreno Ordonez, Sergio Takeo Kofuji	Performance evaluation of the fixed sequential prefetching on a bus-based multiprocessor: preliminary results.	ISPAN	1996	DBLP DOI BibTeX RDF	fixed sequential prefetching, bus-based multiprocessor, sequential prefetching, OBL policy, performance evaluation, performance evaluation, Petri nets, Petri nets, shared memory systems, shared memory systems, cache storage, data prefetching
31	Dean M. Tullsen, Susan J. Eggers	Effective Cache Prefetching on Bus-Based Multiprocessors	ACM Trans. Comput. Syst.	1995	DBLP DOI BibTeX RDF	bus-based multiprocessors, memory latency hiding, false sharing, cache prefetching
31	Jeffrey A. Floyd, Matt Perry	Real-time on-board bus testing.	VTS	1995	DBLP DOI BibTeX RDF	on-board bus testing, wide buses, computer buses, board layout, full-fault testing, multiple speeds, pseudo-random pattern generation, characteristic equations, IEEE JTAG protocol, real-time systems, protocols, logic testing, automatic testing, system buses, operating environments, multiple seed, clock speeds
31	Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng	Physical synthesis of bus matrix for high bandwidth low power on-chip communications.	ISPD	2010	DBLP DOI BibTeX RDF	wire efficiency, bandwidth, power efficiency
31	Khaled Z. Ibrahim, Smaïl Niar	Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
31	Guido Diepen, J. M. van den Akker, J. A. Hoogeveen	Integrated Gate and Bus Assignment at Amsterdam Airport Schiphol.	Robust and Online Large-Scale Optimization	2009	DBLP DOI BibTeX RDF	gate assigment, integrated planning, stabilized column generation, integer linear programming, column generation, airports
31	Hariharan Sankaran, Srinivas Katkoori	On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs.	ISQED	2009	DBLP DOI BibTeX RDF
31	Sujan Pandey, Rolf Drechsler	Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival.	ASP-DAC	2008	DBLP DOI BibTeX RDF
31	Charbel J. Akl, Magdy A. Bayoumi	Cost-effective and low-power memory address bus encodings.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.	VLSI Design	2008	DBLP DOI BibTeX RDF
31	Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang	A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
31	Colin D'Souza, Byung Hwa Kim, Richard M. Voyles	Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots.	ICRA	2007	DBLP DOI BibTeX RDF
31	Jakob Rosen, Alexandru Andrei, Petru Eles, Zebo Peng	Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.	RTSS	2007	DBLP DOI BibTeX RDF
31	Zhiming Zhao, Adam Belloum, Cees T. A. M. de Laat, Pieter W. Adriaans, Bob Hertzberger	Using Jade agent framework to prototype an e-Science workflow bus.	CCGRID	2007	DBLP DOI BibTeX RDF
31	Arash Ahmadi, Mark Zwolinski	Multiple-Width Bus Partitioning Approach to Datapath Synthesis.	ISCAS	2007	DBLP DOI BibTeX RDF
31	Daniele Rossi 0001, Carlo Steiner, Cecilia Metra	Analysis of the impact of bus implemented EDCs on on-chip SSN.	DATE	2006	DBLP DOI BibTeX RDF
31	Alexander Khitun, Kang L. Wang	Nano Logic Circuits with Spin Wave Bus.	ITNG	2006	DBLP DOI BibTeX RDF	logic devices, Spintronics, spin waves
31	Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim	A low power SoC bus with low-leakage and low-swing technique.	ISCAS	2006	DBLP DOI BibTeX RDF
31	Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen	Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context.	SAMOS	2005	DBLP DOI BibTeX RDF
31	Masaru Takesue	The Psi-Cube: A Bus-Based Cube-Type Network for High-Performance On-Chip Systems.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
31	Rung-Bin Lin	Coupling reduction analysis of bus-invert coding.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
31	Guillaume Gasser, Nathaniel D. Bird, Osama Masoud, Nikolaos Papanikolopoulos	Human Activities Monitoring at Bus Stops.	ICRA	2004	DBLP DOI BibTeX RDF
31	Nattawut Thepayasuwan, Alex Doboli	OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip.	ISVLSI	2004	DBLP DOI BibTeX RDF
31	Nikolaos D. Liveris, Prithviraj Banerjee	Power Aware Interface Synthesis for Bus-Based SoC Design.	DATE	2004	DBLP DOI BibTeX RDF
31	Liang Deng, Martin D. F. Wong	Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus.	DATE	2004	DBLP DOI BibTeX RDF
31	Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.	IPDPS	2004	DBLP DOI BibTeX RDF	Network-on-a-Chip, table-lookup routing, interconnection networks, Systems-on-a-Chip, streaming processing, on-chip interconnect, deterministic routing
31	Bongsoo Son, Hyung Jin Kim, Chi-Hyun Shin, Sang-Keon Lee	Bus Arrival Time Prediction Method for ITS Application.	KES	2004	DBLP DOI BibTeX RDF
31	Taehyung Park, Sangkeon Lee, Young-Jun Moon	Real Time Estimation of Bus Arrival Time under Mobile Environment.	ICCSA (1)	2004	DBLP DOI BibTeX RDF
31	Jiamin Zhao, Satish T. S. Bukkapatnam, Maged M. Dessouky	Distributed architecture for real-time coordination of bus holding in transit networks.	IEEE Trans. Intell. Transp. Syst.	2003	DBLP DOI BibTeX RDF
31	Osamu Ogawa, Sylvain Bayon de Noyer, Pascal Chauvet, Katsuya Shinohara, Yoshiharu Watanabe, Hiroshi Niizuma, Takayuki Sasaki, Yuji Takai	A Practical Approach for Bus Architecture Optimization at Transaction Level.	DATE	2003	DBLP DOI BibTeX RDF
31	Michela Bertolotto, Gregory M. P. O'Hare, Robin Strahan, Ailish Brophy, Alan N. Martin, Eoin McLoughlin	Bus Catcher: a Context Sensitive Prototype System for Public Transportation Users.	WISE Workshops	2002	DBLP DOI BibTeX RDF
31	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller 0001	A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission.	PATMOS	2002	DBLP DOI BibTeX RDF
31	Huifen Chen	Stochastic Optimization in Computing Multiple Headways for a Single Bus Line.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF	Flexible Tolerance Method, Multiple Headways, Retrospective Approximation, Retrospective Optimization, Stochastic Optimization
31	Desmond Rainsford, William A. Mackaness	Mobile Journey Planning for Bus Passengers.	GIScience	2002	DBLP DOI BibTeX RDF
31	Rung-Bin Lin, Chi-Ming Tsai	Weight-Based Bus-Invert Coding for Low-Power Applications.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
31	Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang	Narrow bus encoding for low-power DSP systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
31	Savio N. Chau, Joseph Smith, Ann T. Tai	A Design-Diversity Based Fault-Tolerant COTS Avionics Bus Network.	PRDC	2001	DBLP DOI BibTeX RDF
31	Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu	Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
31	Michael O. Sweeney	BUS: A Browser Based User Interface Service for Web Based Applications.	AUIC	2000	DBLP DOI BibTeX RDF	user interface service, user interface language, XML, web application, web engineering, web architecture
31	Shinya Ishihara, Seiichiro Tani, Atsushi Takahara	Virtual BUS: A Simple Implementation of an Effortless Networking System Based on PVM.	PVM/MPI	1999	DBLP DOI BibTeX RDF
31	Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Fast performance analysis of bus-based system-on-chip communication architectures.	ICCAD	1999	DBLP DOI BibTeX RDF
31	Atsushi Takahara, Seiichiro Tani, Shinya Ishihara, Toshiaki Miyazaki, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro	Virtual BUS: An Easy-to-Use Environment for Distributed Resources.	LCN	1999	DBLP DOI BibTeX RDF
31	Rakesh D. Barve, Elizabeth A. M. Shriver, Phillip B. Gibbons, Bruce Hillyer, Yossi Matias, Jeffrey Scott Vitter	Modeling and Optimizing I/O Throughput of Multiple Disks on a Bus (Summary).	SIGMETRICS	1998	DBLP DOI BibTeX RDF