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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1997 occurrences of 975 keywords
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Results
Found 1754 publication records. Showing 1754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Improved spill code generation for software pipelined loops. |
PLDI |
2000 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, register allocation, software pipelining, spill code |
28 | Johann Großschädl |
High-Speed RSA Hardware Based on Barret's Modular Reduction Method. |
CHES |
2000 |
DBLP DOI BibTeX RDF |
RSA algorithm, partial parallel multiplier, full-custom VLSI design, pipelining, Public-key cryptography, modular arithmetic |
28 | Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon |
Bounding Pipeline and Instruction Cache Performance. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache |
28 | Kei-Yong Khoo, Alan N. Willson Jr. |
Single-transistor transparent-latch clocking. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits |
28 | Luca Breveglieri, Luigi Dadda, Vincenzo Piuri |
Column Compression Pipelined Multipliers. |
ASAP |
1995 |
DBLP DOI BibTeX RDF |
pipelining, computer arithmetic, multipliers |
28 | Toshio Nakatani, Kemal Ebcioglu |
Making Compaction-Based Parallelization Affordable. |
IEEE Trans. Parallel Distributed Syst. |
1993 |
DBLP DOI BibTeX RDF |
compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc |
28 | Klaus D. Thalhofer, Karl D. Reinartz |
A Classification of Algorithms which Are Well Suited for Implementations on the DAP as a Basis for Further Research on Parallel Programming. |
CONPAR |
1986 |
DBLP DOI BibTeX RDF |
SIMD-principle, algorithm patterns, recursive doubling, binary decomposition, large scale pipelining, routing, Parallel programming, preprocessors |
25 | Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek |
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping |
25 | SangMin Shim, Soo-Mook Moon |
Split-path Enhanced Pipeline Scheduling for Loops with Control Flows. |
MICRO |
1998 |
DBLP DOI BibTeX RDF |
all-path pipelining, enhanced pipeline scheduling, initiation interval, multi-path loops, software pipelining, modulo scheduling |
25 | David Bernstein, Haran Boral, Ron Y. Pinter |
Optimal Chaining in Expression Trees. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
optimal chaining, vector instructions pipelining, explicit pipelining, expression trees, linear time scheduling algorithm, scheduling, computational complexity, parallel programming, dynamic programming, pipeline processing, automatic programming, automatic code generation, complexity analysis, Cray-1, dynamic programming algorithms |
23 | Jialu Huang, Arun Raman, Thomas B. Jablin, Yun Zhang 0005, Tzu-Han Hung, David I. August |
Decoupled software pipelining creates parallelization opportunities. |
CGO |
2010 |
DBLP DOI BibTeX RDF |
DSWP, enabling transformation, parallelization, multicore, speculation |
23 | Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon |
Pipelining Saturated Accumulation. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor P. Stefanov |
Flexible pipelining design for recursive variable expansion. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng |
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh |
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Mark Muir, Tughrul Arslan, Iain Lindsay |
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Zhikun Wang, Dan Feng 0001, Ke Zhou 0001, Fang Wang 0001 |
PCOW: Pipelining-Based COW Snapshot Method to Decrease First Write Penalty. |
GPC |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Yoonjin Kim, Rabi N. Mahapatra |
Reusable context pipelining for low power coarse-grained reconfigurable architecture. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba |
Clustered Decoupled Software Pipelining on Commodity CMP. |
ICPADS |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August |
Speculative Decoupled Software Pipelining. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Nan Wang, Azeez Sanusi, Peiyi Zhao, Shaheen Mohamed, Magdy A. Bayoumi |
PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Yoshiyuki Yamashita, Masato Tsuru |
Software Pipelining for Packet Filters. |
HPCC |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ricardo Menotti, Eduardo Marques, João M. P. Cardoso |
Aggressive Loop Pipelining for Reconfigurable Architectures. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Yong Dou, Jinhui Xu 0002, Guiming Wu |
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
cache-miss tolerance, prefetching, out-of-order execution, Runahead execution |
23 | Mario R. Casu, Luca Macchiarulo |
Floorplanning With Wire Pipelining in Adaptive Communication Channels. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala |
Software Pipelining Support for Transport Triggered Architecture Processors. |
SAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen |
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application. |
ICME |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Timothy M. McPhillips, Shawn Bowers |
An approach for pipelining nested collections in scientific workflows. |
SIGMOD Rec. |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Lin Qiao, Weitong Huang, Zhizhong Tang |
A Dynamic Data Dependence Analysis Approach for Software Pipelining. |
NPC |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August |
Automatic Thread Extraction with Decoupled Software Pipelining. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Yanjun Zhang, Hu He 0001, Yihe Sun |
A new register file access architecture for software pipelining in VLIW processors. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
23 | T. S. B. Sudarshan, Rahil Mir, S. Vijayalakshmi |
DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
Blowfish, inner loop pipeline, loop folding, four - tier architecture, Platform independent architecture, DRIL Architecture, replication, Dynamic reconfiguration |
23 | Laura Pozzi, Paolo Ienne |
Exploiting pipelining to relax register-file port constraints of instruction-set extensions. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
automatic instruction-set extension, constrained scheduling, embedded customised architectures, multi-cycle register access, input/output |
23 | Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska |
Pipelining Sequential Circuits with Wave Steering. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August |
Decoupled Software Pipelining with the Synchronization Array. |
IEEE PACT |
2004 |
DBLP DOI BibTeX RDF |
|
23 | François-Xavier Standaert, Siddika Berna Örs, Bart Preneel |
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? |
CHES |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating in-order stalls with "flea-flicker" two-pass pipelining. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo |
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Yiqun Zhu, Mohammed Benaissa |
Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Darin Petkov, Randolph E. Harr, Saman P. Amarasinghe |
Efficient Pipelining of Nested Loops: Unroll-and-Squash. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Elsie Nallipogu, Füsun Özgüner, Mario Lauria |
Improving the Throughput of Remote Storage Access through Pipelining. |
GRID |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Oswaldo Cadenas, Graham M. Megson |
Pipelining Considerations for an FPGA Case. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
23 | David Gregg |
Global Software Pipelining with Iteration Preselection. |
CC |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Smita Bakshi, Daniel D. Gajski |
Partitioning and pipelining for performance-constrained hardware/software systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Wei-Kai Cheng, Youn-Long Lin |
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. |
ACM Trans. Design Autom. Electr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
code generation, DSP |
23 | Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya |
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. |
ASYNC |
1998 |
DBLP DOI BibTeX RDF |
pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit |
23 | Vinoo Srinivasan, Ranga Vemuri |
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha |
Rotation scheduling: a loop pipelining algorithm. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Erik R. Altman, Guang R. Gao |
Optimal Software Pipelining Through Enumeration of Schedules. |
Euro-Par, Vol. II |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Steve Carr 0001, Chen Ding, Philip H. Sweany |
Improving Software Pipelining with Unroll-and-Jam. |
HICSS (1) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata |
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. |
ASAP |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao |
Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards. |
PLDI |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
Minimizing register requirements under resource-constrained rate-optimal software pipelining. |
MICRO |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Donald A. Joy, Maciej J. Ciesielski |
Clock period minimization with wave pipelining. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
23 | Evelyn Duesterwald, Rajiv Gupta 0001, Mary Lou Soffa |
Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables. |
CC |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Jan Hoogerbrugge, Henk Corporaal |
Comparing Software Pipelining for an Operation-Triggered and a Tarnsport-Triggered Architecture. |
CC |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Jean Duprat, Mario Fiallos Aguilar |
On the Simulation of Pipelining of Fully Digit On-Line Floating-Point Adder Networks on Massively Parallel Computers. |
CONPAR |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Reinhard J. Richter |
A Reconfigurable Interconnection Network for Flexible Pipelining. |
CONPAR |
1990 |
DBLP DOI BibTeX RDF |
|
23 | T. E. A. Lees |
Context streams a theoretical basis for a generic form of MIMD pipelining. |
SPDP |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita |
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. |
ISCA |
1989 |
DBLP DOI BibTeX RDF |
|
23 | Kemal Ebcioglu |
A compilation technique for software pipelining of loops with conditional jumps. |
MICRO |
1987 |
DBLP DOI BibTeX RDF |
|
23 | Douglas W. Clark |
Pipelining and Performance in the VAX 8800 Processor. |
ASPLOS |
1987 |
DBLP DOI BibTeX RDF |
VAX |
23 | C. V. Ramamoorthy, K. H. Kim |
Pipelining: the generalized concept and sequencing strategies. |
AFIPS National Computer Conference |
1974 |
DBLP DOI BibTeX RDF |
|
23 | Chun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, Meikang Qiu |
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Wei Dong 0002, Peng Li 0001, Xiaoji Ye |
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
parallel computing, multi-core, transient simulation |
23 | Suhyun Kim, Soo-Mook Moon |
Rotating Register Allocation for Enhanced Pipeline Scheduling. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Vinay Sriram, David Kearney |
A FPGA Implementation of Variable Kernel Convolution. |
PDCAT |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Alireza Hodjat, Ingrid Verbauwhede |
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
crypto-processor, security, VLSI, cryptography, Advanced Encryption Standard (AES), ASIC, hardware architectures |
23 | Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe |
Exploiting Vector Parallelism in Software Pipelined Loops. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija |
Architectural Considerations for Energy Efficiency. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Vidyasagar Nookala, Sachin S. Sapatnekar |
Designing optimized pipelined global interconnects: algorithms and methodology impact. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Mihai Budiu, Seth Copen Goldstein |
Optimizing Memory Accesses For Spatial Computation. |
CGO |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Loop fusion for clustered VLIW architectures. |
LCTES-SCOPES |
2002 |
DBLP DOI BibTeX RDF |
clustered VLIW architectures, loop fusion |
23 | Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura |
Scaling Up Of Wave Pipelines. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
23 | José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan |
A wave-pipelined router architecture using ternary associative memory. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt |
Statistical analysis of timing rules for high-speed synchronous VLSI systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Eric Stotzer, Ernst L. Leiss |
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture. |
Workshop on Languages, Compilers, and Tools for Embedded Systems |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Sung-Kwan Kim, Sang Lyul Min, Rhan Ha |
Analysis of the Impacts of Overestimation Sources on the Accuracy of Worst Case Timing Analysis. |
RTSS |
1999 |
DBLP DOI BibTeX RDF |
real-time systems, WCET analysis |
23 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Han-Saem Yun |
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. |
LCPC |
1999 |
DBLP DOI BibTeX RDF |
|
23 | S. Summerfield, Zhongfeng Wang, Keshab K. Parhi |
Area-power-time efficient pipeline-interleaved architectures for wave digital filters. |
ISCAS (3) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Cristina Barrado, Jesús Labarta |
Hamiltonian Recurrence for ILP. |
Euro-Par |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Mary Jane Irwin, Robert Michael Owens |
A case for digit serial VLSI signal processors. |
J. VLSI Signal Process. |
1990 |
DBLP DOI BibTeX RDF |
|
23 | François Bodin, François Charot |
Loop optimization for horizontal microcoded machines. |
ICS |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Krishna P. Mikkilineni, Stanley Y. W. Su |
An Evaluation of Relational Join Algorithms in a Pipelined Query Processing Environment. |
IEEE Trans. Software Eng. |
1988 |
DBLP DOI BibTeX RDF |
timing equations, relational join algorithms, pipelined query processing environment, nested block, sort-merge, pipelined sort-merge, performance evaluation, relational databases, relational databases, distributed processing, distributed databases, distributed databases, sorting, database theory, hash, pipeline processing, merging, query execution |
23 | Chung-Ta King, Wen-Hwa Chou, Lionel M. Ni |
Pipelined data parallel algorithms - concept and modeling. |
ICS |
1988 |
DBLP DOI BibTeX RDF |
|
23 | Shlomo Weiss, James E. Smith 0001 |
A Study of Scalar Compilation Techniques for Pipelined Supercomputers. |
ASPLOS |
1987 |
DBLP DOI BibTeX RDF |
|
20 | Eddy Z. Zhang, Yunlian Jiang, Ziyu Guo, Xipeng Shen |
Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping. |
ICS |
2010 |
DBLP DOI BibTeX RDF |
CPU-GPU pipelining, thread divergence, thread-data remapping, GPGPU, data transformation |
20 | Maxwell Walton, Gary Gréwal, Gerarda A. Darlington |
Parallel FPGA-based implementation of scatter search. |
GECCO |
2010 |
DBLP DOI BibTeX RDF |
0-1 knapsack problem, field programmable gate arrays, pipelining, hardware acceleration, data parallelism, scatter search |
20 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. |
LCTES |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
20 | Roger F. Woods, John V. McCanny, John G. McWhirter |
From Bit Level Systolic Arrays to HDTV Processor Chips. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
SoC architectures, DSP systems, pipelining, systolic arrays |
20 | Hongbo Rong, Alban Douillet, Guang R. Gao |
Register allocation for software pipelined multidimensional loops. |
ACM Trans. Program. Lang. Syst. |
2008 |
DBLP DOI BibTeX RDF |
register allocation, Software pipelining |
20 | Abhishek Das, William J. Dally |
Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies. |
Euro-Par |
2008 |
DBLP DOI BibTeX RDF |
Stream Scheduling, Bulk Operations, Sequoia, GSOP Memory Hierarchy, Tunables, Software Pipelining |
20 | Suhyun Kim, Soo-Mook Moon |
Rotating register allocation with multiple rotating branches. |
ICS |
2008 |
DBLP DOI BibTeX RDF |
rotating register, register allocation, software pipelining |
20 | Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee |
Enabling compiler flow for embedded VLIW DSP processors with distributed register files. |
LCTES |
2007 |
DBLP DOI BibTeX RDF |
distributed register files, embedded VLIW DSP compilers, software pipelining |
20 | Klaus Schöffmann, Markus Fauster, Oliver Lampl, László Böszörményi |
An Evaluation of Parallelization Concepts for Baseline-Profile Compliant H.264/AVC Decoders. |
Euro-Par |
2007 |
DBLP DOI BibTeX RDF |
Evaluation, Parallelization, Pipelining, H.264, Decoding, Multi-Threading, AVC |
20 | Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu |
Tolerating Cache-Miss Latency with Multipass Pipelines. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
Flea-flicker, multipass pipelining, memory-latency tolerance, in-order design |
20 | Abhishek Das, William J. Dally, Peter R. Mattson |
Compiling for stream processing. |
PACT |
2006 |
DBLP DOI BibTeX RDF |
SRF allocation, Stream Operation Precedence (SOP) graph, StreamC, coarse-grained operations, producer-consumer locality, scoreboard slot assignment, stream scheduling, strip-mining, software-pipelining, task level parallelism, stream programming model |
20 | Peter Sanders 0001, Jesper Larsson Träff |
Parallel Prefix (Scan) Algorithms for MPI. |
PVM/MPI |
2006 |
DBLP DOI BibTeX RDF |
MPI implementation, pipelining, collective communication, prefix sum, Cluster of SMPs |
20 | Genhua Jin, Hyuk-Jae Lee |
A Parallel and Pipelined Execution of H.264/AVC Intra Prediction. |
CIT |
2006 |
DBLP DOI BibTeX RDF |
block processing order, pipelining, H.264, parallel execution, Intra prediction |
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