Search results for "RAMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li 0001	Area and reliability efficient ECC scheme for 3D RAMs.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
19	Yun-Chao You, Che-Wei Chou, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu	A built-in self-test scheme for 3D RAMs.	ITC	2012	DBLP DOI BibTeX RDF
19	Sven Gerber, Sandra Gerber, Peter Krüger, Hans-Knud Arndt	"Good Design is Environmentally-Friendly." - Discussion of Rams' Principle in Context of the Software Life Cycle.	EnviroInfo	2012	DBLP BibTeX RDF
19	Ioannis Voyiatzis, Costas Efstathiou, Said Hamdioui, Cleo Sgouropoulou	ALU based address generation for RAMs.	DTIS	2012	DBLP DOI BibTeX RDF
19	Tsu-Wei Tseng, Jin-Fu Li 0001	A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
19	Luis M. Contreras 0001, Carlos Jesus Bernardos, Ignacio Soto	RAMS: A Protocol Extension to PMIPv6 for Improving Handover Performance of Multicast Traffic.	J. Wirel. Mob. Networks Ubiquitous Comput. Dependable Appl.	2011	DBLP DOI BibTeX RDF
19	Chih-Sheng Hou, Jin-Fu Li 0001, Tsu-Wei Tseng	Memory Built-in Self-Repair Planning Framework for RAMs in SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
19	Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger	Efficient Dual-Rail Implementations in FPGA Using Block RAMs.	ReConFig	2011	DBLP DOI BibTeX RDF
19	Chun-Yuan Cheng, Min Wang, Bee Leng Lee	The impacts of common cause failures for two-unit parallel systems from RAMS+C point of view.	IEEM	2011	DBLP DOI BibTeX RDF
19	Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li 0001	DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
19	Miklós Ajtai	Oblivious RAMs without Cryptographic Assumptions.	Electron. Colloquium Comput. Complex.	2010	DBLP BibTeX RDF
19	Paul Beame, Widad Machmouchi	Making RAMs Oblivious Requires Superlogarithmic Overhead.	Electron. Colloquium Comput. Complex.	2010	DBLP BibTeX RDF
19	Tsu-Wei Tseng, Jin-Fu Li 0001, Chih-Sheng Hou	A Built-in Method to Repair SoC RAMs in Parallel.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF
19	Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya	A behavioral model of unipolar resistive RAMs and its application to HSPICE integration.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
19	Petr Böhm, Thomas Gruber 0004	A Novel HAZOP Study Approach in the RAMS Analysis of a Therapeutic Robot for Disabled Children.	SAFECOMP	2010	DBLP DOI BibTeX RDF
19	Shaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, David Hwang	Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
19	Rajesh Velegalati, Jens-Peter Kaps	Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic.	ICECS	2010	DBLP DOI BibTeX RDF
19	Kazue Yasuoka, Atsushi Watabe, Tetsunori Hattori, Masayuki Matsumoto	The Policy of applying RAMS to evaluate Railway Signalling Systems for reliable Transportation.	FORMS/FORMAT	2010	DBLP DOI BibTeX RDF
19	Shigeto Hiraguri, Koji Iwata, Ikuo Watanabe	A Method of Evaluating Railway Signalling System Based on RAMS Concept.	FORMS/FORMAT	2010	DBLP DOI BibTeX RDF
19	Yu-Jen Huang, Yun-Chao You, Jin-Fu Li 0001	Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs.	SoCC	2010	DBLP DOI BibTeX RDF
19	Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen	Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.	DFT	2010	DBLP DOI BibTeX RDF
19	Chih-Sheng Hou, Jin-Fu Li 0001, Che-Wei Chou	Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs.	DELTA	2010	DBLP DOI BibTeX RDF	test, test scheduling, repair, RAM, built-in self-repair
19	A. C. Torres-Echeverría, Sebastián Martorell, Haydn A. Thompson	Design optimization of a safety-instrumented system based on RAMS+C addressing IEC 61508 requirements and diverse redundancy.	Reliab. Eng. Syst. Saf.	2009	DBLP DOI BibTeX RDF
19	Mary Ann Lundteigen, Marvin Rausand, Ingrid Bouwer Utne	Integrating RAMS engineering and management with the safety life cycle of IEC 61508.	Reliab. Eng. Syst. Saf.	2009	DBLP DOI BibTeX RDF
19	Markus Püschel, Peter A. Milder, James C. Hoe	Permuting streaming data using RAMs.	J. ACM	2009	DBLP DOI BibTeX RDF	data reordering, linear bit mapping, streaming datapath, stride permutation, Permutation, switch, RAM, connection network, matrix transposition
19	Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min	Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
19	Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min, Sung-Mo Kang	A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
19	Korefumi Tashiro, Masayuki Matsumoto	Comparison of documents of an Automatic Train Protection system project with RAMS standard.	ISADS	2009	DBLP DOI BibTeX RDF
19	Yu-Jen Huang, Jin-Fu Li 0001	Testability Exploration of 3-D RAMs and CAMs.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
19	Tamas Györfi, Octavian Cret, Alin Suciu	High performance true random number generator based on FPGA block RAMs.	IPDPS	2009	DBLP DOI BibTeX RDF
19	Junseok Park, Hyokyung Bahn, Kern Koh	Buffer Cache Management for Combined MLC and SLC Flash Memories Using both Volatile and Nonvolatile RAMs.	RTCSA	2009	DBLP DOI BibTeX RDF
19	Tim Güneysu, Christof Paar	Transforming write collisions in block RAMs into security applications.	FPT	2009	DBLP DOI BibTeX RDF
19	Petr Böhm, Thomas Gruber 0004	RAMS Analysis of a Bio-inspired Traffic Data Sensor ("Smart Eye").	EUROMICRO-SEAA	2009	DBLP DOI BibTeX RDF
19	Hsing-Chen Lu, Jin-Fu Li 0001	A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC.	ISCAS	2009	DBLP DOI BibTeX RDF
19	Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon	On the Use of Magnetic RAMs in Field-Programmable Gate Arrays.	Int. J. Reconfigurable Comput.	2008	DBLP DOI BibTeX RDF
19	Ioannis Voyiatzis	An ALU-Based BIST Scheme for Word-Organized RAMs.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Memory control and access, Reliability, Test generation, Built-In Tests, Testing and Fault-Tolerance, Semiconductor Memories
19	Yu-Jen Huang, Jin-Fu Li 0001	A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips.	ATS	2008	DBLP DOI BibTeX RDF
19	Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara	An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.	ISSCC	2008	DBLP DOI BibTeX RDF
19	Chao-Da Huang, Jin-Fu Li 0001, Tsu-Wei Tseng	ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
19	Sebastián Martorell, Ana Isabel Sánchez, Sofía Carlos	A tolerance interval based approach to address uncertainty for RAMS+C optimization.	Reliab. Eng. Syst. Saf.	2007	DBLP DOI BibTeX RDF
19	Jin-Fu Li 0001, Chao-Da Huang	An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
19	Takayuki Kawahara	Low-Voltage Embedded RAMs in Nanometer Era.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
19	Marzio Marseguerra, Enrico Zio, Sebastián Martorell	Basics of genetic algorithms optimization for RAMS applications.	Reliab. Eng. Syst. Saf.	2006	DBLP DOI BibTeX RDF
19	Tsu-Wei Tseng, Jin-Fu Li 0001, Da-Ming Chang	A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap.	DATE	2006	DBLP DOI BibTeX RDF
19	Tsu-Wei Tseng, Jin-Fu Li 0001, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen	A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.	ITC	2006	DBLP DOI BibTeX RDF
19	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu	A built-in self-repair design for RAMs with 2-D redundancy.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Sebastián Martorell, José F. Villanueva, Sofía Carlos, Y. Nebot, Ana Isabel Sánchez, José Luis Pitarch, Vicente Serradell	RAMS+C informed decision-making with application to multi-objective optimization of technical specifications and maintenance using genetic algorithms.	Reliab. Eng. Syst. Saf.	2005	DBLP DOI BibTeX RDF
19	Kaiping Zeng, Sorin A. Huss	RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis.	ISVLSI	2005	DBLP DOI BibTeX RDF
19	Najeem Lawal, Benny Thörnberg, Mattias O'Nils	Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems.	FPL	2005	DBLP DOI BibTeX RDF
19	Jin-Fu Li 0001, Yu-Jane Huang	An error detection and correction scheme for RAMs with partial-write function.	MTDT	2005	DBLP DOI BibTeX RDF
19	Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg	A New Algorithm for Dynamic Faults Detection in RAMs.	VTS	2005	DBLP DOI BibTeX RDF
19	Atsumu Iseno, Yukihiro Iguchi, Tsutomu Sasao	Fault Diagnosis for RAMs Using Walsh Spectrum.	IEICE Trans. Inf. Syst.	2004	DBLP BibTeX RDF
19	Peng Gu, Jun Wang 0001	RAMS: a RDMA-enabled I/O cache architecture for clustered network servers.	SNAPI@PACT	2004	DBLP DOI BibTeX RDF
19	Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars	Tests for address decoder delay faults in RAMs due to inter-gate opens.	ETS	2004	DBLP DOI BibTeX RDF
19	Said Hamdioui, John Delos Reyes, Zaid Al-Ars	Evaluation of Intra-Word Faults in Word-Oriented RAMs.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
19	Shyue-Kung Lu, Shih-Chang Huang	Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs.	MTDT	2004	DBLP DOI BibTeX RDF
19	Kiyoo Itoh 0001, Kenichi Osada, Takayda Kawahara	Reviews and future prospects of low-voltage embedded RAMs.	CICC	2004	DBLP DOI BibTeX RDF
19	Shyue-Kung Lu	A Novel Built-In Self-Repair Approach for Embedded RAMs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	divided word line, fault tolerance, redundancy, low power design, embedded memory
19	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor	A Fault Primitive Based Analysis of Linked Faults in RAMs.	MTDT	2003	DBLP DOI BibTeX RDF	Memory testing, march tests, functional fault models, linked faults, fault primitives
19	Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyounghoon Yang	Performance modeling of resonant tunneling based RAMs.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
19	Miklós Ajtai	Determinism versus Nondeterminism for Linear Time RAMs with Memory Restrictions.	J. Comput. Syst. Sci.	2002	DBLP DOI BibTeX RDF
19	Bharadwaj S. Amrutur, Mark A. Horowitz	Fast low-power decoders for RAMs.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
19	Mohamed Azimane, Antonio Lloris Ruiz	A special march test to detect delay coupling faults for RAMs.	ICECS	2001	DBLP DOI BibTeX RDF
19	Michael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian, Ben Chu, Tony Singh, Harvey Berman	Designing and Implementing Efficient BISR Techniques for Embedded RAMs.	LATW	2001	DBLP BibTeX RDF
19	Jörg E. Vollrath, Randall Rooney	Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment.	ITC	2001	DBLP DOI BibTeX RDF
19	Chih-Hsien Hsu, Shyue-Kung Lu, Sy-Yen Kuo	Novel Fault-Tolerant Techniques for High Capacity RAMs.	PRDC	2001	DBLP DOI BibTeX RDF	divided bit-line, divided word-line, fault tolerance and redundancy, built-in self-repair
19	Patrick W. Dymond, Walter L. Ruzzo	Parallel RAMs with owned global memory and deterministic context-free language recognition.	J. ACM	2000	DBLP DOI BibTeX RDF	CROW-PRAM, DCFL recognition, owner write, parallel algorithms
19	Monica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	An effective distributed BIST architecture for RAMs.	ETW	2000	DBLP DOI BibTeX RDF
19	Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi	Detection of Inter-Port Faults in Multi-Port Static RAMs.	VTS	2000	DBLP DOI BibTeX RDF
19	Wen-Jer Wu, Chuan Yi Tang	Automatic Test Timing Assignment for RAMs Using Linear Programming.	VLSI Design	1999	DBLP DOI BibTeX RDF
19	Janusz A. Brzozowski, Helmut Jürgensen	Erratum to An Algebra of Multiple Faults in RAMs.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF
19	Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	A Physical Design Tool for Built-in Self-Repairable Static RAMs.	DATE	1999	DBLP DOI BibTeX RDF	Built-in, (BISR), reliability, yield, self-repair
19	Miklós Ajtai	Determinism versus Non-Determinism for Linear Time RAMs (Extended Abstract).	STOC	1999	DBLP DOI BibTeX RDF
19	Dilip K. Bhavsar	An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264.	ITC	1999	DBLP DOI BibTeX RDF
19	Miklós Ajtai	Determinism versus Non-Determinism for Linear Time RAMs with Memory Restrictions	Electron. Colloquium Comput. Complex.	1998	DBLP BibTeX RDF
19	Andreas Blass, Yuri Gurevich	The Linear Time Hierarchy Theorems for Abstract State Machines and RAMs.	J. Univers. Comput. Sci.	1997	DBLP DOI BibTeX RDF
19	R. David, Janusz A. Brzozowski, Helmut Jürgensen	Testing for Bounded Faults in RAMs.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	bounded fault, testing, Markov chain, random test, RAM, test length, deterministic test
19	Kanad Chakraborty, Pinaki Mazumder	A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs.	ED&TC	1997	DBLP DOI BibTeX RDF
19	Michael Nicolaidis	Theory of Transparent BIST for RAMs.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	RAM test algorithms, transparent BIST, BIST, signature analysis, pattern sensitive faults, coupling faults
19	Oded Goldreich 0001, Rafail Ostrovsky	Software Protection and Simulation on Oblivious RAMs.	J. ACM	1996	DBLP DOI BibTeX RDF	simulation of random access machines, software protection, pseudorandom functions
19	Arne Andersson, Peter Bro Miltersen, Søren Riis, Mikkel Thorup	Static Dictionaries on AC0 RAMs: Query Time Theta(sqrt(log n/log log n)) is Necessary and Sufficient.	FOCS	1996	DBLP DOI BibTeX RDF
19	Peter Bro Miltersen	Lower Bounds for Static Dictionaries on RAMs with Bit Operations But No Multiplication.	ICALP	1996	DBLP DOI BibTeX RDF
19	Nestoras Tzartzanis, William C. Athas	Energy recovery for the design of high-speed, low-power static RAMs.	ISLPED	1996	DBLP DOI BibTeX RDF
19	Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina	Industrial BIST of Embedded RAMs.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF
19	Baher Haroun, Behzad Sajjadi	Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.	FPGA	1995	DBLP DOI BibTeX RDF
19	Bruce F. Cockburn, Y.-F. Nicole Sat	Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs.	ITC	1995	DBLP DOI BibTeX RDF
19	Etienne Grandjean	Invariance Properties of Rams and Linear Time.	Comput. Complex.	1994	DBLP DOI BibTeX RDF
19	Michael Nicolaidis	Efficient UBIST for RAMs.	VTS	1994	DBLP DOI BibTeX RDF
19	Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina	An industrial experience in the built-in self test of embedded RAMs.	VTS	1994	DBLP DOI BibTeX RDF
19	Manoj Franklin, Kewal K. Saluja	An Algorithm to Test Reconfigured RAMs.	VLSI Design	1994	DBLP DOI BibTeX RDF
19	D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan	Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
19	Jos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey	BIST for Embedded Static RAMs with Coverage Calculation.	ITC	1993	DBLP DOI BibTeX RDF
19	Janusz Sosnowski	"In System" Transparent Autodiagnostics of Rams.	ITC	1993	DBLP DOI BibTeX RDF
19	Shogo Matsui	Dynamic refresh method for dynamic RAMs.	SIGARCH Comput. Archit. News	1992	DBLP DOI BibTeX RDF
19	Syhy-Chang Su, Prasenjit Biswas	A memory-mapped interprocessor communication architecture using FIFO RAMs.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
19	Bapiraju Vinnakota, Jason Andrews	Repair of RAMs With Clustered Faults.	ICCD	1992	DBLP DOI BibTeX RDF
19	O. Kebichi, Michael Nicolaidis	A Tool for Automatic Generation of BISTed and Transparent BISTed Rams.	ICCD	1992	DBLP DOI BibTeX RDF
19	Parameswaran Ramanathan, Kewal K. Saluja, Michael J. Franklin	Zero cost testing of check bits in RAMs with on-chip ECC.	VTS	1992	DBLP DOI BibTeX RDF
19	Michael Nicolaidis	Transparent BIST for RAMs.	ITC	1992	DBLP DOI BibTeX RDF
19	Andrzej Krasniewski, Slawomir Pilarski	High Quality Testing of Embedded RAMs Using Circular Self-Test Path.	ITC	1992	DBLP DOI BibTeX RDF