Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li 0001 |
Area and reliability efficient ECC scheme for 3D RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, April 23-25, 2012, pp. 1-4, 2012, IEEE, 978-1-4577-2080-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Yun-Chao You, Che-Wei Chou, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
A built-in self-test scheme for 3D RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, pp. 1-9, 2012, IEEE Computer Society, 978-1-4673-1594-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Sven Gerber, Sandra Gerber, Peter Krüger, Hans-Knud Arndt |
"Good Design is Environmentally-Friendly." - Discussion of Rams' Principle in Context of the Software Life Cycle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EnviroInfo ![In: Light up the Ideas of Environmental Informatics: Proceedings of the 26th International Conference on Informatics for Environmental Protection, EnviroInfo 2012, Dessau, Germany, August 29-31, 2012., pp. 649-656, 2012, Shaker Verlag, Aachen, 978-3-8440-1248-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
19 | Ioannis Voyiatzis, Costas Efstathiou, Said Hamdioui, Cleo Sgouropoulou |
ALU based address generation for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Tunis, Tunisia, May 16-18, 2012, pp. 1-6, 2012, IEEE, 978-1-4673-1926-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Tsu-Wei Tseng, Jin-Fu Li 0001 |
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(11), pp. 1983-1995, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Luis M. Contreras 0001, Carlos Jesus Bernardos, Ignacio Soto |
RAMS: A Protocol Extension to PMIPv6 for Improving Handover Performance of Multicast Traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Wirel. Mob. Networks Ubiquitous Comput. Dependable Appl. ![In: J. Wirel. Mob. Networks Ubiquitous Comput. Dependable Appl. 2(2), pp. 67-82, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Chih-Sheng Hou, Jin-Fu Li 0001, Tsu-Wei Tseng |
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11), pp. 1731-1743, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger |
Efficient Dual-Rail Implementations in FPGA Using Block RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011, pp. 261-267, 2011, IEEE Computer Society, 978-1-4577-1734-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Chun-Yuan Cheng, Min Wang, Bee Leng Lee |
The impacts of common cause failures for two-unit parallel systems from RAMS+C point of view. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEM ![In: 2011 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM), Singapore, Singapore, December 6-9, 2011, pp. 1256-1260, 2011, IEEE, 978-1-4577-0740-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li 0001 |
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10), pp. 1628-1639, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Miklós Ajtai |
Oblivious RAMs without Cryptographic Assumptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR10, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
19 | Paul Beame, Widad Machmouchi |
Making RAMs Oblivious Requires Superlogarithmic Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR10, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
19 | Tsu-Wei Tseng, Jin-Fu Li 0001, Chih-Sheng Hou |
A Built-in Method to Repair SoC RAMs in Parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 27(6), pp. 46-57, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya |
A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 7(19), pp. 1467-1473, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Petr Böhm, Thomas Gruber 0004 |
A Novel HAZOP Study Approach in the RAMS Analysis of a Therapeutic Robot for Disabled Children. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFECOMP ![In: Computer Safety, Reliability, and Security, 29th International Conference, SAFECOMP 2010, Vienna, Austria, September 14-17, 2010. Proceedings, pp. 15-27, 2010, Springer, 978-3-642-15650-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Shaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, David Hwang |
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings, pp. 274-279, 2010, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Rajesh Velegalati, Jens-Peter Kaps |
Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 1244-1247, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Kazue Yasuoka, Atsushi Watabe, Tetsunori Hattori, Masayuki Matsumoto |
The Policy of applying RAMS to evaluate Railway Signalling Systems for reliable Transportation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORMS/FORMAT ![In: FORMS/FORMAT 2010 - Formal Methods for Automation and Safety in Railway and Automotive Systems [8th Symposium on Formal Methods for Automation and Safety in Railway and Automotive Systems, Braunschweig, Germany, December 2-3, 2010, pp. 55-63, 2010, Springer, 978-3-642-14260-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Shigeto Hiraguri, Koji Iwata, Ikuo Watanabe |
A Method of Evaluating Railway Signalling System Based on RAMS Concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORMS/FORMAT ![In: FORMS/FORMAT 2010 - Formal Methods for Automation and Safety in Railway and Automotive Systems [8th Symposium on Formal Methods for Automation and Safety in Railway and Automotive Systems, Braunschweig, Germany, December 2-3, 2010, pp. 97-105, 2010, Springer, 978-3-642-14260-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Yu-Jen Huang, Yun-Chao You, Jin-Fu Li 0001 |
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings, pp. 236-240, 2010, IEEE, 978-1-4244-6682-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen |
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 331-339, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Chih-Sheng Hou, Jin-Fu Li 0001, Che-Wei Chou |
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 3-7, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
test, test scheduling, repair, RAM, built-in self-repair |
19 | A. C. Torres-Echeverría, Sebastián Martorell, Haydn A. Thompson |
Design optimization of a safety-instrumented system based on RAMS+C addressing IEC 61508 requirements and diverse redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 94(2), pp. 162-179, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Mary Ann Lundteigen, Marvin Rausand, Ingrid Bouwer Utne |
Integrating RAMS engineering and management with the safety life cycle of IEC 61508. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 94(12), pp. 1894-1903, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Markus Püschel, Peter A. Milder, James C. Hoe |
Permuting streaming data using RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 56(2), pp. 10:1-10:34, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
data reordering, linear bit mapping, streaming datapath, stride permutation, Permutation, switch, RAM, connection network, matrix transposition |
19 | Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min |
Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(14), pp. 986-992, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min, Sung-Mo Kang |
A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(19), pp. 1414-1420, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Korefumi Tashiro, Masayuki Matsumoto |
Comparison of documents of an Automatic Train Protection system project with RAMS standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISADS ![In: International Symposium on Autonomous Decentralized Systems (ISADS 2009), 23-25 March 2009, Athens, Greece, pp. 479-482, 2009, IEEE Computer Society, 978-1-4244-4327-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Yu-Jen Huang, Jin-Fu Li 0001 |
Testability Exploration of 3-D RAMs and CAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, pp. 397-402, 2009, IEEE Computer Society, 978-0-7695-3864-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Tamas Györfi, Octavian Cret, Alin Suciu |
High performance true random number generator based on FPGA block RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Junseok Park, Hyokyung Bahn, Kern Koh |
Buffer Cache Management for Combined MLC and SLC Flash Memories Using both Volatile and Nonvolatile RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009, Beijing, China, 24-26 August 2009, pp. 228-235, 2009, IEEE Computer Society, 978-0-7695-3787-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Tim Güneysu, Christof Paar |
Transforming write collisions in block RAMs into security applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009, pp. 128-134, 2009, IEEE Computer Society, 978-1-4244-4377-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Petr Böhm, Thomas Gruber 0004 |
RAMS Analysis of a Bio-inspired Traffic Data Sensor ("Smart Eye"). ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO-SEAA ![In: 35th Euromicro Conference on Software Engineering and Advanced Applications, SEAA 2009, Patras, Greece, August 27-29, 2009, Proceedings, pp. 546-552, 2009, IEEE Computer Society, 978-0-7695-3784-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Hsing-Chen Lu, Jin-Fu Li 0001 |
A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 1997-2000, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon |
On the Use of Magnetic RAMs in Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2008, pp. 723950:1-723950:9, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Ioannis Voyiatzis |
An ALU-Based BIST Scheme for Word-Organized RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(5), pp. 577-590, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Memory control and access, Reliability, Test generation, Built-In Tests, Testing and Fault-Tolerance, Semiconductor Memories |
19 | Yu-Jen Huang, Jin-Fu Li 0001 |
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 357-362, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara |
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, pp. 90-91, 2008, IEEE, 978-1-4244-2010-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Chao-Da Huang, Jin-Fu Li 0001, Tsu-Wei Tseng |
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1135-1143, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Sebastián Martorell, Ana Isabel Sánchez, Sofía Carlos |
A tolerance interval based approach to address uncertainty for RAMS+C optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 92(4), pp. 408-422, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Fu Li 0001, Chao-Da Huang |
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12), pp. 2703-2711, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Takayuki Kawahara |
Low-Voltage Embedded RAMs in Nanometer Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 90-C(4), pp. 735-742, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Marzio Marseguerra, Enrico Zio, Sebastián Martorell |
Basics of genetic algorithms optimization for RAMS applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 91(9), pp. 977-991, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Tsu-Wei Tseng, Jin-Fu Li 0001, Da-Ming Chang |
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 53-58, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Tsu-Wei Tseng, Jin-Fu Li 0001, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen |
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-9, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu |
A built-in self-repair design for RAMs with 2-D redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 742-745, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Sebastián Martorell, José F. Villanueva, Sofía Carlos, Y. Nebot, Ana Isabel Sánchez, José Luis Pitarch, Vicente Serradell |
RAMS+C informed decision-making with application to multi-objective optimization of technical specifications and maintenance using genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 87(1), pp. 65-75, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Kaiping Zeng, Sorin A. Huss |
RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 266-267, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Najeem Lawal, Benny Thörnberg, Mattias O'Nils |
Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 136-141, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Fu Li 0001, Yu-Jane Huang |
An error detection and correction scheme for RAMs with partial-write function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 115-120, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg |
A New Algorithm for Dynamic Faults Detection in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 177-182, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Atsumu Iseno, Yukihiro Iguchi, Tsutomu Sasao |
Fault Diagnosis for RAMs Using Walsh Spectrum. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 87-D(3), pp. 592-600, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
19 | Peng Gu, Jun Wang 0001 |
RAMS: a RDMA-enabled I/O cache architecture for clustered network servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SNAPI@PACT ![In: Proceedings of the International Workshop on Storage Network Architecture and Parallel I/Os, SNAPI@PACT, Antibes Juan-les-Pins, France, September 30, 2004, pp. 66-72, 2004, ACM, 978-1-4503-7822-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars |
Tests for address decoder delay faults in RAMs due to inter-gate opens. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004, pp. 146-151, 2004, IEEE Computer Society, 0-7695-2119-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Said Hamdioui, John Delos Reyes, Zaid Al-Ars |
Evaluation of Intra-Word Faults in Word-Oriented RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 283-288, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Shyue-Kung Lu, Shih-Chang Huang |
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 60-64, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Kiyoo Itoh 0001, Kenichi Osada, Takayda Kawahara |
Reviews and future prospects of low-voltage embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004, pp. 339-344, 2004, IEEE, 0-7803-8495-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Shyue-Kung Lu |
A Novel Built-In Self-Repair Approach for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 315-324, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
divided word line, fault tolerance, redundancy, low power design, embedded memory |
19 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
A Fault Primitive Based Analysis of Linked Faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 33-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Memory testing, march tests, functional fault models, linked faults, fault primitives |
19 | Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyounghoon Yang |
Performance modeling of resonant tunneling based RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 900-903, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Miklós Ajtai |
Determinism versus Nondeterminism for Linear Time RAMs with Memory Restrictions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Syst. Sci. ![In: J. Comput. Syst. Sci. 65(1), pp. 2-37, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Bharadwaj S. Amrutur, Mark A. Horowitz |
Fast low-power decoders for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(10), pp. 1506-1515, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Mohamed Azimane, Antonio Lloris Ruiz |
A special march test to detect delay coupling faults for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 995-999, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Michael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian, Ben Chu, Tony Singh, Harvey Berman |
Designing and Implementing Efficient BISR Techniques for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001., pp. 248-252, 2001, IEEE. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
19 | Jörg E. Vollrath, Randall Rooney |
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 768-775, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Chih-Hsien Hsu, Shyue-Kung Lu, Sy-Yen Kuo |
Novel Fault-Tolerant Techniques for High Capacity RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 17-19 December 2001, Seoul, Korea, pp. 11-18, 2001, IEEE Computer Society, 0-7695-1414-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
divided bit-line, divided word-line, fault tolerance and redundancy, built-in self-repair |
19 | Patrick W. Dymond, Walter L. Ruzzo |
Parallel RAMs with owned global memory and deterministic context-free language recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 47(1), pp. 16-45, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CROW-PRAM, DCFL recognition, owner write, parallel algorithms |
19 | Monica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |
An effective distributed BIST architecture for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000, pp. 119-124, 2000, IEEE Computer Society, 0-7695-0701-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi |
Detection of Inter-Port Faults in Multi-Port Static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 297-304, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Wen-Jer Wu, Chuan Yi Tang |
Automatic Test Timing Assignment for RAMs Using Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 10(2), pp. 143-153, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Janusz A. Brzozowski, Helmut Jürgensen |
Erratum to An Algebra of Multiple Faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 305-306, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder |
A Physical Design Tool for Built-in Self-Repairable Static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 714-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Built-in, (BISR), reliability, yield, self-repair |
19 | Miklós Ajtai |
Determinism versus Non-Determinism for Linear Time RAMs (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the Thirty-First Annual ACM Symposium on Theory of Computing, May 1-4, 1999, Atlanta, Georgia, USA, pp. 632-641, 1999, ACM, 1-58113-067-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Dilip K. Bhavsar |
An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999, pp. 311-318, 1999, IEEE Computer Society, 0-7803-5753-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Miklós Ajtai |
Determinism versus Non-Determinism for Linear Time RAMs with Memory Restrictions ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR98, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
19 | Andreas Blass, Yuri Gurevich |
The Linear Time Hierarchy Theorems for Abstract State Machines and RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Univers. Comput. Sci. ![In: J. Univers. Comput. Sci. 3(4), pp. 247-278, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | R. David, Janusz A. Brzozowski, Helmut Jürgensen |
Testing for Bounded Faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(3), pp. 197-214, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bounded fault, testing, Markov chain, random test, RAM, test length, deterministic test |
19 | Kanad Chakraborty, Pinaki Mazumder |
A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 330-334, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Michael Nicolaidis |
Theory of Transparent BIST for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(10), pp. 1141-1156, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
RAM test algorithms, transparent BIST, BIST, signature analysis, pattern sensitive faults, coupling faults |
19 | Oded Goldreich 0001, Rafail Ostrovsky |
Software Protection and Simulation on Oblivious RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 43(3), pp. 431-473, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
simulation of random access machines, software protection, pseudorandom functions |
19 | Arne Andersson, Peter Bro Miltersen, Søren Riis, Mikkel Thorup |
Static Dictionaries on AC0 RAMs: Query Time Theta(sqrt(log n/log log n)) is Necessary and Sufficient. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 37th Annual Symposium on Foundations of Computer Science, FOCS '96, Burlington, Vermont, USA, 14-16 October, 1996, pp. 441-450, 1996, IEEE Computer Society, 0-8186-7594-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Peter Bro Miltersen |
Lower Bounds for Static Dictionaries on RAMs with Bit Operations But No Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 23rd International Colloquium, ICALP96, Paderborn, Germany, 8-12 July 1996, Proceedings, pp. 442-453, 1996, Springer, 3-540-61440-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Nestoras Tzartzanis, William C. Athas |
Energy recovery for the design of high-speed, low-power static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996, pp. 55-60, 1996, IEEE, 0-7803-3571-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina |
Industrial BIST of Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 12(3), pp. 86-95, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Baher Haroun, Behzad Sajjadi |
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 75-81, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Bruce F. Cockburn, Y.-F. Nicole Sat |
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995, pp. 23-32, 1995, IEEE Computer Society, 0-7803-2992-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Etienne Grandjean |
Invariance Properties of Rams and Linear Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Complex. ![In: Comput. Complex. 4, pp. 62-106, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Michael Nicolaidis |
Efficient UBIST for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 12th IEEE VLSI Test Symposium (VTS'94), April 25-28, 1994, Cherry Hill, New Jersey, USA, pp. 158-166, 1994, IEEE Computer Society, 0-8186-5440-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina |
An industrial experience in the built-in self test of embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 12th IEEE VLSI Test Symposium (VTS'94), April 25-28, 1994, Cherry Hill, New Jersey, USA, pp. 306-311, 1994, IEEE Computer Society, 0-8186-5440-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Manoj Franklin, Kewal K. Saluja |
An Algorithm to Test Reconfigured RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 359-364, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan |
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 546-558, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Jos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey |
BIST for Embedded Static RAMs with Coverage Calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 339-348, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Janusz Sosnowski |
"In System" Transparent Autodiagnostics of Rams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 835-844, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Shogo Matsui |
Dynamic refresh method for dynamic RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 20(4), pp. 9-16, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Syhy-Chang Su, Prasenjit Biswas |
A memory-mapped interprocessor communication architecture using FIFO RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 34(1-5), pp. 187-191, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Bapiraju Vinnakota, Jason Andrews |
Repair of RAMs With Clustered Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 582-585, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | O. Kebichi, Michael Nicolaidis |
A Tool for Automatic Generation of BISTed and Transparent BISTed Rams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 570-575, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Parameswaran Ramanathan, Kewal K. Saluja, Michael J. Franklin |
Zero cost testing of check bits in RAMs with on-chip ECC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA, pp. 292-297, 1992, IEEE Computer Society, 0-7803-0623-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Michael Nicolaidis |
Transparent BIST for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 598-607, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Andrzej Krasniewski, Slawomir Pilarski |
High Quality Testing of Embedded RAMs Using Circular Self-Test Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 652-661, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|