Search results for "SPARC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Stefan Tillich, Johann Großschädl	Power Analysis Resistant AES Implementation with Instruction Set Extensions.	CHES	2007	DBLP DOI BibTeX RDF	embedded RISC processor, SPARC V8 architecture, SCA resistance, Advanced Encryption Standard, power analysis, instruction set extensions
20	Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama	A 1.3GHz fifth generation SPARC64 microprocessor.	DAC	2003	DBLP DOI BibTeX RDF	unix server, reliability, microprocessor, microarchitecture, SPARC, clock distribution
20	Andreas Koch	A Comprehensive Prototyping-Platform for Hardware-Software Codesign.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	hybrid processor, RTEMS, Virtex, FPGA, prototyping, codesign, SPARC, Xilinx
20	H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar	An SBus Multi-Tracer and its applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	SBus Multi Tracer, SBus monitoring board, logic analyzer, bus analyzer, trace length, board memory, multi occurrences, trigger patterns, multiple partitions, tracing memory, systematic timing information, pattern occurrences, triggering patterns, SUN SPARC station, field programmable gate arrays, Field Programmable Gate Array, FPGA, logic testing, automatic test equipment, system buses, timing diagrams, computerised monitoring
20	Seungjoon Park, David L. Dill	An Executable Specification, Analyzer and Verifier for RMO (Relaxed Memory Order).	SPAA	1995	DBLP DOI BibTeX RDF	SPARC
20	Robert H. B. Netzer, Mark H. Weaver	Optimal Tracing and Incremental Reexecution for Debugging Long-Running Programs.	PLDI	1994	DBLP DOI BibTeX RDF	DEBUG, SPARC
20	Peter M. Chen, David A. Patterson 0001	A New Approach to I/O Performance Evaluation - Self-Scaling I/O Benchmarks, Predicted I/O Performance.	SIGMETRICS	1993	DBLP DOI BibTeX RDF	SPARC
20	Hans-Juergen Boehm	Space Efficient Conservative Garbage Collection.	PLDI	1993	DBLP DOI BibTeX RDF	C, SPARC, Cedar
20	Koray Öner, Michel Dubois 0001	Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF	SPARC
20	Peter Steenkiste	Analyzing Communication Latency Using the Nectar Communication Processor.	SIGCOMM	1992	DBLP DOI BibTeX RDF	SPARC
20	Paul F. Reynolds Jr., Carmen M. Pancerella, Sudhir Srinivasan	Making Parallel Simulations go Fast.	WSC	1992	DBLP DOI BibTeX RDF	SPARC
20	Eric K. Clemons	Design of an External Schema Facility to Define and Process Recursive Structures.	ACM Trans. Database Syst.	1981	DBLP DOI BibTeX RDF	ANSI SPARC architectures, external schemata, recursive data structures, user views
20	Ramez Elmasri, Gio Wiederhold	Data Model Integration Using the Structural Model.	SIGMOD Conference	1979	DBLP DOI BibTeX RDF	ansi/sparc dbms architecture, conceptual and external schema, data model integration, entity classes and relationships, logical database design, relational model, structural model, data semantics
11	Stephan Aier, Robert Winter 0001	Virtual Decoupling for IT/Business Alignment - Conceptual Foundations, Architecture Design and Implementation Example.	Bus. Inf. Syst. Eng.	2009	DBLP DOI BibTeX RDF	] Integration, IT/business alignment, Decoupling
11	Mehrdad Reshadi, Prabhat Mishra 0001, Nikil D. Dutt	Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation
11	Stephan Aier, Robert Winter 0001	Virtuelle Entkopplung von fachlichen und IT-Strukturen für das IT/Business Alignment - Grundlagen, Architekturgestaltung und Umsetzung am Beispiel der Domänenbildung.	Wirtschaftsinf.	2009	DBLP DOI BibTeX RDF	IT/business alignment, Integration, Decoupling
11	William N. Scherer III, Doug Lea, Michael L. Scott	Scalable synchronous queues.	Commun. ACM	2009	DBLP DOI BibTeX RDF
11	Ping Chen 0003, Hai Xiao, Xiaobin Shen 0001, Xinchun Yin, Bing Mao, Li Xie 0001	DROP: Detecting Return-Oriented Programming Malicious Code.	ICISS	2009	DBLP DOI BibTeX RDF
11	Matthew D. Allen, Srinath Sridharan, Gurindar S. Sohi	Serialization sets: a dynamic dependence-based parallel execution model.	PPoPP	2009	DBLP DOI BibTeX RDF	serialization sets, parallel computing, runtime system, serializer
11	Jonathan D. Ellithorpe, Zhangxi Tan, Randy H. Katz	Internet-in-a-Box: emulating datacenter network architectures using FPGAs.	DAC	2009	DBLP DOI BibTeX RDF	datacenter networking, hardware modeling
11	Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang	Automatic Verification of External Interrupt Behaviors for Microprocessor Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado	An open-source binary utility generator.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Platform debugging, retargetable tools, TLM
11	Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez	Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration.	DSD	2008	DBLP DOI BibTeX RDF
11	Takamitsu Tahara, Katsuhiko Gondow, Seiya Ohsuga	DRACULA: Detector of Data Races in Signals Handlers.	APSEC	2008	DBLP DOI BibTeX RDF
11	Ming Yang, Lixin Yu, Heping Peng	Energy Efficient Register File with Reduced Window Partition.	ICPADS	2008	DBLP DOI BibTeX RDF
11	Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards, Edward A. Lee	Predictable programming on a precision timed architecture.	CASES	2008	DBLP DOI BibTeX RDF	pipeline, memory hierarchy, timing predictability
11	Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau	Control flow optimization in loops using interval analysis.	CASES	2008	DBLP DOI BibTeX RDF	algorithmic code transformation, compiler loop optimization, interval analysis
11	Enkhbold Ochirsuren, Heiko Hinkelmann, Leandro Soares Indrusiak, Manfred Glesner	TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor.	DIPES	2008	DBLP DOI BibTeX RDF
11	Babu Turumella, Mukesh Sharma	Assertion-based verification of a 32 thread SPARCTM CMT microprocessor.	DAC	2008	DBLP DOI BibTeX RDF	simulation, verification, coverage, assertions, multi-threading
11	Max R. de O. Schultz, Alexandre Keunecke Ignácio Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. dos Santos	A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems.	SAMOS	2007	DBLP DOI BibTeX RDF
11	José O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos	An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code.	SAMOS	2007	DBLP DOI BibTeX RDF
11	Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado	Automatic Retargeting of Binary Utilities for Embedded Code Generation.	ISVLSI	2007	DBLP DOI BibTeX RDF
11	Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau	Short-Circuit Compiler Transformation: Optimizing Conditional Blocks.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Jonathan K. Lee, Jens Palsberg, Fernando Magno Quintão Pereira	Aliased Register Allocation for Straight-Line Programs Is NP-Complete.	ICALP	2007	DBLP DOI BibTeX RDF
11	Tobias Vejda, Dan Page, Johann Großschädl	Instruction Set Extensions for Pairing-Based Cryptography.	Pairing	2007	DBLP DOI BibTeX RDF
11	V. Mariatos, Kostas Adaos, George Alexiou	Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
11	Antonio Dasilva 0001, José-Fernán Martínez, Lourdes López-Santidrián, Ana Belén García, Luis Redondo	Exhaustif: a fault injection tool for distributed heterogeneous embedded systems.	EATIS	2007	DBLP DOI BibTeX RDF	SWIFI, fault injection techniques, fault tolerance, distributed embedded systems
11	Adam J. Elbirt	Fast and Efficient Implementation of AES via Instruction Set Extensions.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF	cryptography, block cipher, AES, Galois Field
11	Shrenik Mehta, Dwayne Lee	Industry perspective on chip multi-threading, bridging the gap with academia using OpenSPARC.	WCAE	2007	DBLP DOI BibTeX RDF
11	Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel	Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001	A retargetable framework for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm
11	Bernd Mathiske, Douglas N. Simon, Dave Ungar	The Project Maxwell assembler system.	PPPJ	2006	DBLP DOI BibTeX RDF	assembler generator, cross assembler, domain-specific framework, the Java language, Java, automated testing, systems programming, disassembler
11	Michael Armbruster, Erik Zimmer, Matthias Lehmann, Reinhard Reichel, E. Sieglin, Gernot Spiegelberg, Armin Sulzmann	Affordable X-By-Wire technology based on an innovative, scalable E/E platform-concept.	VTC Spring	2006	DBLP DOI BibTeX RDF
11	Zhelong Pan, Rudolf Eigenmann	Fast and Effective Orchestration of Compiler Optimizations for Automatic Performance Tuning.	CGO	2006	DBLP DOI BibTeX RDF
11	Kamran Karimi, Mohsen Sharifi	Transparent Distributed Programming under Linux.	HPCS	2006	DBLP DOI BibTeX RDF
11	Guy-Vincent Jourdan, Panitee Ritthiruangdech, Hasan Ural	Test Suite Reduction Based on Dependence Analysis.	ISCIS	2006	DBLP DOI BibTeX RDF
11	Greg Bronevetsky, Keshav Pingali, Paul Stodghill	Experimental evaluation of application-level checkpointing for OpenMP programs.	ICS	2006	DBLP DOI BibTeX RDF
11	Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Integrated Verification Approach during ADL-Driven Processor Design.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
11	Miroslav N. Velev	Formal Verification of Pipelined Microprocessors with Delayed Branches.	ISQED	2006	DBLP DOI BibTeX RDF
11	William N. Scherer III, Doug Lea, Michael L. Scott	Scalable synchronous queues.	PPoPP	2006	DBLP DOI BibTeX RDF	contention freedom, dual data structures, dual queue, dual stack, lock freedom, synchronous queue, nonblocking synchronization
11	Arvind, Jan-Willem Maessen	Memory Model = Instruction Reordering + Store Atomicity.	ISCA	2006	DBLP DOI BibTeX RDF
11	Jason Hiser, Daniel W. Williams, Adrian Filipi, Jack W. Davidson, Bruce R. Childers	Evaluating fragment construction policies for SDT systems.	VEE	2006	DBLP DOI BibTeX RDF	dynamic translation performance, software dynamic translator, performance, low overhead
11	Hans Eberle, Sheueling Chang Shantz, Vipul Gupta, Nils Gura, Leonard Rarick, Lawrence Spracklen	Accelerating Next-Generation Public-Key Cryptosystems on General-Purpose CPUs.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Public key cryptosystems, Processor Architectures, Cryptographic controls
11	Haris Lekatsas, Jörg Henkel, Wayne H. Wolf	Approximate arithmetic coding for bus transition reduction in low power designs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Hisashige Ando, Nestoras Tzartzanis, William W. Walker	A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano C. de Araújo, Edna Barros	The ArchC Architecture Description Language and Tools.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	ISA simulator, Architecture description language, SystemC, compiled simulation
11	Patrick Schaumont, David Hwang 0001, Ingrid Verbauwhede	Platform-based design for an embedded-fingerprint-authentication device.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
11	Yasushi Shinjo, Calton Pu	Achieving Efficiency and Portability in Systems Software: A Case Study on POSIX-Compliant Multithreaded Programs.	IEEE Trans. Software Eng.	2005	DBLP DOI BibTeX RDF	runtime specialization, thread-specific data, Performance, concurrent programming, threads, portability, software libraries
11	Jürgen Becker 0001, Alexander Thomas	Scalable Processor Instruction Set Extension.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF
11	Yonghong Song, Spiros Kalogeropulos, Partha Tirumalai	Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
11	John D. Davis, James Laudon, Kunle Olukotun	Maximizing CMP Throughput with Mediocre Cores.	IEEE PACT	2005	DBLP DOI BibTeX RDF
11	Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee	SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
11	Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno	Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.	DATE	2005	DBLP DOI BibTeX RDF
11	Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones	Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory.	MSE	2005	DBLP DOI BibTeX RDF
11	Mehrdad Reshadi, Prabhat Mishra 0001	Memory access optimizations in instruction-set simulators.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	memory address-space mapping, instruction-set simulator
11	Radu Teodorescu, Josep Torrellas	Prototyping Architectural Support for Program Rollback Using FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
11	Christophe Honvault, Marc Le Roy, Pascal Gula, Jean-Charles Fabre, Gérard Le Lann, Eric Bornschlegl	Novel Generic Middleware Building Blocks for Dependable Modular Avionics Systems.	EDCC	2005	DBLP DOI BibTeX RDF
11	Stefan Tillich, Johann Großschädl, Alexander Szekely	An Instruction Set Extension for Fast and Memory-Efficient AES Implementation.	Communications and Multimedia Security	2005	DBLP DOI BibTeX RDF	32-bit implementation, cache-based side-channel analysis, Advanced Encryption Standard, S-box, instruction set extensions
11	Rod Fatoohi, Ken Kardys, Sumy Koshy, Soundarya Sivaramakrishnan, Jeffrey S. Vetter	Performance Evaluation of High-Speed Interconnects Using Dense Communication Patterns.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
11	Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rainer Dorsch, Hans-Joachim Wunderlich	Development of an audio player as system-on-a-chip using an open source platform.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
11	Michele Portolan, Régis Leveugle	On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors.	IOLTS	2005	DBLP DOI BibTeX RDF
11	Stefan Tillich, Johann Großschädl	Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography.	ICCSA (2)	2005	DBLP DOI BibTeX RDF	32-bit implementation, software acceleration, Advanced Encryption Standard, Rijndael, instruction set extensions
11	Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo	Extending the ArchC Language for Automatic Generation of Assemblers.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
11	Michael Ball 0002, Cristina Cifuentes, Deepankar Bairagi	Partitioning of Code for a Massively Parallel Machine.	IEEE PACT	2004	DBLP DOI BibTeX RDF
11	Kristian Hildingsson, Tughrul Arslan, Ahmet T. Erdogan	Energy Evaluation Methodology for Platform Based System-on-Chip Design.	ISVLSI	2004	DBLP DOI BibTeX RDF
11	Irina Chihaia, Thomas R. Gross	Effectiveness of simple memory models for performance prediction.	ISPASS	2004	DBLP DOI BibTeX RDF
11	Gabriel Marin, John M. Mellor-Crummey	Cross-architecture performance predictions for scientific applications using parameterized models.	SIGMETRICS	2004	DBLP DOI BibTeX RDF	modeling, performance analysis, prediction
11	Phillip H. Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, Ron Cytron	Liquid Architecture.	IPDPS Next Generation Software Program - NSFNGS - PI Workshop	2004	DBLP DOI BibTeX RDF
11	Sandro Rigo, Guido Araujo, Marcus Bartholomeu, Rodolfo Azevedo	ArchC: A SystemC-Based Architecture Description Language.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
11	Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo	Optimizations for Compiled Simulation Using Instruction Type Information.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
11	Daniel Luna, Mikael Pettersson, Konstantinos Sagonas	HiPE on AMD64.	Erlang Workshop	2004	DBLP DOI BibTeX RDF	AMD64, native code compilation, erlang
11	Naveen Kumar 0002, Jonathan Misurda, Bruce R. Childers, Mary Lou Soffa	Instrumentation in software dynamic translators for self-managed systems.	WOSS	2004	DBLP DOI BibTeX RDF
11	Ji-Rong Wen, Qing Li 0001, Wei-Ying Ma, HongJiang Zhang	A Multi-paradigm Querying Approach for a Generic Multimedia Database Management System.	SIGMOD Rec.	2003	DBLP DOI BibTeX RDF	media independence, multi-paradigm querying, multimedia database management, uniform data modeling
11	Mark W. Bailey, Jack W. Davidson	Automatic Detection and Diagnosis of Faults in Generated Code for Procedure Calls.	IEEE Trans. Software Eng.	2003	DBLP DOI BibTeX RDF	Target-sensitive test suite generation, automatic fault isolation, procedure-calling convention, compiler testing and debugging, code generation
11	Norman Ramsey, Cristina Cifuentes	A transformational approach to binary translation of delayed branches.	ACM Trans. Program. Lang. Syst.	2003	DBLP DOI BibTeX RDF	program transformation, program analysis, Binary translation
11	Jürgen Becker 0001, Martin Vorbach	Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC).	ISVLSI	2003	DBLP DOI BibTeX RDF
11	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor.	DATE	2003	DBLP DOI BibTeX RDF
11	Tom J. Kazmierski, Xing Q. Yang	A Secure Web-Based Framework for Electronic System Level Design.	DATE	2003	DBLP DOI BibTeX RDF
11	Jürgen Becker 0001, Alexander Thomas, Maik Scheer	Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration.	SBCCI	2003	DBLP DOI BibTeX RDF
11	Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt	An efficient retargetable framework for instruction-set simulation.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm
11	Makoto Kudo, Hisayasu Kuroda, Yasumasa Kanada	Parallel Blocked Sparse Matrix-Vector Multiplication with Dynamic Parameter Selection Method.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
11	Prasad Jayanti, Srdjan Petrovic	Efficient and practical constructions of LL/SC variables.	PODC	2003	DBLP DOI BibTeX RDF
11	Mehrdad Reshadi, Nikil D. Dutt	Reducing Compilation Time Overhead in Compiled Simulators.	ICCD	2003	DBLP DOI BibTeX RDF
11	Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo	Exploring Memory Hierarchy with ArchC.	SBAC-PAD	2003	DBLP DOI BibTeX RDF
11	Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell	A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF
11	Christian S. Collberg	Automatic derivation of compiler machine descriptions.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	Back-end generators, compiler configuration scripts, retargeting
11	Georg Bißeling, Hans-Christian Hoppe, Alexander V. Supalov, Pierre Lagier, Jean Latour	Fujitsu MPI-2: Fast Locally, Reaching Globally.	PVM/MPI	2002	DBLP DOI BibTeX RDF
11	Nihar R. Mahapatra, Jiangjiang Liu 0002, Krishnan Sundaresan	The performance advantage of applying compression to the memory system.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	address compression, instruction compression, cache, data compression, entropy, memory, latency, Markov models, bandwidth, storage, traffic, register file, lossless compression
11	Davide Bertozzi, Luca Benini, Giovanni De Micheli	Low Power Error Resilient Encoding for On-Chip Data Buses.	DATE	2002	DBLP DOI BibTeX RDF
11	Tom J. Kazmierski, Neil Clayton	A Two-Tier Distributed Electronic Design Framework.	DATE	2002	DBLP DOI BibTeX RDF