Search results for "codesign"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss	A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines.	DSD	2001	DBLP DOI BibTeX RDF
26	Robert H. Klenke	A Hardware/Software Codesign Senior Capstone Design Project in Computer Engineering.	MSE	2001	DBLP DOI BibTeX RDF
26	Peter Petrov, Alex Orailoglu	Towards effective embedded processors in codesigns: customizable partitioned caches.	CODES	2001	DBLP DOI BibTeX RDF	reprogrammable customizations, embedded processors, data cache
26	Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani	Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
26	Frank Slomka, Matthias Dörfel, Ralf Münzenberger, Richard Hofmann	Hardware/Software Codesign and Rapid Prototyping of Embedded Systems.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
26	Euripides Sotiriades, Apostolos Dollas, Peter Athanas	Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine.	FCCM	2000	DBLP DOI BibTeX RDF	FPGA, Architecture, Custom, Golomb Ruler
26	JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas	A codesign virtual machine for hierarchical, balanced hardware/software system modeling.	DAC	2000	DBLP DOI BibTeX RDF
26	Frank Engel, Johannes Nührenberg, Gerhard P. Fettweis	A generic tool set for application specific processor architectures.	CODES	2000	DBLP DOI BibTeX RDF
26	Dai Araki, Tadatoshi Ishii, Daniel Gajski	Rapid Prototyping with HW/SW Codesign Tool.	ECBS	1999	DBLP DOI BibTeX RDF
26	Juan Antonio Maestro, Daniel Mozos, Román Hermida	The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach.	DATE	1999	DBLP DOI BibTeX RDF
26	Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig	Self Recovering Controller and Datapath Codesign.	DATE	1999	DBLP DOI BibTeX RDF
26	William Fornaciari, Paolo Gubian, Donatella Sciuto, Cristina Silvano	Power estimation of embedded systems: a hardware/software codesign approach.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
26	Rolf Ernst	Codesign of Embedded Systems: Status and Trends.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
26	Claude Ackad	Statechart-Based HW/SW-Codesign of a Multi-FPGA-Board and a Microprocessor.	FPL	1998	DBLP DOI BibTeX RDF
26	Jesper Grode, Jan Madsen	A Uni.ed Component Modeling Approach for Performance Estimation in Hardware/Software Codesign.	EUROMICRO	1998	DBLP DOI BibTeX RDF
26	Juan Antonio Maestro, Daniel Mozos, Julio Septién	A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces.	EUROMICRO	1998	DBLP DOI BibTeX RDF
26	Frank Vahid	Modifying Min-Cut for Hardware and Software Functional Partitioning.	CODES	1997	DBLP DOI BibTeX RDF	Kernighan/Lin, min-cut, Functional partitioning
26	Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, Kiyoung Choi	Hardware-Software Codesign of Resource-Constrained Real-Time Systems.	RTCSA	1996	DBLP DOI BibTeX RDF
26	Joseph T. Buck	A dynamic dataflow model suitable for efficient mixed hardware and software implementations of DSP applications.	CODES	1994	DBLP DOI BibTeX RDF
26	Michel Auguin, Mohamed Belhadj, Judith Benzakki, C. Carrière, Guy Durrieu, Thierry Gautier, Michel Israël, Paul Le Guernic, Michel Lemaître, E. Martin, Patrice Quinton, Laurence Rideau, Frédéric Rousseau 0001, Olivier Sentieys	Towards a multi-formalism framework for architectural synthesis: the ASAR project.	CODES	1994	DBLP DOI BibTeX RDF
26	Donald E. Thomas, Jay K. Adams, Herman Schmit	A Model and Methodology for Hardware-Software Codesign.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
25	Nikos S. Voros, Konstantinos Masselos	Prototyping of a WLAN system using C++ based architecture exploration.	MobiMedia	2007	DBLP DOI BibTeX RDF	hardware/software codesign, wireless systems, architecture exploration
25	Manar AbuTalib, Adel Khelifi, Alain Abran, Olga Ormandjieva	Assessment of Real-Time Software Specifications Quality Using COSMIC-FFP.	IWSM/Mensura	2007	DBLP DOI BibTeX RDF	ISO 19761, system-level requirements specification, codesign, functional size measurement, COSMIC-FFP
25	Frédéric Danesi, Nicolas Gardan, Yvon Gardan	Collaborative Design: From Concept to Application.	GMAI	2006	DBLP DOI BibTeX RDF	CAD, Collaborative work, codesign, distributed design
25	Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari, Nasir D. Memon	SAFE-OPS: An approach to embedded software security.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Software protection, HW/SW codesign
25	William B. Gardner	Converging CSP specifications and C++ programming via selective formalism.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	hardware/software codesign, Executable specifications, object-oriented application frameworks
25	Sébastien Bilavarn, Eric Debes, Pierre Vandergheynst, Jean-Philippe Diguet	Processor Enhancements for Media Streaming Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	reconfigurable coprocessor, hardware design space exploration, video coding, codesign, multimedia processing, matching pursuit, software profiling
25	Chih-Hao Tseng, Pao-Ann Hsiung	UML-Based Design Flow and Partitioning Methodology for Dynamically Reconfigurable Computing Systems.	EUC	2005	DBLP DOI BibTeX RDF	FPGA, UML, partitioning, reconfigurable computing, codesign, sequence diagram, design flow
25	Octavian Cret, Kalman Pusztai, Cristian Vancea, Balint Szente	CREC: A Novel Reconfigurable Computing Design Methodology.	IPDPS	2003	DBLP DOI BibTeX RDF	general-purpose reconfigurable systems, Hardware / Software CoDesign, multiple execution units, FPGA, VHDL, RISC, Instruction Level Parallelism (ILP)
25	Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya	Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	reconfigurable datapaths, hardware-software codesign
25	Wieland Fischer, Jean-Pierre Seifert	Increasing the Bitlength of a Crypto-Coprocessor.	CHES	2002	DBLP DOI BibTeX RDF	Arithmetical coprocessor, Hardware/Software codesign, Modular multiplication, Hardware architecture
25	Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa	Architecture-level power estimation and design experiments.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	architecture tradeoff, architecture-level power estimation, control unit, energy table, instruction format transition, output signal transition, power analysis and estimation, switch capacitance, low power design, hardware/software codesign, energy model, functional unit, computer-aided design of VLSI
25	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New Approach to Design Reliable Real-Time Speech Recognition Systems.	IOLTW	2001	DBLP DOI BibTeX RDF	HW-SW Codesign, Digital Signal Processing - DSP, Speech-Recognition Systems, Fault-Tolerance Techniques, Transparent BIST, Performance Degradation, Area overhead
25	Stephan Schulz 0002	A Transformation for System Level Design Model Specifications into Implementation Descriptions.	SCCC	2001	DBLP DOI BibTeX RDF	CSP, system modeling, codesign, embedded systems design
25	Mourad Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, André Tissot	A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology.	CAMP	2000	DBLP DOI BibTeX RDF	pattern recognition architecture, VLSI physical integration, VLSI characteristics, pattern recognition, specification, design methodology, system architecture, system-on-a-chip, hardware/software codesign, heterogeneous architecture
25	Frank-Michael Renner, Jürgen Becker 0001, Manfred Glesner	Field Programmable Communication Emulation and Optimization for Embedded System Design.	FPL	2000	DBLP DOI BibTeX RDF	architecture-precise rapid prototyping, field programmable emulation, Hardware/software codesign, real-time embedded systems
25	Arvind Rajawat, M. Balakrishnan, Anshul Kumar	nterface Synthesis: Issues and Approaches.	VLSI Design	2000	DBLP DOI BibTeX RDF	Codesign methodology, Interface optimization, Communication protocols, Interface synthesis
25	Matthias Dörfel, Frank Slomka, Richard Hofmann	A Scalable Hardware Library for the Rapid Prototyping of SDL Specifications.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Interface Selection, High-Level Synthesis, Rapid Prototyping, SDL, Codesign, Communication Systems
25	Michael Eisenring, Jürgen Teich	Interfacing Hardware and Software.	FPL	1998	DBLP DOI BibTeX RDF	automatic interface synthesis, low power design, rapid prototyping, hardware/software codesign
25	Adel Baganne, Jean Luc Philippe, Eric Martin 0001	Hardware interface design for real time embedded systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	real time digital signal processing, hardware interface design, codesign approach, storage components, hardware-software components, I/O data modeling style, hardware I/O transfer sequences, high level synthesis tool, GAUT, I/O transfer order, cosynthesis tool, real-time systems, ASICs, timing constraints, generic model, data communication, real time embedded systems, formal technique, interface specification, FFT algorithms, allocation problem
25	Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, Rainer Schoenen, Heinrich Meyr	DSP Processor/Compiler Co-Design: A Quantitative Approach.	ISSS	1996	DBLP DOI BibTeX RDF	processor/compiler codesign, benchmarking methodology, DSPstone, fast processor simulation, SuperSim, compiled processor simulation, performance evaluation, embedded systems, digital signal processing, digital signal processing chips, LISA, top-down approach, machine description
25	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
21	Patrick Schaumont, Krste Asanovic, James C. Hoe	MEMOCODE 2008 Co-Design Contest.	MEMOCODE	2008	DBLP DOI BibTeX RDF
21	Sachoun Park, Gihwon Kwon	Avoidance of State Explosion Using Dependency Analysis in Model Checking Control Flow Model.	ICCSA (5)	2006	DBLP DOI BibTeX RDF	Model checking, Dependency analysis, Model reduction, State explosion problem
21	Sachoun Park, Gihwon Kwon, Soonhoi Ha	Formalization of fFSM Model and Its Verification.	ICESS	2005	DBLP DOI BibTeX RDF	Step semantics, Model checking, Formal verification, Finite state machine
21	Medard Rieder, Rico Steiner, Cathy Berthouzoz, Francois Corthay, Thomas Sterren	Synthesized UML, a Practical Approach to Map UML to VHDL.	RISE	2005	DBLP DOI BibTeX RDF
21	P. Garg, Aseem Gupta, Jerzy W. Rozenblit	Performance Analysis of Embedded Systems in the Virtual Component Co-Design Environment.	ECBS	2004	DBLP DOI BibTeX RDF
21	Pao-Ann Hsiung	CMAPS: a cosynthesis methodology for application-oriented parallel systems.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	application-oriented general-purpose multiprocessors, hardware-software modeling and cosynthesis, requirements analysis
21	Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice	A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
21	Miodrag Potkonjak, Jan M. Rabaey	Algorithm selection: a quantitative optimization-intensive approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
21	Pao-Ann Hsiung	Hardware-software coverification of concurrent embedded real-time systems.	ECRTS	1999	DBLP DOI BibTeX RDF
21	William Fornaciari, Donatella Sciuto	HW/SW Co-design of Embedded Systems.	Ada-Europe	1999	DBLP DOI BibTeX RDF
21	Anupam Basu, Raj S. Mitra, Peter Marwedel	Interface Synthesis for Embedded Applications in a Co Design Environment.	VLSI Design	1998	DBLP DOI BibTeX RDF
21	Thomas Egolf, Mark Pettigrew, James Debardelaben, Rahmi Hezar, Shahram Famorzadeh, Anil Kumar Kavipurapu, Moinul H. Khan, Lan-Rong Dung, Kasyapa Balemarthy, Neeraj Desai, Vijay K. Madisetti	VHDL-based rapid system prototyping.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
21	Xiaobo Hu 0001, Garrison W. Greenwood, Joseph G. D'Ambrosio	An Evolutionary Approach to Hardware/ Software Partitioning.	PPSN	1996	DBLP DOI BibTeX RDF
21	Paul-Gerhard Plöger, Jörg Wilberg, Michel Langevin, Raul Camposano	WWW based structuring of codesigns.	ISSS	1995	DBLP DOI BibTeX RDF	WWW based structuring, design by documentation, hypertext documents, World Wide Web, World Wide Web (WWW), hypermedia, systems analysis, codesigns, Mosaic, information networks, documentation generation, WWW browser
16	Abanoub M. Girgis, Hyowoon Seo, Jihong Park, Mehdi Bennis	Semantic and Logical Communication-Control Codesign for Correlated Dynamical Systems.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
16	Xiaolin Wang, Jinglong Zhang, Cailian Chen, Jianping He 0001, Yehan Ma, Xinping Guan	Trust-AoI-Aware Codesign of Scheduling and Control for Edge-Enabled IIoT Systems.	IEEE Trans. Ind. Informatics	2024	DBLP DOI BibTeX RDF
16	Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen 0001, Yi Kang	Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
16	Hanning Chen, Yang Ni, Ali Zakeri, Zhuowen Zou, Sanggeon Yun, Fei Wen, Behnam Khaleghi, Narayan Srinivasa, Hugo Latapie, Mohsen Imani	HDReason: Algorithm-Hardware Codesign for Hyperdimensional Knowledge Graph Reasoning.	CoRR	2024	DBLP DOI BibTeX RDF
16	Chunyu Xue, Weihao Cui, Han Zhao, Quan Chen 0002, Shulai Zhang, Pengyu Yang, Jing Yang, Shaobo Li, Minyi Guo	A Codesign of Scheduling and Parallelization for Large Model Training in Heterogeneous Clusters.	CoRR	2024	DBLP DOI BibTeX RDF
16	Sophia Fuhui Lin, Joshua Viszlai, Kaitlin N. Smith, Gokul Subramanian Ravi, Charles Yuan, Frederic T. Chong, Benjamin J. Brown	Codesign of quantum error-correcting codes and modular chiplets in the presence of defects.	ASPLOS (2)	2024	DBLP DOI BibTeX RDF
16	James A. Ang, Kevin J. Barker, Draguna L. Vrabie, Gokcen Kestor	Codesign for Extreme Heterogeneity: Integrating Custom Hardware With Commodity Computing Technology to Support Next-Generation HPC Converged Workloads.	IEEE Internet Comput.	2023	DBLP DOI BibTeX RDF
16	Brenda Mariana Hernández-Morales, Sandra Díaz-Santiago, Cuauhtemoc Mancillas-López	Codesign for Generation of Large Random Sequences on Zynq FPGA.	IEEE Embed. Syst. Lett.	2023	DBLP DOI BibTeX RDF
16	Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen 0001, Yi Kang	Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Minghao Cheng, Di Li 0001, Nan Zhou 0004, Hao Tang 0004, Ge Wang, Shipeng Li 0003, Uzair Aslam Bhatti, Muhammad Khurram Khan	Vision-Motion Codesign for Low-Level Trajectory Generation in Visual Servoing Systems.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
16	Gillian R. Hayes, Candice L. Odgers, Julie A. Kientz, Jason C. Yip 0001, Kiley Sobel, Morgan Ames, Anamara Ritt Olson	Codesign and the Art of Creating a Global Research-Practice Network Built for Impact.	Interactions	2023	DBLP DOI BibTeX RDF
16	Jianchen Hu, Xingqi Li, Zhanbo Xu, Hongguang Pan	Codesign of Quantized Dynamic Output Feedback MPC for the Takagi-Sugeno Model.	IEEE Trans. Ind. Informatics	2023	DBLP DOI BibTeX RDF
16	Xufeng He, Feilong Lin, Minglu Li 0001	Codesign of Industrial Wireless Sensor Networks and Consensus-Based Sequential Estimation for Process Industries.	IEEE Trans. Ind. Informatics	2023	DBLP DOI BibTeX RDF
16	Jillian L. Warren, Alissa Nicole Antle, Alexandra Kitson, Alireza Davoodi	A codesign study exploring needs, strategies, and opportunities for digital health platforms to address pandemic-related impacts on children and families.	Int. J. Child Comput. Interact.	2023	DBLP DOI BibTeX RDF
16	Jeffrey S. Vetter, Prasanna Date, Farah Fahim, Shruti R. Kulkarni, Petro Maksymovych, A. Alec Talin, Marc González Tallada, Pruek Vanna-Iampikul, Aaron R. Young, David Brooks 0001, Yu Cao 0001, Gu-Yeon Wei, Sung Kyu Lim, Frank Liu 0001, Matthew J. Marinella, Bobby G. Sumpter, Narasinga Rao Miniskar	Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials.	Int. J. High Perform. Comput. Appl.	2023	DBLP DOI BibTeX RDF
16	Judith Odili Uchidiuno, Jaemarie Solyst, Jonaya Kemper, Erik Harpstead, Ross Higashi, Jessica Hammer	"What's Your Name Again?": How Race and Gender Dynamics Impact Codesign Processes and Output.	ACM Trans. Comput. Hum. Interact.	2023	DBLP DOI BibTeX RDF
16	Shreshth Tuli, Giuliano Casale, Nicholas R. Jennings	SciNet: Codesign of Resource Management in Cloud Computing Environments.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
16	Shengnan Shi, Zishu He, Ziyang Cheng	Codesign for Hybrid MU-MIMO Communication and MIMO Radar Systems Based on Mutual Information.	IEEE Syst. J.	2023	DBLP DOI BibTeX RDF
16	Carlotta Sartore, Lorenzo Rapetti, Fabio Bergonti, Stefano Dafarra, Silvio Traversaro, Daniele Pucci	Codesign of Humanoid Robots for Ergonomy Collaboration with Multiple Humans via Genetic Algorithms and Nonlinear Optimization.	CoRR	2023	DBLP DOI BibTeX RDF
16	Luke McDermott, Jason Weitz, Dmitri Demler, Daniel Cummings, Nhan Tran, Javier M. Duarte	Neural Architecture Codesign for Fast Bragg Peak Analysis.	CoRR	2023	DBLP DOI BibTeX RDF
16	Mikail Yayla, Simon Thomann, Ming-Liang Wei, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch	HW/SW Codesign for Robust and Efficient Binarized SNNs by Capacitor Minimization.	CoRR	2023	DBLP DOI BibTeX RDF
16	Jaemarie Solyst, Judith Odili Uchidiuno, Erik Harpstead, Jonaya Kemper, Ross Higashi	Comparative Design-Based Research: How Afterschool Programs Impact Learners' Engagement with a Video Game Codesign.	CoRR	2023	DBLP DOI BibTeX RDF
16	Malith Gallage, Rafaela Scaciota, Sumudu Samarakoon, Mehdi Bennis	Codesign of Edge Intelligence and Automated Guided Vehicle Control.	CoRR	2023	DBLP DOI BibTeX RDF
16	Javier Campos, Zhen Dong, Javier M. Duarte, Amir Gholami, Michael W. Mahoney, Jovan Mitrevski, Nhan Tran	End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICs.	CoRR	2023	DBLP DOI BibTeX RDF
16	Abhilasha Dave, Fabio Frustaci, Fanny Spagnolo, Mikail Yayla, Jian-Jia Chen, Hussam Amrouch	HW/SW Codesign for Approximation-Aware Binary Neural Networks.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Polianna Paim, Soraia Silva Prietch, J. Alfredo Sánchez 0001	Adapting Codesign Techniques for the Construction of a Learning Environment of a Written Second Language for the D/deaf.	Interact. Comput.	2023	DBLP DOI BibTeX RDF
16	Navid Hashemi, Justin Ruths	Codesign for Resilience and Performance.	IEEE Trans. Control. Netw. Syst.	2023	DBLP DOI BibTeX RDF
16	Syed Hammad Hussain Shah, Anniken Susanne Th. Karlsen, Mads Solberg, Ibrahim A. Hameed	A social VR-based collaborative exergame for rehabilitation: codesign, development and user study.	Virtual Real.	2023	DBLP DOI BibTeX RDF
16	Fabio Morbidi, Louise Devigne, Catalin-Stefan Teodorescu, Bastien Fraudet, Emilie Leblong, Tom Carlson, Marie Babel, Guillaume Caron, Sarah Delmas, François Pasteau, Guillaume Vailland, Valérie Gouranton, Sylvain Guégan, Ronan Le Breton, Nicolas Ragot	Assistive Robotic Technologies for Next-Generation Smart Wheelchairs: Codesign and Modularity to Improve Users' Quality of Life.	IEEE Robotics Autom. Mag.	2023	DBLP DOI BibTeX RDF
16	Douglas Cale Crowder, J. Darby Smith, Suma George Cardwell	AI-Enhanced Codesign of Neuromorphic Circuits.	MWSCAS	2023	DBLP DOI BibTeX RDF
16		International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2023, Hamburg, Germany, September 17-22, 2023	CODES+ISSS	2023	DBLP BibTeX RDF
16	Tom Glint, Kailash Prasad, Jinay Dagli, Krishil Gandhi, Aryan Gupta, Vrajesh Patel, Neel Shah, Joycee Mekie	Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers.	ASP-DAC	2023	DBLP DOI BibTeX RDF
16	Jeff Grasberger, Lisheng Yang, Giorgio Bacelli, Lei Zuo	Control Codesign Optimization of an Oscillating-Surge Wave Energy Converter.	ACC	2023	DBLP DOI BibTeX RDF
16	Chris van der Heide, Peter Cudmore, Ingo Jahn, Viv Bone, Peter M. Dower, Chris Manzie	Feasibility Detection for Nested Codesign of Hypersonic Vehicles.	CDC	2023	DBLP DOI BibTeX RDF
16	Ecivaldo de Souza Matos, Diego Zabot, Filipe Adeodato Garrido, Juliana Maria Oliveira Dos Santos	Towards alterity in interaction codesign.	IHC	2023	DBLP DOI BibTeX RDF
16	Valéria Argôlo Rosa, Ecivaldo de Souza Matos, Diego Zabot, Juliana Maria Oliveira Dos Santos	Online interaction codesign: an experience report with elderly women.	IHC	2023	DBLP DOI BibTeX RDF
16	Malith Gallage, Rafaela Scaciota, Sumudu Samarakoon, Mehdi Bennis	Artifact: Codesign of Edge Intelligence and Automated Guided Vehicle Control.	PerCom Workshops	2023	DBLP DOI BibTeX RDF
16	Malith Gallage, Rafaela Scaciota, Sumudu Samarakoon, Mehdi Bennis	Codesign of Edge Intelligence and Automated Guided Vehicle Control.	PerCom Workshops	2023	DBLP DOI BibTeX RDF
16	Catalina Ramirez, Sebastian Arevalo, Matteo Deponti, Federido DeAngulo, Paula Castro	Codesign Simple Technology to Automate the Irrigation of Small Crops in Rural Communities in Colombia.	EUROCON	2023	DBLP DOI BibTeX RDF
16	Carlotta Sartore, Lorenzo Rapetti, Fabio Bergonti, Stefano Dafarra, Silvio Traversaro, Daniele Pucci	Codesign of Humanoid Robots for Ergonomic Collaboration with Multiple Humans via Genetic Algorithms and Nonlinear Optimization.	Humanoids	2023	DBLP DOI BibTeX RDF
16	Nalika Ulapane, Abdur Rahim Mohammad Forkan, Prem Prakash Jayaraman, Penelope Schofield, Kate Burbury, Nilmini Wickramasinghe	Using Task Technology Fit Theory to Guide the Codesign of Mobile Clinical Decision Support Systems.	HICSS	2023	DBLP BibTeX RDF
16	Cuong Pham-Quoc	FPGA-Based Hardware/Software Codesign for Video Encoder on IoT Edge Platforms.	ICCSA (Workshops 5)	2023	DBLP DOI BibTeX RDF
16	Qiaochu Liang, Lei Gong, Chao Wang, Xuehai Zhou, Xi Li 0003	Work-in-Progress: NAPMAE: Generalized Data-Efficient Neural Architecture Predictor with Masked Autoencoder.	CODES+ISSS	2023	DBLP BibTeX RDF
16	Mohammad Abdullah Al Faruque, Muhammad Shafique 0001	Message from the Program Chair.	CODES+ISSS	2023	DBLP BibTeX RDF