Search results for "datapath"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Hua Li, Jianzhou Li	A New Compact Architecture for AES with Optimized ShiftRows Operation.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Jiang Long, Andrew Seawright	Synthesizing SVA Local Variables for Formal Verification.	DAC	2007	DBLP DOI BibTeX RDF
18	Vyas Krishnan, Srinivas Katkoori	A genetic algorithm for the design space exploration of datapaths during high-level synthesis.	IEEE Trans. Evol. Comput.	2006	DBLP DOI BibTeX RDF
18	Knockaert Radecka, Zeljko Zilic	Arithmetic transforms for compositions of sequential and imprecise datapaths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Salvatore Carta, Danilo Pani, Luigi Raffo	Reconfigurable Coprocessor for Multimedia Application Domain.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	multimedia, reconfigurable computing, digital signal processing, domain-specific architectures
18	Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev 0001	Adaptive reorder buffers for SMT processors.	PACT	2006	DBLP DOI BibTeX RDF	simultaneous multithreading, reorder buffer
18	Jaan Raik, Raimund Ubar, Taavi Viilukas	High-Level Decision Diagram based Fault Models for Targeting FSMs.	DSD	2006	DBLP DOI BibTeX RDF
18	Harmander Deogun, Dennis Sylvester, Kevin J. Nowka	Fine grained multi-threshold CMOS for enhanced leakage reduction.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda	Rapid estimation of control delay from high-level specifications.	DAC	2006	DBLP DOI BibTeX RDF	control delay, high level synthesis, estimation, FSM
18	Jason T. Higgins, Mark D. Aagaard	Simplifying the design and automating the verification of pipelines with structural hazards.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	formal design verification, design automation, Pipelined circuits
18	Vinu Vijay Kumar, John C. Lach	Highly flexible multi-mode system synthesis.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	multi-mode synthesis, reconfigurability, adaptable systems
18	Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu	Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
18	Koji Ohashi, Mineo Kaneko	Statistical Analysis Driven Synthesis of Asynchronous Systems.	ICCD	2005	DBLP DOI BibTeX RDF
18	Zhaojun Wo, Israel Koren, Maciej J. Ciesielski	An ILP Formulation for Yield-driven Architectural Synthesis.	DFT	2005	DBLP DOI BibTeX RDF
18	Andrei Sergeevich Terechko, Manish Garg, Henk Corporaal	Evaluation of Speed and Area of Clustered VLIW Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	David Moloney, Dermot Geraghty, Colm McSweeney, Ciarán McElroy	Streaming Sparse Matrix Compression/Decompression.	HiPEAC	2005	DBLP DOI BibTeX RDF
18	Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak	Flexible ASIC: shared masking for multiple media processors.	DAC	2005	DBLP DOI BibTeX RDF	optimization, interconnect, ASIC
18	Ivan Blunno, Luciano Lavagno	Designing an asynchronous microcontroller using Pipefitter.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
18	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Efficient Design Diversity Estimation for Combinational Circuits.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	common-mode failures, reliability, fault-tolerant computing, dependability, Error detection, design diversity
18	Sune Fallgaard Nielsen, Jens Sparsø, Jan Madsen	Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation.	DSD	2004	DBLP DOI BibTeX RDF
18	Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	A cosynthesis algorithm for application specific processors with heterogeneous datapaths.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	Ashok K. Murugavel, N. Ranganathan	A game theoretic approach for power optimization during behavioral synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
18	Amit Singh 0001, Arindam Mukherjee 0001, Luca Macchiarulo, Malgorzata Marek-Sadowska	PITIA: an FPGA for throughput-intensive applications.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
18	Nam Ling, Nien-Tsu Wang	A Real-Time Video Decoder for Digital HDTV.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	HDTV video decoder, MPEG-2 MP@HL decoder, digital TV, HDTV, video decoding
18	Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija	Energy Optimization of High-Performance Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
18	Chandramouli Gopalakrishnan, Srinivas Katkoori	An Architectural Leakage Power Simulator for VHDL Structural Datapaths.	ISVLSI	2003	DBLP DOI BibTeX RDF
18	María C. Molina, José M. Mendías, Román Hermida	Multiple-Precision Circuits Allocation Independent of Data-Objects Length.	DATE	2002	DBLP DOI BibTeX RDF
18	Katarzyna Radecka, Zeljko Zilic	Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms.	ICCAD	2002	DBLP DOI BibTeX RDF
18	Ruby B. Lee, A. Murat Fiskiran, Zhijie Shi, Xiao Yang 0001	Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments.	ASAP	2002	DBLP DOI BibTeX RDF
18	Zhining Huang, Sharad Malik	Exploiting operation level parallelism through dynamically reconfigurable datapaths.	DAC	2002	DBLP DOI BibTeX RDF
18	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Techniques for Estimation of Design Diversity for Combinational Logic Circuits.	DSN	2001	DBLP DOI BibTeX RDF
18	Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.	ISQED	2001	DBLP DOI BibTeX RDF
18	Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri	Application Specific Macro Based Synthesis.	VLSI Design	2001	DBLP DOI BibTeX RDF
18	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
18	M. Balakrishnan, Heman Khanna	Allocation of FIFO structures in RTL data paths.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	synthesis, RTL, ILP, FIFO, data path
18	Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino	Power Models for Semi-autonomous RTL Macros.	PATMOS	2000	DBLP DOI BibTeX RDF
18	Joan Carletta, Christos A. Papachristou, Mehrdad Nourani	Detecting Undetectable Controller Faults Using Power Analysis.	DATE	2000	DBLP DOI BibTeX RDF
18	Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Effective Low Power BIST for Datapaths.	DATE	2000	DBLP DOI BibTeX RDF
18	Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva	High-Level Asynchronous System Design Using the ACK Framework.	ASYNC	2000	DBLP DOI BibTeX RDF
18	Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei	Regression-based RTL power models for controllers.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
18	Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Low Power/Energy BIST Scheme for Datapaths.	VTS	2000	DBLP DOI BibTeX RDF
18	Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	The design and use of simplepower: a cycle-accurate energy estimation tool.	DAC	2000	DBLP DOI BibTeX RDF
18	Bojana Obrenic, Martin C. Herbordt, Arnold L. Rosenberg, Charles C. Weems	Using Emulations to Enhance the Performance of Parallel Architectures.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	parallel algorithms, Parallel architecture, multiprocessor interconnection
18	Christos A. Papachristou, Yusuf Alzazeri	A Method of Distributed Controller Design for RTL Circuits.	DATE	1999	DBLP DOI BibTeX RDF
18	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.	VTS	1999	DBLP DOI BibTeX RDF
18	Alex Orailoglu	On-Line Fault Resilience Through Gracefully Degradable ASICs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	fault tolerant ICs, reconfigurable ASICs, high level synthesis, on-line test, graceful degradation
18	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
18	Maya B. Gokhale, Janice M. Stone	NAPA C: Compiling for a Hybrid RISC/FPGA Architecture.	FCCM	1998	DBLP DOI BibTeX RDF
18	James H. Kukula, Thomas R. Shiple, Adnan Aziz	Techniques for Implicit State Enumeration of EFSMs.	FMCAD	1998	DBLP DOI BibTeX RDF
18	Srinivasa Rao Arikati, Ravi Varadarajan	A signature based approach to regularity extraction.	ICCAD	1997	DBLP DOI BibTeX RDF	regular structure extraction, Physical design
18	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
18	Paul E. Landman, Jan M. Rabaey	Activity-sensitive architectural power analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen	VASS - A VLSI array system synthesizer.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
18	Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002	Two-Level Hardware/Software Partitioning Using CoDe-X.	ECBS	1996	DBLP DOI BibTeX RDF
18	Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002	Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine.	CODES	1996	DBLP DOI BibTeX RDF
18	Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002, Helmut Reinig	CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework.	VLSI Design	1996	DBLP DOI BibTeX RDF
18	John A. Nestor	Visual register-transfer description of VLSI microarchitectures.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
17	William B. Toms, David A. Edwards	A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths.	ACSD	2010	DBLP DOI BibTeX RDF	Asynchronous Combinational Logic Synthesis, Datapath Synthesis
17	Keisuke Inoue, Mineo Kaneko	A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	ordered clocking, resource assignment, datapath synthesis
17	Ronny Krashinsky, Christopher Batten, Krste Asanovic	Implementing the scale vector-thread processor.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hybrid C++/Verilog simulation, iterative VLSI design flow, procedural datapath pre-placement, vector-thread processors, multithreaded processors, Vector processors
17	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing
17	Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara	An Effective Design for Hierarchical Test Generation Based on Strong Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	Hierarchical test generation, strong testability, datapath, test plan
17	Sebastian Wallner	A Reconfigurable Multi-threaded Architecture Model.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF	Computation Threads, Hardware Virtualization, Datapath Processor, Pipelining, Reconfigurable Architectures
17	Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Power efficient comparators for long arguments in superscalar processors.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power comparators, superscalar datapath
17	Amitabh Menon, S. K. Nandy 0001, Mahesh Mehendale	Multivoltage scheduling with voltage-partitioned variable storage.	ISLPED	2003	DBLP DOI BibTeX RDF	multivoltage, high level synthesis, datapath synthesis
17	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Reducing reorder buffer complexity through selective operand caching.	ISLPED	2003	DBLP DOI BibTeX RDF	low-complexity datapath, short-lived values, low-power design, reorder buffer
17	Laurence Goodby, Alex Orailoglu, Paul M. Chau	Microarchitectural synthesis of performance-constrained, low-power VLSI designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	DSP datapath design, High-level synthesis, low-power design
17	Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman	PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	high-level hardware synthesis, automatic parallelization, datapath synthesis
17	Gurhan Kucuk, Dmitry Ponomarev 0001, Kanad Ghose	Low-complexity reorder buffer architecture.	ICS	2002	DBLP DOI BibTeX RDF	low-complexity datapath, low-power design, reorder buffer
17	Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev 0001, Peter M. Kogge	Energy: efficient instruction dispatch buffer design for superscalar processors.	ISLPED	2001	DBLP DOI BibTeX RDF	bitline segmentation, low power comparator, low power instruction scheduling, low-power superscalar datapath
17	V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed	A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.	ASAP	2000	DBLP DOI BibTeX RDF	disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations
17	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre	BISTing Datapaths under Heterogeneous Test Schemes.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	RT level, BIST, datapath, test synthesis
17	Mark C. Johnson, Kaushik Roy 0001	Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints.	ICCD	1996	DBLP DOI BibTeX RDF	level conversion, voltage selection, scheduling, low-power, synthesis, DSP, ILP, resource constraints, datapath
17	Jin-O. Seo, Mingoo Seok, SeongHwan Cho	A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
17	Junxue Zhang 0001, Chaoliang Zeng, Hong Zhang 0025, Shuihai Hu, Kai Chen 0005	LiteFlow: Toward High-Performance Adaptive Neural Networks for Kernel Datapath.	IEEE/ACM Trans. Netw.	2024	DBLP DOI BibTeX RDF
17	Kari Hepola, Joonas Multanen, Pekka Jääskeläinen	Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
17	Xuzheng Chen, Jie Zhang, Ting Fu, Yifan Shen, Shu Ma, Kun Qian, Lingjun Zhu, Chao Shi, Yin Zhang, Ming Liu, Zeke Wang	Demystifying Datapath Accelerator Enhanced Off-path SmartNIC.	CoRR	2024	DBLP DOI BibTeX RDF
17	Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura	High Throughput Datapath Design for Vision Permutator FPGA Accelerator.	ICCE	2024	DBLP DOI BibTeX RDF
17	Aditya Anshul, Anirban Sengupta	PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis.	Expert Syst. Appl.	2023	DBLP DOI BibTeX RDF
17	Jun-Seok Park, Changsoo Park, Suknam Kwon, Taeho Jeon, Yesung Kang, Heonsoo Lee, Dongwoo Lee, James Kim, Hyeong-Seok Kim, YoungJong Lee, Sangkyu Park, MinSeong Kim, Sanghyuck Ha, Jihoon Bang, Jinpyo Park, Sukhwan Lim, Inyup Kang	A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
17	Giovanni Quintarelli, Matteo Bertolucci, Pietro Nannipieri	Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry.	IEEE Access	2023	DBLP DOI BibTeX RDF
17	Pedro Tauã Lopes Pereira, Guilherme Paim, Eduardo Antônio César da Costa, Sérgio Jose Melo de Almeida, Sergio Bampi	ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
17	Ionel Zagan, Vasile Gheorghita Gaitan	Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation.	PeerJ Comput. Sci.	2023	DBLP DOI BibTeX RDF
17	Steven Lyons, Raju Rangaswami, Ning Xie	Finding optimal non-datapath caching strategies via network flow.	Theor. Comput. Sci.	2023	DBLP DOI BibTeX RDF
17	Samuel Coward, George A. Constantinides, Theo Drane	Automating Constraint-Aware Datapath Optimization using E-Graphs.	CoRR	2023	DBLP DOI BibTeX RDF
17	Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides	Datapath Verification via Word-Level E-Graph Rewriting.	CoRR	2023	DBLP DOI BibTeX RDF
17	Hongyu Fan, Fei He 0001	Leveraging Datapath Propagation in IC3 for Hardware Model Checking.	CoRR	2023	DBLP DOI BibTeX RDF
17	Denis Salopek, Miljenko Mikuc	Enhancing Mitigation of Volumetric DDoS Attacks: A Hybrid FPGA/Software Filtering Datapath.	Sensors	2023	DBLP DOI BibTeX RDF
17	Katharina Ruep, Daniel Große	Improving Design Understanding of Processors leveraging Datapath Clustering.	DATE	2023	DBLP DOI BibTeX RDF
17	Dushyant Behl, Hai Huang 0002, Palanivel A. Kodeswaran, Sayandeep Sen	On eBPF extensions to Kubernetes CNI datapath#.	COMSNETS	2023	DBLP DOI BibTeX RDF
17	Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura	Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
17	Zhihan Chen, Xindi Zhang, Yuhang Qian, Qiang Xu 0001, Shaowei Cai 0001	Integrating Exact Simulation into Sweeping for Datapath Combinational Equivalence Checking.	ICCAD	2023	DBLP DOI BibTeX RDF
17	Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides	Datapath Verification via Word-Level E-Graph Rewriting.	FMCAD	2023	DBLP DOI BibTeX RDF
17	Johannes Knödtel, Marc Reichenbach	Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration.	DroneSE/RAPIDO@HiPEAC	2023	DBLP DOI BibTeX RDF
17	Ecenur Ustun, Cunxi Yu, Zhiru Zhang	Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality.	DAC	2023	DBLP DOI BibTeX RDF
17	Samuel Coward, George A. Constantinides, Theo Drane	Automating Constraint-Aware Datapath Optimization using E-Graphs.	DAC	2023	DBLP DOI BibTeX RDF
17	Seyedeh Fatemeh Ghamkhari, Mohammad Bagher Ghaznavi Ghoushchi	A power-performance partitioning approach for low-power DA-based FIR filter design with emphasis on datapath and controller.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Samuel Coward, George A. Constantinides, Theo Drane	Automatic Datapath Optimization using E-Graphs.	CoRR	2022	DBLP DOI BibTeX RDF
17	Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie 0001	Alleviating Datapath Conflicts and Design Centralization in Graph Analytics Acceleration.	CoRR	2022	DBLP BibTeX RDF
17	Donghyun Kang, Soonhoi Ha	Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF