Search results for "fanout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Stefan Blom, Simona Orzan	Distributed state space minimization.	Int. J. Softw. Tools Technol. Transf.	2005	DBLP DOI BibTeX RDF	Distributed verification, Bisimulation equivalence
12	Xinyu Guo, Carl Sechen	High Speed Redundant Adder and Divider in Output Prediction Logic.	ISVLSI	2005	DBLP DOI BibTeX RDF
12	Jay Kumar Sundararajan, Supratim Deb, Muriel Médard	Extending the Birkhoff-Von Neumann Switching Strategy to Multicast Switches.	NETWORKING	2005	DBLP DOI BibTeX RDF
12	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura	Low Power Test Compression Technique for Designs with Multiple Scan Chain.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
12	Emil Axelsson, Koen Claessen, Mary Sheeran	Wired: Wire-Aware Circuit Design.	CHARME	2005	DBLP DOI BibTeX RDF
12	Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi	Modeling QCA Defects at Molecular-level in Combinational Circuits.	DFT	2005	DBLP DOI BibTeX RDF	fault model, emerging technology, defect tolerance, QCA
12	Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura	Cooperation of Neighboring PEs in Clustered Architectures.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
12	Kartik Mohanram	Closed-Form Simulation and Robustness Models for SEU-Tolerant Design.	VTS	2005	DBLP DOI BibTeX RDF
12	Karthik Pattabiraman, Zbigniew Kalbarczyk, Ravishankar K. Iyer	Application-Based Metrics for Strategic Placement of Detectors.	PRDC	2005	DBLP DOI BibTeX RDF
12	Fatih Kocan, Mehmet Hadi Gunes	Acyclic circuit partitioning for path delay fault emulation.	AICCSA	2005	DBLP DOI BibTeX RDF
12	Sumio Morioka, Akashi Satoh	A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
12	Jason Helge Anderson, Farid N. Najm	Power estimation techniques for FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
12	Hanan Samet	Decoupling partitioning and grouping: Overcoming shortcomings of spatial indexing with bucketing.	ACM Trans. Database Syst.	2004	DBLP DOI BibTeX RDF	BV-trees, PK-trees, space decomposition, R-trees, decoupling, Spatial indexing, object hierarchies
12	Matthew M. Ziegler, Mircea R. Stan	A Unified Design Space for Regular Parallel Prefix Adders.	DATE	2004	DBLP DOI BibTeX RDF	Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder
12	Saravanan Padmanaban, Spyros Tragoudas	Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults.	DATE	2004	DBLP DOI BibTeX RDF
12	Maher N. Mneimneh, Karem A. Sakallah, John Moondanos	Preserving synchronizing sequences of sequential circuits after retiming.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Jason Helge Anderson, Farid N. Najm	Interconnect capacitance estimation for FPGAs.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Soft Delay Error Effects in CMOS Combinational Circuits.	VTS	2004	DBLP DOI BibTeX RDF	Soft delay, single event upsets (SEUs), soft error rate (SER), soft errors
12	Anders Gunnar, Mikael Johansson 0001, Thomas Telkamp	Traffic matrix estimation on a large IP backbone: a comparison on real data.	Internet Measurement Conference	2004	DBLP DOI BibTeX RDF	optimization, MPLS, SNMP, traffic matrix estimation
12	Tatsuhiro Tsuchiya, Tohru Kikuno	An Adaptive Mechanism for Epidemic Communication.	BioADIT	2004	DBLP DOI BibTeX RDF
12	José Pereira 0001, Luís E. T. Rodrigues, Alexandre S. Pinto, Rui Oliveira 0001	Low Latency Probabilistic Broadcast in Wide Area Networks.	SRDS	2004	DBLP DOI BibTeX RDF
12	Ingmar Neumann, Wolfgang Kunz	Layout driven retiming using the coupled edge timing model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
12	Shi-Yu Huang	A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	diagnosis, symbolic simulation, Byzantine fault
12	Yee William Li, George Patounakis, Anup P. Jose, Kenneth L. Shepard, Steven M. Nowick	Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application.	ASYNC	2003	DBLP DOI BibTeX RDF
12	Myoung Hun Kim, Hong-Shik Park	An Integrated Scheduling for Multiple Loss Priority Traffic in E-PON OLT Switches.	Art-QoS	2003	DBLP DOI BibTeX RDF
12	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A Family of Parallel-Pre.x Modulo 2n - 1 Adders.	ASAP	2003	DBLP DOI BibTeX RDF
12	Sayed Vahid Azhari, Nasser Yazdani, Ali Mohammad Zareh Bidoki	Providing Delay Guarantee in Input Queued Switches: A Comparative Analysis of Scheduling Algorithms.	ICOIN	2003	DBLP DOI BibTeX RDF
12	Peter Wohl, Leendert M. Huisman	Analysis and Design of Optimal Combinational Compactors.	VTS	2003	DBLP DOI BibTeX RDF
12	Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta 0001, Melvin A. Breuer	Analyzing Crosstalk in the Presence of Weak Bridge Defects.	VTS	2003	DBLP DOI BibTeX RDF
12	Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell	A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF
12	Navin Vemuri, Priyank Kalla, Russell Tessier	BDD-based logic synthesis for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, decomposition, logic synthesis, BDD
12	Luís Guerra e Silva, João Marques-Silva 0001, Luís Miguel Silveira, Karem A. Sakallah	Satisfiability models and algorithms for circuit delay computation.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	circuit delay computation, timing analysis, Boolean satisfiability, delay modeling, false path
12	John Moses, Malcolm Farrow, Peter Smith	Statistical Methods for Predicting and Improving Cohesion Using Information Flow: An Empirical Study.	Softw. Qual. J.	2002	DBLP DOI BibTeX RDF	information flow measures, cohesion prediction systems, empirical relations, ordinal cohesion scales, binary and ordinal logistic regression, cohesion
12	Yasushi Sakurai, Masatoshi Yoshikawa, Shunsuke Uemura, Haruhiko Kojima	Spatial indexing of high-dimensional data based on relative approximation.	VLDB J.	2002	DBLP DOI BibTeX RDF	Relative approximation, Similarity search, High-dimensional data
12	Bassam Shaer, Khaled Dib	An Efficient Partitioning Algorithm of Combinational CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF	partitioning, pseudoexhaustive testing
12	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Congestion-Aware Logic Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
12	Olaf Maennel, Anja Feldmann	Realistic BGP traffic for test labs.	SIGCOMM	2002	DBLP DOI BibTeX RDF	BGP, workload
12	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
12	Jiong Yang 0001, Wei Wang 0010, Yi Xia, Philip S. Yu	Accelerating Approximate Subsequence Search on Large Protein Sequence Databases.	CSB	2002	DBLP DOI BibTeX RDF
12	Amit Singh 0001, Malgorzata Marek-Sadowska	FPGA interconnect planning.	SLIP	2002	DBLP DOI BibTeX RDF
12	Sumio Morioka, Akashi Satoh	A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture.	ICCD	2002	DBLP DOI BibTeX RDF
12	Shi-Yu Huang	Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation.	VTS	2002	DBLP DOI BibTeX RDF
12	Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu	An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.	PRDC	2002	DBLP DOI BibTeX RDF
12	Srinath R. Naidu	Timing Yield Calculation Using an Impulse-Train Approach.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
12	Cheng-Shang Chang, Duan-Shin Lee, Ching-Ming Lien	Load balanced Birkhoff-von Neumann switches with resequencing.	SIGMETRICS Perform. Evaluation Rev.	2001	DBLP DOI BibTeX RDF
12	David B. Lomet	The Evolution of Effective B-tree: Page Organization and Techniques: A Personal Account.	SIGMOD Rec.	2001	DBLP DOI BibTeX RDF
12	Mike Sheng, Jonathan Rose	Mixing buffers and pass transistors in FPGA routing architectures.	FPGA	2001	DBLP DOI BibTeX RDF
12	PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia	fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits.	FPL	2001	DBLP DOI BibTeX RDF
12	Simon Knowles	A Family of Adders.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
12	Kihong Kim, Sang Kyun Cha, Keunjoo Kwon	Optimizing Multidimensional Index Trees for Main Memory Access.	SIGMOD Conference	2001	DBLP DOI BibTeX RDF
12	Bhaskaran Raman, Pravin Bhagwat, Srinivasan Seshan	Arguments for Cross-Layer Optimizations in Bluetooth Scatternets.	SAINT	2001	DBLP DOI BibTeX RDF
12	Eelco Rouw, Jaap Hoekstra, Arthur H. M. van Roermund	Spike correlation based learning for unsupervised neural lattice structures.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
12	Wen-Yu Tseng, Sy-Yen Kuo	All-Optical Multicasting on Wavelength-Routed WDM Networks with Partial Replica.	ICOIN	2001	DBLP DOI BibTeX RDF
12	Kelly A. Ockunzzi, Christos A. Papachristou	Breaking Correlation to Improve Testability.	VTS	2001	DBLP DOI BibTeX RDF	BIST, DFT, Test Synthesis
12	Supratik Chakraborty, Rajeev Murgai	Complexity Of Minimum-Delay Gate Resizing.	VLSI Design	2001	DBLP DOI BibTeX RDF
12	Bassam Shaer, David L. Landis, Sami A. Al-Arian	Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
12	Bassam Shaer, Sami A. Al-Arian, David L. Landis	Partitioning sequential circuits for pseudoexhaustive testing.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
12	Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski	Retiming-based factorization for sequential logic optimization.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	finite stat machines, retiming, sequential synthesis
12	Eric Keller	JRoute: A Run-Time Routing API for FPGA Hardware.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
12	Yibin Ye, Kaushik Roy 0001, Rolf Drechsler	Power Consumption in XOR-Based Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
12	Dongsheng Wang 0012, Ping Zhang 0001, Chung-Kuan Cheng, Arunabha Sen	A Performance-Driven I/O Pin Routing Algorithm.	ASP-DAC	1999	DBLP DOI BibTeX RDF
12	Simon Knowles	A Family of Adders.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
12	Rajeev Murgai	Performance optimization under rise and fall parameters.	ICCAD	1999	DBLP DOI BibTeX RDF
12	Bassam Shaer, Sami A. Al-Arian, David L. Landis	Pseudo-Exhaustive Testing of Sequential Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
12	Patrick Fay, Gary H. Bernstein, David H. Chow, Joel N. Schulman, Pinaki Mazumder, William Williamson III, Barry K. Gilbert	Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	resonant tunneling diode (RTD), resonant interband tunneling diode (RITD), heterostructure field-effect transistor (HFET), ultra-high-speed logic circuits
12	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	A Test Generator for Segment Delay Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
12	Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya	Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions.	DATE	1998	DBLP DOI BibTeX RDF	simple disjunctive decomposition, symmetric variables, multi-level logic circuit, ordered binary decision diagram
12	Zhongcheng Li, Yinghua Min, Robert K. Brayton	A New Low-Cost Method for Identifying Untestable Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF	non-robustly untestable, Delay testing, path delay fault, implication
12	W. Kwon, Boseob Kwon, Jae-Hyun Park, Hyunsoo Yoon	Two-phase Multicast in Wormhole-Switched Bidirectional Multistage Banyan Networks.	ICPP	1998	DBLP DOI BibTeX RDF
12	Jui-Ming Chang, Massoud Pedram	Energy minimization using multiple supply voltages.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
12	Supratik Chakraborty, David L. Dill	More Accurate Polynomial-Time Min-Max Timing Simulation.	ASYNC	1997	DBLP DOI BibTeX RDF	Uncertain component delays, min-max timing simulation, thirteen-valued signal algebra, polynomial-time algorithm
12	Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu	Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.	ICCAD	1997	DBLP DOI BibTeX RDF
12	Jason Cong, Wilburt Labio, Narayanan Shivakumar	Multiway VLSI circuit partitioning based on dual net representation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Krishnendu Chakrabarty, John P. Hayes	Test response compaction using multiplexed parity trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Irith Pomeranz, Sudhakar M. Reddy	On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF
12	Sujit Dey, Srimat T. Chakradhar	Design of testable sequential circuits by repositioning flip-flops.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault
12	Baher Haroun, Behzad Sajjadi	Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.	FPGA	1995	DBLP DOI BibTeX RDF
12	Tanay Karnik, Sung-Mo Kang	An empirical model for accurate estimation of routing delay in FPGAs.	ICCAD	1995	DBLP DOI BibTeX RDF	Routing Delay, Modeling, FPGA, Estimation, Statistics
12	Xiaobo Sharon Hu, Steven C. Bass, Ronald G. Harber	Minimizing the number of delay buffers in the synchronization of pipelined systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
12	Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell	Energy minimization and design for testability.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	neural networks, graph theory, energy minimization, digital testing, Combinational logic circuits
12	Marianne E. Louie, Milos D. Ercegovac	Implementing division with field programmable gate arrays.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
12	Ohyoung Song, Premachandran R. Menon	3-valued trace-based fault simulation of synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Ohyoung Song, Premachandran R. Menon	Acceleration of trace-based fault simulation of combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Thomas K. Callaway, Earl E. Swartzlander Jr.	Estimating the power consumption of CMOS adders.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
12	Marianne E. Louie, Milos D. Ercegovac	On digit-recurrence division implementations for field programmable gate arrays.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
12	Vijay S. Iyengar, Gopalakrishnan Vijayan	Optimized test application timing for AC test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
12	Patrick Kam Lui, Jon C. Muzio	Constrained parity testing.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	compaction testing, parity testing, Built-in self-test, signature analysis
12	David M. Nicol	Performance Bounds on Parallel Self-Initiating Discrete-Event Simulations.	ACM Trans. Model. Comput. Simul.	1991	DBLP DOI BibTeX RDF	parallel simulation, synchronization protocol
12	Robert J. Francis, Jonathan Rose, Kevin Chung	Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays.	DAC	1990	DBLP DOI BibTeX RDF
12	Noriyuki Ito	Automatic Incorporation of On-Chip Testability Circuits.	DAC	1990	DBLP DOI BibTeX RDF
12	Kaushik Roy 0001, Jacob A. Abraham	A Novel Approach to Accurate Timing Verification Using RTL Descriptions.	DAC	1989	DBLP DOI BibTeX RDF
12	Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler	CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology.	DAC	1988	DBLP BibTeX RDF
12	M. Ladjadj, John F. McDonald 0001, D.-H. Ho, W. Murray Jr.	Use of the subscripted DALG in submodule testing with applications in cellular arrays.	DAC	1986	DBLP DOI BibTeX RDF
12	Donald L. Richards	Efficient Exercising of Switching Elements in Nets of Identical Gates.	J. ACM	1973	DBLP DOI BibTeX RDF