Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Amir Moradi 0001, Oliver Mischke |
On the Simplicity of Converting Leakages from Multivariate to Univariate - Case Study of a Glitch-Resistant Masking Scheme - ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2012, pp. 472, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
20 | Jing Jin 0005, Xiaoming Liu 0008, Tingting Mo, Jianjun Zhou |
Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(5), pp. 926-937, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Amir Fathi, Sarkis Azizian, Rahim Fathi, Habib Ghasemizadeh Tamar |
Low latency, glitch-free booth encoder-decoder for high speed multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 9(16), pp. 1335-1341, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Dai Yamamoto, Gabriel Hospodar, Roel Maes, Ingrid Verbauwhede |
Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPACE ![In: Security, Privacy, and Applied Cryptography Engineering - Second International Conference, SPACE 2012, Chennai, India, November 3-4, 2012. Proceedings, pp. 45-62, 2012, Springer, 978-3-642-34415-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Mariem Slimani, Philippe Matherat, Yves Mathieu |
A dual threshold voltage technique for glitch minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 444-447, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria |
Identification of soft error glitch-propagation paths: Leveraging SAT solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 3258-3261, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Amir Moradi 0001, Oliver Mischke |
Glitch-free implementation of masking in modern FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2012, San Francisco, CA, USA, June 3-4, 2012, pp. 89-95, 2012, IEEE Computer Society, 978-1-4673-2341-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Hongying Liu, Guoyu Qian, Yukiyasu Tsunoo, Satoshi Goto |
The Switching Glitch Power Leakage Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Softw. ![In: J. Softw. 6(9), pp. 1787-1794, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin |
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptol. ![In: J. Cryptol. 24(2), pp. 247-268, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Will Tracz |
Glitch: the hidden impact of faulty software by Jeff Papows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGSOFT Softw. Eng. Notes ![In: ACM SIGSOFT Softw. Eng. Notes 36(2), pp. 41, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Kesava R. Talupuru, Sanjai Athi |
Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011, pp. 5-9, 2011, IEEE Computer Society, 978-1-4577-2101-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Laure Berti-Équille, Tamraparni Dasu, Divesh Srivastava |
Discovery of complex glitch patterns: A novel approach to Quantitative Data Cleaning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: Proceedings of the 27th International Conference on Data Engineering, ICDE 2011, April 11-16, 2011, Hannover, Germany, pp. 733-744, 2011, IEEE Computer Society, 978-1-4244-8958-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria |
SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 358-361, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Warren Wai-Kit Shum, Jason Helge Anderson |
FPGA glitch power analysis and reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 27-32, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
20 | Xiaoming Liu 0008, Jing Jin 0005, Xi Li, Jianjun Zhou |
Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 478-481, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz |
A gate sizing method for glitch power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011, pp. 24-29, 2011, IEEE, 978-1-4577-1616-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita |
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2010, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Meng-Hung Shen, Jen-Huan Tsai, Po-Chiun Huang |
Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 57-II(5), pp. 369-373, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad |
Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8), pp. 2020-2031, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Amit Mondal, Ross Cutler, Cheng Huang 0002, Jin Li 0001, Aleksandar Kuzmanovic |
SureCall: Towards glitch-free real-time audio/video conferencing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWQoS ![In: 18th International Workshop on Quality of Service, IWQoS 2010, Beijing, China, 16-18 June 2010., pp. 1-9, 2010, IEEE, 978-1-4244-5987-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Dina Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, David Bol |
Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010, pp. 518-521, 2010, IEEE, 978-1-4244-6662-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Hongying Liu, Guoyu Qian, Satoshi Goto, Yukiyasu Tsunoo |
Correlation Power Analysis Based on Switching Glitch Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISA ![In: Information Security Applications - 11th International Workshop, WISA 2010, Jeju Island, Korea, August 24-26, 2010, Revised Selected Papers, pp. 191-205, 2010, Springer, 978-3-642-17954-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | William John Bainbridge, Sean James Salisbury |
Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009, pp. 35-44, 2009, IEEE Computer Society, 978-1-4244-3933-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Betsy James DiSalvo, Mark Guzdial, Tom McKlin, Charles Meadows, Kenneth Perry, Corey Steward, Amy S. Bruckman |
Glitch Game Testers: African American Men Breaking Open the Console. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DiGRA Conference ![In: Proceedings of the 2009 DiGRA International Conference: Breaking New Ground: Innovation in Games, Play, Practice and Theory, DiGRA 2009, London, UK, September 1-4, 2009, 2009, Digital Games Research Association. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
20 | Marco Zanuso, Salvatore Levantino, Davide Tasca, Daniele Raiteri, Carlo Samori, Andrea L. Lacaita |
A glitch-corrector circuit for low-spur ADPLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, pp. 595-598, 2009, IEEE, 978-1-4244-5090-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Ali Kiaei, Mounir Bohsali, Ahmad Bahai, Thomas H. Lee |
A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, Greece, 14-18 September 2009., pp. 372-375, 2009, IEEE, 978-1-4244-4354-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Xiao Dong, Guy G. F. Lemieux |
PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009, pp. 88-95, 2009, IEEE Computer Society, 978-1-4244-4377-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler |
Fast dynamic power estimation considering glitch filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings, pp. 361-364, 2009, IEEE, 978-1-4244-4940-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Asier Goikoetxea Yanci, Stephen Pickles, Tughrul Arslan |
Characterization of a Voltage Glitch Attack Detector for Secure Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BLISS ![In: 2009 Symposium on Bio-inspired Learning and Intelligent Systems for Security, BLISS 2009, Edingburgh, United Kingdom, August 20-21 2009, pp. 91-96, 2009, IEEE Computer Society, 978-0-7695-3754-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Adrian Stoica, Srinivas Katkoori |
"Glitch Logic" and Applications to Computing and Information Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BLISS ![In: 2009 Symposium on Bio-inspired Learning and Intelligent Systems for Security, BLISS 2009, Edingburgh, United Kingdom, August 20-21 2009, pp. 107-112, 2009, IEEE Computer Society, 978-0-7695-3754-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
anti-tamper, trusted design, protection to reverse engineering, information exfiltration, stego-design, hardware vulnerabilities |
20 | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1521-1534, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng |
Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 2(6), pp. 445-460, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Vishal Midha |
The Glitch in On-line Advertising: A Study of Click Fraud in Pay-Per-Click Advertising Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Electron. Commer. ![In: Int. J. Electron. Commer. 13(2), pp. 91-112, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Kwan-Houng Lee, Jin-Gu Kang, Nam-Seo Park, Choong-Mo Yun, Jae-Jin Kim |
A Low Power Communication Circuit Design Using Selective Glitch Removal Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FGCN (2) ![In: The Second International Conference on Future Generation Communication and Networking, FGCN 2008, Volume 2, Workshops, Hainan Island, China, December 13-15, 2008, pp. 51-56, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Gu-Yeon Wei, David M. Brooks, Ali Durlov Khan, Xiaoyao Liang |
Instruction-driven clock scheduling with glitch mitigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 357-362, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith |
Glitch-aware output switching activity from word-level statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1792-1795, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Asier Goikoetxea Yanci, Stephen Pickles, Tughrul Arslan |
Detecting Voltage Glitch Attacks on Secure Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BLISS ![In: 2008 ECSIS Symposium on Bio-inspired, Learning, and Intelligent Systems for Security, BLISS 2008, Edinburgh, UK, 4-6 August 2008, pp. 75-80, 2008, IEEE Computer Society, 978-0-7695-3265-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
GlitchLess: an active glitch minimization technique for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 156-165, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, power minimization |
20 | Youse Kim, Naeun Zang, Juho Kim |
Stochastic glitch elimination considering path correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2007 IEEE International SOC Conference, Tampere, Finland, November 19-21, 2007, pp. 169-172, 2007, IEEE, 978-1-4244-1592-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Michael N. Skoufis, Haibo Wang 0005, Themistoklis Haniotakis, Spyros Tragoudas |
Glitch Control with Dynamic Receiver Threshold Adjustment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 410-415, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Yuanlin Lu, Vishwani D. Agrawal |
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 2(3), pp. 378-387, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin I. Karsilayan |
Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 53-II(9), pp. 843-847, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides |
Modeling of glitch effects in FPGA based arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006, pp. 349-352, 2006, IEEE, 0-7803-9728-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Hosun Shin, Naeun Zang, Juho Kim |
Stochastic Glitch Estimation and Path Balancing for Statistical Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006, pp. 85-88, 2006, IEEE, 0-7803-9781-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Krister Landernäs, Johnny Holmberg, Mark Vesterbacka |
Glitch reduction in digit-serial recursive filters using retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 12th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2005, Gammarth, Tunisia, December 11-14, 2005, pp. 1-4, 2005, IEEE, 978-9972-61-100-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Huayi Zhang, Ezz I. El-Masry |
A novel CMOS power efficient and glitch free d-flip-flop for dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits, Signals, and Systems ![In: Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005, pp. 1-4, 2005, IASTED/ACTA Press, 0-88986-509-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
20 | Henrik Eriksson, Per Larsson-Edefors |
Glitch-conscious low-power design of arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 281-284, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
20 | Sungjae Kim, Hyungwoo Lee, Juho Kim |
Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(1), pp. 234-240, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
20 | Ki-Seok Chung, Taewhan Kim, C. L. Liu 0001 |
A Complete Model for Glitch Analysis in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 11(2), pp. 137-154, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Ki-Seok Chung, Taewhan Kim, C. L. Liu 0001 |
G-vector: A New Model for Glitch Analysis in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(3), pp. 235-251, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
synthesis, power estimation, logic circuits, glitches |
20 | Henrik Eriksson, Per Larsson-Edefors |
Impact of Voltage Scaling on Glitch Power Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 139-148, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Mikael Karlsson Rudberg, Mark Vesterbacka, Niklas U. Andersson, J. Jacob Wikner |
Glitch minimization and dynamic element matching in D/A converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000, pp. 899-902, 2000, IEEE, 0-7803-6542-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Pasin Israsena, Steve Summerfield |
Novel pattern-based power estimation tool with accurate glitch modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 721-724, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Nihar R. Mahapatra, Sriram V. Garimella, Alwin Takeen |
Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 537-540, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register transfer level power optimization with emphasis on glitch analysis and reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8), pp. 1114-1131, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 446-451, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Anne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas, Augusto Manuel Marques, José Bastos, Michiel Steyaert, Georges G. E. Gielen, Willy Sansen |
A 12 bit 200 MHz low glitch CMOS D/A converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998, pp. 249-252, 1998, IEEE, 0-7803-4292-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
20 | Bruce J. Tesch, Juan C. Garcia |
A low glitch 14-b 100-MHz D/A converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(9), pp. 1465-1469, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
20 | Dirk Rabe, Wolfgang Nebel |
New approach in gate-level glitch modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 66-71, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Glitch Analysis and Reduction in Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 331-336, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Tien-Yu Wu, Ching-Tsing Jih, Jueh-Chi Chen, Chung-Yu Wu |
A low glitch 10-bit 75-MHz CMOS video D/A converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(1), pp. 68-72, January 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
20 | Michele Favalli, Luca Benini |
Analysis of glitch power dissipation in CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPD ![In: Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995, pp. 123-128, 1995, ACM, 0-89791-744-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
20 | Qiuting Huang, Robert Rogenmoser |
A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 11-14, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
20 | James H. Anderson, Mohamed G. Gouda |
A New Explanation of the Glitch Phenomenon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Acta Informatica ![In: Acta Informatica 28(4), pp. 297-309, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
20 | Stephen D. Crocker |
Output of the Host-Host Protocol glitch cleaning committee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RFC ![In: RFC 102, pp. 1-4, February 1971. The full citation details ...](Pics/full.jpeg) |
1971 |
DBLP DOI BibTeX RDF |
|
20 | Robert D. Bressler, Stephen D. Crocker, William R. Crowther, Gary R. Grossman, Raymond S. Tomlinson, James E. White |
Output of the Host-Host Protocol Glitch Cleaning Committee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RFC ![In: RFC 107, pp. 1-12, March 1971. The full citation details ...](Pics/full.jpeg) |
1971 |
DBLP DOI BibTeX RDF |
|
14 | Rupesh S. Shelar, Marek Patyra |
Impact of local interconnects on timing and power in a high performance microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 145-152, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CAD, delay, interconnects, power, microprocessor |
14 | Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
Effective BIST for crosstalk faults in interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 164-169, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Zhimin Chen 0002, Syed Haider, Patrick Schaumont |
Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISA ![In: Advances in Information Security and Assurance, Third International Conference and Workshops, ISA 2009, Seoul, Korea, June 25-27, 2009. Proceedings, pp. 327-336, 2009, Springer, 978-3-642-02616-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 830-836, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Charu Nagpal, Rajesh Garg, Sunil P. Khatri |
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 354-359, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Denis Réal, Cécile Canovas, Jessy Clédière, M'hamed Drissi, Frédéric Valette |
Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1274-1279, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Hung Tien Bui |
Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3422-3425, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Santanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee |
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 149-152, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Chanyang Joo, Soojae Kim, Kwangsub Yoon |
A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 219-222, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
binary decoder, pseudo-segmentation, swing reduced driver, low power, DAC |
14 | Qian Ding, Yu Wang 0002, Hui Wang 0004, Rong Luo, Huazhong Yang |
Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 74-77, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Rajesh Garg, Charu Nagpal, Sunil P. Khatri |
A fast, analytical estimator for the SEU-induced pulse width in combinational designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 918-923, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
single event upset (SEU), model, analysis |
14 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 |
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 534-539, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo |
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1265-1270, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Chong Hee Kim, Jean-Jacques Quisquater |
Fault Attacks for CRT Based RSA: New Attacks, New Results, and New Countermeasures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISTP ![In: Information Security Theory and Practices. Smart Cards, Mobile and Ubiquitous Computing Systems, First IFIP TC6 / WG 8.8 / WG 11.2 International Workshop, WISTP 2007, Heraklion, Crete, Greece, May 9-11, 2007, Proceedings, pp. 215-228, 2007, Springer, 978-3-540-72353-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria |
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 633-636, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Zhenglin Liu, Xu Guo, Yi-Cheng Chen, Yu Han, Xuecheng Zou |
On the Ability of AES S-Boxes to Secure Against Correlation Power Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPEC ![In: Information Security Practice and Experience, Third International Conference, ISPEC 2007, Hong Kong, China, May 7-9, 2007, Proceedings, pp. 43-50, 2007, Springer, 978-3-540-72159-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
correlation power analysis (CPA), Advanced Encryption Standard (AES), hamming distance, correlation coefficient |
14 | Mustafa Parlak, Ilker Hamzaoglu |
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 127-133, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi |
Error Tolerance of DNA Self-Healing Assemblies by Puncturing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 400-408, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Natasa Miskov-Zivanov, Diana Marculescu |
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 893-898, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Natasa Miskov-Zivanov, Diana Marculescu |
Circuit Reliability Analysis Using Symbolic Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2638-2649, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Jan Camenisch, Susan Hohenberger, Markulf Kohlweiss, Anna Lysyanskaya, Mira Meyerovich |
How to win the clonewars: efficient periodic n-times anonymous authentication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 13th ACM Conference on Computer and Communications Security, CCS 2006, Alexandria, VA, USA, October 30 - November 3, 2006, pp. 201-210, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
n-anonymous authentication, credentials, clone detection |
14 | Michele Boreale |
Attacking Right-to-Left Modular Exponentiation with Timely Random Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: Fault Diagnosis and Tolerance in Cryptography, Third International Workshop, FDTC 2006, Yokohama, Japan, October 10, 2006, Proceedings, pp. 24-35, 2006, Springer, 3-540-46250-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault-based cryptanalysis, public-key cryptosystems, smartcards |
14 | Tzyy-Kuen Tien, Jing-Jou Tang, Kuan-Jou Chen |
A new high speed dynamic PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Adit D. Singh, Gefu Xu |
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 349-357, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Hazard-Free, Test, Delay, Transition |
14 | Gaurav Raja, Basabi Bhaumik |
16-Bit Segmented Type Current Steering DAC for Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 63-68, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Digital-to-Analog Conversion, Segmentation, Matching |
14 | Jiajia Chen 0002, Chip-Hong Chang, A. Prasad Vinod 0001 |
Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 756-759, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Natasa Miskov-Zivanov, Diana Marculescu |
MARS-C: modeling and reduction of soft errors in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 767-772, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reliability symbolic techniques, SER |
14 | Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra |
A novel high-speed sense-amplifier-based flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1266-1274, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Jean-Pierre Seifert |
On authenticated computing and RSA-based authentication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 12th ACM Conference on Computer and Communications Security, CCS 2005, Alexandria, VA, USA, November 7-11, 2005, pp. 122-127, 2005, ACM, 1-59593-226-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
authenticated computing, RSA, fault attacks, secure boot |
14 | Cristiano Forzan, Davide Pandini |
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 982-983, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun |
Design of A 2.4-GHz integrated frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 21-22, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel |
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 22-27, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity |
14 | Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen |
Pipelining technique for energy-aware datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1218-1221, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo |
A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2429-2432, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|