Search results for "glitch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Amir Moradi 0001, Oliver Mischke	On the Simplicity of Converting Leakages from Multivariate to Univariate - Case Study of a Glitch-Resistant Masking Scheme -	IACR Cryptol. ePrint Arch.	2012	DBLP BibTeX RDF
20	Jing Jin 0005, Xiaoming Liu 0008, Tingting Mo, Jianjun Zhou	Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
20	Amir Fathi, Sarkis Azizian, Rahim Fathi, Habib Ghasemizadeh Tamar	Low latency, glitch-free booth encoder-decoder for high speed multipliers.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
20	Dai Yamamoto, Gabriel Hospodar, Roel Maes, Ingrid Verbauwhede	Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs.	SPACE	2012	DBLP DOI BibTeX RDF
20	Mariem Slimani, Philippe Matherat, Yves Mathieu	A dual threshold voltage technique for glitch minimization.	ICECS	2012	DBLP DOI BibTeX RDF
20	Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria	Identification of soft error glitch-propagation paths: Leveraging SAT solvers.	ISCAS	2012	DBLP DOI BibTeX RDF
20	Amir Moradi 0001, Oliver Mischke	Glitch-free implementation of masking in modern FPGAs.	HOST	2012	DBLP DOI BibTeX RDF
20	Hongying Liu, Guoyu Qian, Yukiyasu Tsunoo, Satoshi Goto	The Switching Glitch Power Leakage Model.	J. Softw.	2011	DBLP DOI BibTeX RDF
20	Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin	Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA.	J. Cryptol.	2011	DBLP DOI BibTeX RDF
20	Will Tracz	Glitch: the hidden impact of faulty software by Jeff Papows.	ACM SIGSOFT Softw. Eng. Notes	2011	DBLP DOI BibTeX RDF
20	Kesava R. Talupuru, Sanjai Athi	Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking.	MTV	2011	DBLP DOI BibTeX RDF
20	Laure Berti-Équille, Tamraparni Dasu, Divesh Srivastava	Discovery of complex glitch patterns: A novel approach to Quantitative Data Cleaning.	ICDE	2011	DBLP DOI BibTeX RDF
20	Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria	SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.	ICECS	2011	DBLP DOI BibTeX RDF
20	Warren Wai-Kit Shum, Jason Helge Anderson	FPGA glitch power analysis and reduction.	ISLPED	2011	DBLP BibTeX RDF
20	Xiaoming Liu 0008, Jing Jin 0005, Xi Li, Jianjun Zhou	Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs.	ISCAS	2011	DBLP DOI BibTeX RDF
20	Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz	A gate sizing method for glitch power reduction.	SoCC	2011	DBLP DOI BibTeX RDF
20	Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita	AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.	EURASIP J. Embed. Syst.	2010	DBLP DOI BibTeX RDF
20	Meng-Hung Shen, Jen-Huan Tsai, Po-Chiun Huang	Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
20	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
20	Amit Mondal, Ross Cutler, Cheng Huang 0002, Jin Li 0001, Aleksandar Kuzmanovic	SureCall: Towards glitch-free real-time audio/video conferencing.	IWQoS	2010	DBLP DOI BibTeX RDF
20	Dina Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, David Bol	Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits.	ESSCIRC	2010	DBLP DOI BibTeX RDF
20	Hongying Liu, Guoyu Qian, Satoshi Goto, Yukiyasu Tsunoo	Correlation Power Analysis Based on Switching Glitch Model.	WISA	2010	DBLP DOI BibTeX RDF
20	William John Bainbridge, Sean James Salisbury	Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links.	ASYNC	2009	DBLP DOI BibTeX RDF
20	Betsy James DiSalvo, Mark Guzdial, Tom McKlin, Charles Meadows, Kenneth Perry, Corey Steward, Amy S. Bruckman	Glitch Game Testers: African American Men Breaking Open the Console.	DiGRA Conference	2009	DBLP BibTeX RDF
20	Marco Zanuso, Salvatore Levantino, Davide Tasca, Daniele Raiteri, Carlo Samori, Andrea L. Lacaita	A glitch-corrector circuit for low-spur ADPLLs.	ICECS	2009	DBLP DOI BibTeX RDF
20	Ali Kiaei, Mounir Bohsali, Ahmad Bahai, Thomas H. Lee	A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector.	ESSCIRC	2009	DBLP DOI BibTeX RDF
20	Xiao Dong, Guy G. F. Lemieux	PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess.	FPT	2009	DBLP DOI BibTeX RDF
20	Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler	Fast dynamic power estimation considering glitch filtering.	SoCC	2009	DBLP DOI BibTeX RDF
20	Asier Goikoetxea Yanci, Stephen Pickles, Tughrul Arslan	Characterization of a Voltage Glitch Attack Detector for Secure Devices.	BLISS	2009	DBLP DOI BibTeX RDF
20	Adrian Stoica, Srinivas Katkoori	"Glitch Logic" and Applications to Computing and Information Security.	BLISS	2009	DBLP DOI BibTeX RDF	anti-tamper, trusted design, protection to reverse engineering, information exfiltration, stego-design, hardware vulnerabilities
20	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
20	Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng	Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols.	IET Comput. Digit. Tech.	2008	DBLP DOI BibTeX RDF
20	Vishal Midha	The Glitch in On-line Advertising: A Study of Click Fraud in Pay-Per-Click Advertising Programs.	Int. J. Electron. Commer.	2008	DBLP DOI BibTeX RDF
20	Kwan-Houng Lee, Jin-Gu Kang, Nam-Seo Park, Choong-Mo Yun, Jae-Jin Kim	A Low Power Communication Circuit Design Using Selective Glitch Removal Method.	FGCN (2)	2008	DBLP DOI BibTeX RDF
20	Gu-Yeon Wei, David M. Brooks, Ali Durlov Khan, Xiaoyao Liang	Instruction-driven clock scheduling with glitch mitigation.	ISLPED	2008	DBLP DOI BibTeX RDF
20	Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith	Glitch-aware output switching activity from word-level statistics.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Asier Goikoetxea Yanci, Stephen Pickles, Tughrul Arslan	Detecting Voltage Glitch Attacks on Secure Devices.	BLISS	2008	DBLP DOI BibTeX RDF
20	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: an active glitch minimization technique for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, power minimization
20	Youse Kim, Naeun Zang, Juho Kim	Stochastic glitch elimination considering path correlation.	SoCC	2007	DBLP DOI BibTeX RDF
20	Michael N. Skoufis, Haibo Wang 0005, Themistoklis Haniotakis, Spyros Tragoudas	Glitch Control with Dynamic Receiver Threshold Adjustment.	ISQED	2007	DBLP DOI BibTeX RDF
20	Yuanlin Lu, Vishwani D. Agrawal	CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
20	Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin I. Karsilayan	Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
20	Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides	Modeling of glitch effects in FPGA based arithmetic circuits.	FPT	2006	DBLP DOI BibTeX RDF
20	Hosun Shin, Naeun Zang, Juho Kim	Stochastic Glitch Estimation and Path Balancing for Statistical Optimization.	SoCC	2006	DBLP DOI BibTeX RDF
20	Krister Landernäs, Johnny Holmberg, Mark Vesterbacka	Glitch reduction in digit-serial recursive filters using retiming.	ICECS	2005	DBLP DOI BibTeX RDF
20	Huayi Zhang, Ezz I. El-Masry	A novel CMOS power efficient and glitch free d-flip-flop for dual-modulus prescaler.	Circuits, Signals, and Systems	2005	DBLP BibTeX RDF
20	Henrik Eriksson, Per Larsson-Edefors	Glitch-conscious low-power design of arithmetic circuits.	ISCAS (2)	2004	DBLP BibTeX RDF
20	Sungjae Kim, Hyungwoo Lee, Juho Kim	Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
20	Ki-Seok Chung, Taewhan Kim, C. L. Liu 0001	A Complete Model for Glitch Analysis in Logic Circuits.	J. Circuits Syst. Comput.	2002	DBLP DOI BibTeX RDF
20	Ki-Seok Chung, Taewhan Kim, C. L. Liu 0001	G-vector: A New Model for Glitch Analysis in Logic Circuits.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	synthesis, power estimation, logic circuits, glitches
20	Henrik Eriksson, Per Larsson-Edefors	Impact of Voltage Scaling on Glitch Power Consumption.	PATMOS	2000	DBLP DOI BibTeX RDF
20	Mikael Karlsson Rudberg, Mark Vesterbacka, Niklas U. Andersson, J. Jacob Wikner	Glitch minimization and dynamic element matching in D/A converters.	ICECS	2000	DBLP DOI BibTeX RDF
20	Pasin Israsena, Steve Summerfield	Novel pattern-based power estimation tool with accurate glitch modeling.	ISCAS	2000	DBLP DOI BibTeX RDF
20	Nihar R. Mahapatra, Sriram V. Garimella, Alwin Takeen	Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation.	ISCAS	2000	DBLP DOI BibTeX RDF
20	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register transfer level power optimization with emphasis on glitch analysis and reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
20	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.	DAC	1999	DBLP DOI BibTeX RDF
20	Anne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas, Augusto Manuel Marques, José Bastos, Michiel Steyaert, Georges G. E. Gielen, Willy Sansen	A 12 bit 200 MHz low glitch CMOS D/A converter.	CICC	1998	DBLP DOI BibTeX RDF
20	Bruce J. Tesch, Juan C. Garcia	A low glitch 14-b 100-MHz D/A converter.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
20	Dirk Rabe, Wolfgang Nebel	New approach in gate-level glitch modelling.	EURO-DAC	1996	DBLP DOI BibTeX RDF
20	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Glitch Analysis and Reduction in Register Transfer Level.	DAC	1996	DBLP DOI BibTeX RDF
20	Tien-Yu Wu, Ching-Tsing Jih, Jueh-Chi Chen, Chung-Yu Wu	A low glitch 10-bit 75-MHz CMOS video D/A converter.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
20	Michele Favalli, Luca Benini	Analysis of glitch power dissipation in CMOS ICs.	ISLPD	1995	DBLP DOI BibTeX RDF
20	Qiuting Huang, Robert Rogenmoser	A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications.	ISCAS	1994	DBLP DOI BibTeX RDF
20	James H. Anderson, Mohamed G. Gouda	A New Explanation of the Glitch Phenomenon.	Acta Informatica	1991	DBLP DOI BibTeX RDF
20	Stephen D. Crocker	Output of the Host-Host Protocol glitch cleaning committee.	RFC	1971	DBLP DOI BibTeX RDF
20	Robert D. Bressler, Stephen D. Crocker, William R. Crowther, Gary R. Grossman, Raymond S. Tomlinson, James E. White	Output of the Host-Host Protocol Glitch Cleaning Committee.	RFC	1971	DBLP DOI BibTeX RDF
14	Rupesh S. Shelar, Marek Patyra	Impact of local interconnects on timing and power in a high performance microprocessor.	ISPD	2010	DBLP DOI BibTeX RDF	CAD, delay, interconnects, power, microprocessor
14	Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	Effective BIST for crosstalk faults in interconnects.	DDECS	2009	DBLP DOI BibTeX RDF
14	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
14	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Charu Nagpal, Rajesh Garg, Sunil P. Khatri	A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.	DATE	2008	DBLP DOI BibTeX RDF
14	Denis Réal, Cécile Canovas, Jessy Clédière, M'hamed Drissi, Frédéric Valette	Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis.	DATE	2008	DBLP DOI BibTeX RDF
14	Hung Tien Bui	Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Santanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee	An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Chanyang Joo, Soojae Kim, Kwangsub Yoon	A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	binary decoder, pseudo-segmentation, swing reduced driver, low power, DAC
14	Qian Ding, Yu Wang 0002, Hui Wang 0004, Rong Luo, Huazhong Yang	Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.	ISQED	2008	DBLP DOI BibTeX RDF
14	Rajesh Garg, Charu Nagpal, Sunil P. Khatri	A fast, analytical estimator for the SEU-induced pulse width in combinational designs.	DAC	2008	DBLP DOI BibTeX RDF	single event upset (SEU), model, analysis
14	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.	DATE	2007	DBLP DOI BibTeX RDF
14	Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo	Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware.	DATE	2007	DBLP DOI BibTeX RDF
14	Chong Hee Kim, Jean-Jacques Quisquater	Fault Attacks for CRT Based RSA: New Attacks, New Results, and New Countermeasures.	WISTP	2007	DBLP DOI BibTeX RDF
14	Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria	A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Zhenglin Liu, Xu Guo, Yi-Cheng Chen, Yu Han, Xuecheng Zou	On the Ability of AES S-Boxes to Secure Against Correlation Power Analysis.	ISPEC	2007	DBLP DOI BibTeX RDF	correlation power analysis (CPA), Advanced Encryption Standard (AES), hamming distance, correlation coefficient
14	Mustafa Parlak, Ilker Hamzaoglu	A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm.	AHS	2007	DBLP DOI BibTeX RDF
14	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	Error Tolerance of DNA Self-Healing Assemblies by Puncturing.	DFT	2007	DBLP DOI BibTeX RDF
14	Natasa Miskov-Zivanov, Diana Marculescu	MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
14	Natasa Miskov-Zivanov, Diana Marculescu	Circuit Reliability Analysis Using Symbolic Techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Jan Camenisch, Susan Hohenberger, Markulf Kohlweiss, Anna Lysyanskaya, Mira Meyerovich	How to win the clonewars: efficient periodic n-times anonymous authentication.	CCS	2006	DBLP DOI BibTeX RDF	n-anonymous authentication, credentials, clone detection
14	Michele Boreale	Attacking Right-to-Left Modular Exponentiation with Timely Random Faults.	FDTC	2006	DBLP DOI BibTeX RDF	fault-based cryptanalysis, public-key cryptosystems, smartcards
14	Tzyy-Kuen Tien, Jing-Jou Tang, Kuan-Jou Chen	A new high speed dynamic PLA.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Adit D. Singh, Gefu Xu	Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing.	VTS	2006	DBLP DOI BibTeX RDF	Hazard-Free, Test, Delay, Transition
14	Gaurav Raja, Basabi Bhaumik	16-Bit Segmented Type Current Steering DAC for Video Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF	Digital-to-Analog Conversion, Segmentation, Matching
14	Jiajia Chen 0002, Chip-Hong Chang, A. Prasad Vinod 0001	Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Natasa Miskov-Zivanov, Diana Marculescu	MARS-C: modeling and reduction of soft errors in combinational circuits.	DAC	2006	DBLP DOI BibTeX RDF	reliability symbolic techniques, SER
14	Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra	A novel high-speed sense-amplifier-based flip-flop.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
14	Jean-Pierre Seifert	On authenticated computing and RSA-based authentication.	CCS	2005	DBLP DOI BibTeX RDF	authenticated computing, RSA, fault attacks, secure boot
14	Cristiano Forzan, Davide Pandini	Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis.	DATE	2005	DBLP DOI BibTeX RDF
14	Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun	Design of A 2.4-GHz integrated frequency synthesizer.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity
14	Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen	Pipelining technique for energy-aware datapaths.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
14	Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo	A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration.	ISCAS (3)	2005	DBLP DOI BibTeX RDF