|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1997 occurrences of 975 keywords
|
|
|
Results
Found 1754 publication records. Showing 1754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Improved spill code generation for software pipelined loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2000 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Vancouver, Britith Columbia, Canada, June 18-21, 2000, pp. 134-144, 2000, ACM, 1-58113-199-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, register allocation, software pipelining, spill code |
28 | Johann Großschädl |
High-Speed RSA Hardware Based on Barret's Modular Reduction Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop, Worcester, MA, USA, August 17-18, 2000, Proceedings, pp. 191-203, 2000, Springer, 3-540-41455-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA algorithm, partial parallel multiplier, full-custom VLSI design, pipelining, Public-key cryptography, modular arithmetic |
28 | Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon |
Bounding Pipeline and Instruction Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(1), pp. 53-70, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache |
28 | Kei-Yong Khoo, Alan N. Willson Jr. |
Single-transistor transparent-latch clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 331-341, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits |
28 | Luca Breveglieri, Luigi Dadda, Vincenzo Piuri |
Column Compression Pipelined Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 93-103, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pipelining, computer arithmetic, multipliers |
28 | Toshio Nakatani, Kemal Ebcioglu |
Making Compaction-Based Parallelization Affordable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(9), pp. 1014-1029, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc |
28 | Klaus D. Thalhofer, Karl D. Reinartz |
A Classification of Algorithms which Are Well Suited for Implementations on the DAP as a Basis for Further Research on Parallel Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 86: Conference on Algorithms and Hardware for Parallel Processing, Aachen, Germany, September 17-19, 1986, Proceedings, pp. 376-384, 1986, Springer, 3-540-16811-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
SIMD-principle, algorithm patterns, recursive doubling, binary decomposition, large scale pipelining, routing, Parallel programming, preprocessors |
25 | Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek |
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 310-315, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping |
25 | SangMin Shim, Soo-Mook Moon |
Split-path Enhanced Pipeline Scheduling for Loops with Control Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998, pp. 93-102, 1998, ACM/IEEE Computer Society, 0-8186-8609-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
all-path pipelining, enhanced pipeline scheduling, initiation interval, multi-path loops, software pipelining, modulo scheduling |
25 | David Bernstein, Haran Boral, Ron Y. Pinter |
Optimal Chaining in Expression Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(11), pp. 1366-1374, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
optimal chaining, vector instructions pipelining, explicit pipelining, expression trees, linear time scheduling algorithm, scheduling, computational complexity, parallel programming, dynamic programming, pipeline processing, automatic programming, automatic code generation, complexity analysis, Cray-1, dynamic programming algorithms |
23 | Jialu Huang, Arun Raman, Thomas B. Jablin, Yun Zhang 0005, Tzu-Han Hung, David I. August |
Decoupled software pipelining creates parallelization opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 121-130, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
DSWP, enabling transformation, parallelization, multicore, speculation |
23 | Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon |
Pipelining Saturated Accumulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(2), pp. 208-219, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor P. Stefanov |
Flexible pipelining design for recursive variable expansion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng |
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 594-598, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh |
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), pp. 409-422, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Mark Muir, Tughrul Arslan, Iain Lindsay |
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1358-1361, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Zhikun Wang, Dan Feng 0001, Ke Zhou 0001, Fang Wang 0001 |
PCOW: Pipelining-Based COW Snapshot Method to Decrease First Write Penalty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPC ![In: Advances in Grid and Pervasive Computing, Third International Conference, GPC 2008, Kunming, China, May 25-28, 2008. Proceedings, pp. 266-274, 2008, Springer, 978-3-540-68081-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Yoonjin Kim, Rabi N. Mahapatra |
Reusable context pipelining for low power coarse-grained reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba |
Clustered Decoupled Software Pipelining on Commodity CMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 681-688, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August |
Speculative Decoupled Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 49-59, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Nan Wang, Azeez Sanusi, Peiyi Zhao, Shaheen Mohamed, Magdy A. Bayoumi |
PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 487-492, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Yoshiyuki Yamashita, Masato Tsuru |
Software Pipelining for Packet Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, Third International Conference, HPCC 2007, Houston, USA, September 26-28, 2007, Proceedings, pp. 446-459, 2007, Springer, 978-3-540-75443-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ricardo Menotti, Eduardo Marques, João M. P. Cardoso |
Aggressive Loop Pipelining for Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 501-502, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Yong Dou, Jinhui Xu 0002, Guiming Wu |
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 155-166, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(1), pp. 18-33, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cache-miss tolerance, prefetching, out-of-order execution, Runahead execution |
23 | Mario R. Casu, Luca Macchiarulo |
Floorplanning With Wire Pipelining in Adaptive Communication Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2996-3004, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala |
Software Pipelining Support for Transport Triggered Architecture Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 237-247, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen |
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, ICME 2006, July 9-12 2006, Toronto, Ontario, Canada, pp. 281-284, 2006, IEEE Computer Society, 1-4244-0367-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Timothy M. McPhillips, Shawn Bowers |
An approach for pipelining nested collections in scientific workflows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Rec. ![In: SIGMOD Rec. 34(3), pp. 12-17, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Lin Qiao, Weitong Huang, Zhizhong Tang |
A Dynamic Data Dependence Analysis Approach for Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings, pp. 221-228, 2005, Springer, 3-540-29810-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August |
Automatic Thread Extraction with Decoupled Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 105-118, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Yanjun Zhang, Hu He 0001, Yihe Sun |
A new register file access architecture for software pipelining in VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 627-630, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | T. S. B. Sudarshan, Rahil Mir, S. Vijayalakshmi |
DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 625-639, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Blowfish, inner loop pipeline, loop folding, four - tier architecture, Platform independent architecture, DRIL Architecture, replication, Dynamic reconfiguration |
23 | Laura Pozzi, Paolo Ienne |
Exploiting pipelining to relax register-file port constraints of instruction-set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 2-10, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
automatic instruction-set extension, constrained scheduling, embedded customised architectures, multi-cycle register access, input/output |
23 | Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska |
Pipelining Sequential Circuits with Wave Steering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(9), pp. 1205-1210, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August |
Decoupled Software Pipelining with the Synchronization Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, pp. 177-188, 2004, IEEE Computer Society, 0-7695-2229-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | François-Xavier Standaert, Siddika Berna Örs, Bart Preneel |
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 30-44, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating in-order stalls with "flea-flicker" two-pass pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 387-398, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo |
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 292-302, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Yiqun Zhu, Mohammed Benaissa |
Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 360-368, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Darin Petkov, Randolph E. Harr, Saman P. Amarasinghe |
Efficient Pipelining of Nested Loops: Unroll-and-Squash. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Elsie Nallipogu, Füsun Özgüner, Mario Lauria |
Improving the Throughput of Remote Storage Access through Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GRID ![In: Grid Computing - GRID 2002, Third International Workshop, Baltimore, MD, USA, November 18, 2002, Proceedings, pp. 305-316, 2002, Springer, 3-540-00133-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Oswaldo Cadenas, Graham M. Megson |
Pipelining Considerations for an FPGA Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 276-285, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | David Gregg |
Global Software Pipelining with Iteration Preselection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 9th International Conference, CC 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 189-201, 2000, Springer, 3-540-67263-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Smita Bakshi, Daniel D. Gajski |
Partitioning and pipelining for performance-constrained hardware/software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 419-432, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Wei-Kai Cheng, Youn-Long Lin |
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(3), pp. 231-256, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
code generation, DSP |
23 | Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya |
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 262-273, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit |
23 | Vinoo Srinivasan, Ranga Vemuri |
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 435-441, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha |
Rotation scheduling: a loop pipelining algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3), pp. 229-239, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Erik R. Altman, Guang R. Gao |
Optimal Software Pipelining Through Enumeration of Schedules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 833-840, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Steve Carr 0001, Chen Ding, Philip H. Sweany |
Improving Software Pipelining with Unroll-and-Jam. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 29th Annual Hawaii International Conference on System Sciences (HICSS-29), January 3-6, 1996, Maui, Hawaii, USA, pp. 183-192, 1996, IEEE Computer Society, 0-8186-7324-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata |
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 165-, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao |
Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI), La Jolla, California, USA, June 18-21, 1995, pp. 139-150, 1995, ACM, 0-89791-697-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
Minimizing register requirements under resource-constrained rate-optimal software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 85-94, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Donald A. Joy, Maciej J. Ciesielski |
Clock period minimization with wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 461-472, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
23 | Evelyn Duesterwald, Rajiv Gupta 0001, Mary Lou Soffa |
Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 4th International Conference on Compiler Construction, CC'92, Paderborn, Germany, October 5-7, 1992, Proceedings, pp. 192-206, 1992, Springer, 3-540-55984-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Jan Hoogerbrugge, Henk Corporaal |
Comparing Software Pipelining for an Operation-Triggered and a Tarnsport-Triggered Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 4th International Conference on Compiler Construction, CC'92, Paderborn, Germany, October 5-7, 1992, Proceedings, pp. 219-228, 1992, Springer, 3-540-55984-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Jean Duprat, Mario Fiallos Aguilar |
On the Simulation of Pipelining of Fully Digit On-Line Floating-Point Adder Networks on Massively Parallel Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 92 - VAPP V, Second Joint International Conference on Vector and Parallel Processing, Lyon, France, September 1-4, 1992, Proceedings, pp. 707-712, 1992, Springer, 3-540-55895-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Reinhard J. Richter |
A Reconfigurable Interconnection Network for Flexible Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 90 - VAPP IV, Joint International Conference on Vector and Parallel Processing, Zurich, Switzerland, September 10-13, 1990, Proceedings, pp. 397-404, 1990, Springer, 3-540-53065-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | T. E. A. Lees |
Context streams a theoretical basis for a generic form of MIMD pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, SPDP 1990, Dallas, Texas, USA, December 9-13, 1990., pp. 754-757, 1990, IEEE Computer Society, 0-8186-2087-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita |
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 78-85, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
23 | Kemal Ebcioglu |
A compilation technique for software pipelining of loops with conditional jumps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 69-79, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
23 | Douglas W. Clark |
Pipelining and Performance in the VAX 8800 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 173-177, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
VAX |
23 | C. V. Ramamoorthy, K. H. Kim |
Pipelining: the generalized concept and sequencing strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1974 National Computer Conference, 6-10 May 1974, Chicago, Illinois, USA, pp. 289-297, 1974, AFIPS Press, 978-1-4503-7920-5. The full citation details ...](Pics/full.jpeg) |
1974 |
DBLP DOI BibTeX RDF |
|
23 | Chun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, Meikang Qiu |
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1202-1207, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Wei Dong 0002, Peng Li 0001, Xiaoji Ye |
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 238-243, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
parallel computing, multi-core, transient simulation |
23 | Suhyun Kim, Soo-Mook Moon |
Rotating Register Allocation for Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 60-72, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Vinay Sriram, David Kearney |
A FPGA Implementation of Variable Kernel Convolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), 3-6 December 2007, Adelaide, Australia, pp. 105-110, 2007, IEEE Computer Society, 0-7695-3049-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Alireza Hodjat, Ingrid Verbauwhede |
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(4), pp. 366-372, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
crypto-processor, security, VLSI, cryptography, Advanced Encryption Standard (AES), ASIC, hardware architectures |
23 | Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe |
Exploiting Vector Parallelism in Software Pipelined Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 119-129, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija |
Architectural Considerations for Energy Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 13-16, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Vidyasagar Nookala, Sachin S. Sapatnekar |
Designing optimized pipelined global interconnects: algorithms and methodology impact. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 608-611, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Mihai Budiu, Seth Copen Goldstein |
Optimizing Memory Accesses For Spatial Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 216-227, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Loop fusion for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 112-119, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clustered VLIW architectures, loop fusion |
23 | Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura |
Scaling Up Of Wave Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 439-445, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan |
A wave-pipelined router architecture using ternary associative memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 67-70, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt |
Statistical analysis of timing rules for high-speed synchronous VLSI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 477-482, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Eric Stotzer, Ernst L. Leiss |
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Languages, Compilers, and Tools for Embedded Systems ![In: Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'99), Atlanta, Georgia, USA, May 5, 1999, pp. 28-34, 1999, ACM, 1-58113-136-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Sung-Kwan Kim, Sang Lyul Min, Rhan Ha |
Analysis of the Impacts of Overestimation Sources on the Accuracy of Worst Case Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 20th IEEE Real-Time Systems Symposium, Phoenix, AZ, USA, December 1-3, 1999, pp. 22-31, 1999, IEEE Computer Society, 0-7695-0475-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
real-time systems, WCET analysis |
23 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Han-Saem Yun |
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 12th International Workshop, LCPC'99, La Jolla/San Diego, CA, USA, August 4-6, 1999, Proceedings, pp. 85-99, 1999, Springer, 3-540-67858-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | S. Summerfield, Zhongfeng Wang, Keshab K. Parhi |
Area-power-time efficient pipeline-interleaved architectures for wave digital filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 343-346, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Cristina Barrado, Jesús Labarta |
Hamiltonian Recurrence for ILP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 352-355, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Mary Jane Irwin, Robert Michael Owens |
A case for digit serial VLSI signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 1(4), pp. 321-334, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | François Bodin, François Charot |
Loop optimization for horizontal microcoded machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990, pp. 164-176, 1990, ACM, 0-89791-369-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Krishna P. Mikkilineni, Stanley Y. W. Su |
An Evaluation of Relational Join Algorithms in a Pipelined Query Processing Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 14(6), pp. 838-848, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
timing equations, relational join algorithms, pipelined query processing environment, nested block, sort-merge, pipelined sort-merge, performance evaluation, relational databases, relational databases, distributed processing, distributed databases, distributed databases, sorting, database theory, hash, pipeline processing, merging, query execution |
23 | Chung-Ta King, Wen-Hwa Chou, Lionel M. Ni |
Pipelined data parallel algorithms - concept and modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 2nd international conference on Supercomputing, ICS 1988, Saint Malo, France, July 4-8, 1988, pp. 385-395, 1988, ACM, 0-89791-272-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
23 | Shlomo Weiss, James E. Smith 0001 |
A Study of Scalar Compilation Techniques for Pipelined Supercomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 105-109, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
20 | Eddy Z. Zhang, Yunlian Jiang, Ziyu Guo, Xipeng Shen |
Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 115-126, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CPU-GPU pipelining, thread divergence, thread-data remapping, GPGPU, data transformation |
20 | Maxwell Walton, Gary Gréwal, Gerarda A. Darlington |
Parallel FPGA-based implementation of scatter search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2010, Proceedings, Portland, Oregon, USA, July 7-11, 2010, pp. 1075-1082, 2010, ACM, 978-1-4503-0072-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
0-1 knapsack problem, field programmable gate arrays, pipelining, hardware acceleration, data parallelism, scatter search |
20 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 99-108, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
20 | Roger F. Woods, John V. McCanny, John G. McWhirter |
From Bit Level Systolic Arrays to HDTV Processor Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 35-49, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SoC architectures, DSP systems, pipelining, systolic arrays |
20 | Hongbo Rong, Alban Douillet, Guang R. Gao |
Register allocation for software pipelined multidimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 30(4), pp. 23:1-23:68, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register allocation, Software pipelining |
20 | Abhishek Das, William J. Dally |
Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2008 - Parallel Processing, 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings, pp. 337-349, 2008, Springer, 978-3-540-85450-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Stream Scheduling, Bulk Operations, Sequoia, GSOP Memory Hierarchy, Tunables, Software Pipelining |
20 | Suhyun Kim, Soo-Mook Moon |
Rotating register allocation with multiple rotating branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 235-244, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
rotating register, register allocation, software pipelining |
20 | Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee |
Enabling compiler flow for embedded VLIW DSP processors with distributed register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 146-148, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
distributed register files, embedded VLIW DSP compilers, software pipelining |
20 | Klaus Schöffmann, Markus Fauster, Oliver Lampl, László Böszörményi |
An Evaluation of Parallelization Concepts for Baseline-Profile Compliant H.264/AVC Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2007, Parallel Processing, 13th International Euro-Par Conference, Rennes, France, August 28-31, 2007, Proceedings, pp. 782-791, 2007, Springer, 978-3-540-74465-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Evaluation, Parallelization, Pipelining, H.264, Decoding, Multi-Threading, AVC |
20 | Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu |
Tolerating Cache-Miss Latency with Multipass Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(1), pp. 40-47, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Flea-flicker, multipass pipelining, memory-latency tolerance, in-order design |
20 | Abhishek Das, William J. Dally, Peter R. Mattson |
Compiling for stream processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 33-42, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SRF allocation, Stream Operation Precedence (SOP) graph, StreamC, coarse-grained operations, producer-consumer locality, scoreboard slot assignment, stream scheduling, strip-mining, software-pipelining, task level parallelism, stream programming model |
20 | Peter Sanders 0001, Jesper Larsson Träff |
Parallel Prefix (Scan) Algorithms for MPI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PVM/MPI ![In: Recent Advances in Parallel Virtual Machine and Message Passing Interface, 13th European PVM/MPI User's Group Meeting, Bonn, Germany, September 17-20, 2006, Proceedings, pp. 49-57, 2006, Springer, 3-540-39110-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MPI implementation, pipelining, collective communication, prefix sum, Cluster of SMPs |
20 | Genhua Jin, Hyuk-Jae Lee |
A Parallel and Pipelined Execution of H.264/AVC Intra Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 246, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
block processing order, pipelining, H.264, parallel execution, Intra prediction |
Displaying result #201 - #300 of 1754 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ 12][ >>] |
|