Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Roland Kasper, Steffen Toscher	Reconfigurable Controllers - A Mechatronic Systems Approach.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Alexander Thomas, Jürgen Becker 0001	Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Enno Lübbers, Marco Platzner	ReconOS: An Operating System for Dynamically Reconfigurable Hardware.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Matthias Alles, Timo Vogt, Christian Brehm, Norbert Wehn	FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Christopher Claus, Walter Stechele	AutoVision - Reconfigurable Hardware Acceleration for Video-Based Driver Assistance.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Marc Stöttinger, Felix Madlener, Sorin A. Huss	Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Tobias G. Noll, Thorsten von Sydow, Bernd Neumann, Jochen Schleifer, Thomas Coenen, Götz Kappen	Reconfigurable Components for Application-Specific Processor Architectures.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel	Evaluation and Design Methods for Processor-Like Reconfigurable Architectures.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle, Thilo Pionteck	DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Christian Haubelt, Dirk Koch, Felix Reimann, Thilo Streichert, Jürgen Teich	ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Peter M. Athanas, Jürgen Becker 0001, Jürgen Teich, Ingrid Verbauwhede	10281 Abstracts Collection - Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Peter M. Athanas, Jürgen Becker 0001, Jürgen Teich, Ingrid Verbauwhede	10281 Summary - Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	René Cumplido, Juan M. Campos, Claudia Feregrino Uribe, Jose Roberto Perez-Andrade	Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Jim Tørresen, Dirk Koch	A new project to address run-time reconfigurable hardware systems.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Jens Huthmann, Peter Müller 0010, Florian Stock, Dietmar Hildenbrand, Andreas Koch 0001	Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Matthias Hanke, Tim Kranich, Mladen Berekovic, Yannis Papaefstathiou	Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Walter Stechele, Christopher Claus, Andreas Laika	Lessons Learned from last 4 Years of Reconfigurable Computing.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Rainer Buchty	Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Douglas L. Maskell, Timothy F. Oliver	Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Jürgen Becker 0001, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas	06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Jürgen Becker 0001, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas	06141 Executive Summary -- Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Norbert Wehn, Timo Vogt, Christian Neeb	A Reconfigurable Outer Modem Platform for Future Communications Systems.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	József Vásárhelyi, Péter Serfözö	Analysis of Mojette Transform Implementation on Reconfigurable Hardware.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Peter Zipf, Manfred Glesner	Towards an Automated Design of Application-specific Reconfigurable Logic.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Walter Stechele	Dynamically Reconfigurable Systems-on-Chip.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Aravind Dasu, Ali Akoglu, Sethuraman Panchanathan	An Analysis Tool Set for Reconfigurable Media Processing.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Vincent Nollet, Jean-Yves Mignolet, T. Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins	Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	James M. McCollum, Joseph M. Lancaster, Gregory D. Peterson	Using Reconfigurable Computing to Accelerate Simulation Applications.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	X. Zhang, Gabriel Dragffy, Anthony G. Pipe, Nigel Gunton, Quan Min Zhu	A Reconfigurable Self-Healing Embryonic Cell Architecture.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Christophe Wolinski, Frans Trouw, Maya B. Gokhale	A Preliminary Study of Molecular Dynamics on Reconfigurable Computers.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Soheil Ghiasi, Hyun J. Moon, Majid Sarrafzadeh	Collaborative and Reconfigurable Object Tracking.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Gerard K. Rauwerda, Gerard J. M. Smit, L. F. W. van Hoesel, Paul M. Heysters	Mapping Wireless Communication Algorithms to a Reconfigurable Architecture.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Janusz A. Starzyk, Yongtao Guo	Dynamically Self-Reconfigurable Machine Learning Structure for FPGA Implementation.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Neil W. Bergmann, John A. Williams 0001, Peter Waldeck	Egret: A Flexible Platform for Real-Time Reconfigurable Systems on Chip.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Darrin M. Hanna, Richard E. Haskell	Using Flowpaths for the High-Level Synthesis of Reconfigurable Systems.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Nikolaos G. Bartzoudis, Alexandros G. Fragkiadakis, David J. Parish, Jose Luis Nunez, Mark Sandford	Reconfigurable Computing and Active Networks.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Herbert Walder, Marco Platzner	Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	John P. Morrison, Padraig J. O'Dowd, Philip D. Healy	Searching RC5 Keyspaces with Distributed Reconfigurable Hardware.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Jack S. N. Jean, Xinzhong Guo, Fei Wang 0009, Lei Song, Ying Zhang	A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Lilian Bossuet, Guy Gogniat, Jean Luc Philippe	Fast Design Space Exploration Method for Reconfigurable Architectures.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Linda Kaouane, Mohamed Akil, Thierry Grandpierre, Yves Sorel	A Methodology to Implement Real-Time Applications on Reconfigurable Circuits.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Nick Tredennick, Brion Shimamoto	The Rise of Reconfigurable Systems.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Valery Sklyarov, Iouliia Skliarova	Architecture of a Reconfigurable Processor for Implementing Search Algorithm over Discrete Matrices.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Dominique Lavenier, Stéphane Guyetant, Steven Derrien, Stéphane Rubini	A Reconfigurable Parallel Disk System for Filtering Genomic Banks.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
28	Shawn A. Bohner, Ramya Ravichandar, James D. Arthur	Model-based engineering for change-tolerant systems.	Innov. Syst. Softw. Eng.	2007	DBLP DOI BibTeX RDF	Change tolerance, Capabilities engineering, Model-driven architecture, Reconfigurable computing, Complex systems, Agent-based systems, Model-based engineering
28	Ronald Hecht, Stephan Kubisch, Harald Michelsen, Elmar Zeeb, Dirk Timmermann	A distributed object system approach for dynamic reconfiguration.	IPDPS	2006	DBLP DOI BibTeX RDF
28	José Manuel Moya, Javier Rodríguez Escolar, Julio Martín, Juan Carlos Vallejo, Pedro Malagón, Álvaro Araujo, Juan-Mariano de Goyeneche, Agustín Rubio, Elena Romero, Daniel Villanueva, Octavio Nieto-Taladriz, Carlos A. López-Barrio	SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems.	ARC	2009	DBLP DOI BibTeX RDF	Application-transparent adaptation, Ubiquitous computing, Reconfigurable hardware, Adaptable architectures
28	Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin	The Need for Reconfigurable Routers in Networks-on-Chip.	ARC	2009	DBLP DOI BibTeX RDF	heterogeneous NoC, reconfigurable router, buffer, FIFO
28	Peiheng Zhang, Guangming Tan, Guang R. Gao	Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform.	HPRCTA	2007	DBLP DOI BibTeX RDF	reconfigurable supercomputing, FPGA, coprocessor, Smith-Waterman algorithm
28	Esam El-Araby, Iván González, Tarek A. El-Ghazawi	Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing.	HPRCTA	2007	DBLP DOI BibTeX RDF	field programmable gate arrays (FPGA), high performance computing, reconfigurable computing, dynamic partial reconfiguration
28	Christophe Bobda, Ali Ahmadinia	Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Dynamic Interconnection, Network on Chip, Reconfigurable Hardware
28	Daniel Ménard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David	Reconfigurable Operator Based Multimedia Embedded Processor.	ARC	2009	DBLP DOI BibTeX RDF
28	Tobias Becker, Wayne Luk, Peter Y. K. Cheung	Parametric Design for Reconfigurable Software-Defined Radio.	ARC	2009	DBLP DOI BibTeX RDF
28	Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele	Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.	ARC	2008	DBLP DOI BibTeX RDF
28	Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev	Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.	ARC	2007	DBLP DOI BibTeX RDF
28	Edson Pedro Ferlin, Heitor S. Lopes, Carlos Raimundo Erig Lima, Ederson Cichaczewski	Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits.	ARC	2007	DBLP DOI BibTeX RDF
28	Yeong-Jae Oh, Hanho Lee, Chong Ho Lee	Dynamic Partial Reconfigurable FIR Filter Design.	ARC	2006	DBLP DOI BibTeX RDF
28	Katherine Compton, Akshay Sharma, Shawn Phillips, Scott Hauck	Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems.	FPL	2002	DBLP DOI BibTeX RDF
28	Domingo Benitez	A Quantitative Understanding of the Performance of Reconfigurable Coprocessors.	FPL	2002	DBLP DOI BibTeX RDF
28	Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida	A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model.	FPL	2002	DBLP DOI BibTeX RDF
28	Hideharu Amano, Yuichiro Shibata, Masaki Uno	Reconfigurable Systems: New Activities in Asia.	FPL	2000	DBLP DOI BibTeX RDF
28	Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano	A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.	FPL	2000	DBLP DOI BibTeX RDF
28	Abdellah Touhafi	A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller.	FPL	2000	DBLP DOI BibTeX RDF
28	Milan Vasilko	Design Visualisation for Dynamically Reconfigurable Systems.	FPL	2000	DBLP DOI BibTeX RDF
26	Min Xie, Youren Wang, Li Wang, Yuan Zhang	Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.	ICES	2007	DBLP DOI BibTeX RDF	Operator-based programmable cell circuit, FPGA, Reconfigurable computing, Reconfigurable hardware, Information processing
26	Siu-Cheung Chau, Ada Wai-Chee Fu	A reconfigurable fault-tolerant hypercube architecture with global sparing.	PRDC	2000	DBLP DOI BibTeX RDF	reconfigurable fault-tolerant hypercube architecture, global sparing, reliability, fault tolerant computing, reconfigurable architectures, hypercube networks, switching networks, switching networks
26	Douglas Chang, Malgorzata Marek-Sadowska	Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Dynamically reconfigurable FPGAs, time-mulitplexed FPGA, Dharma, DPGA, field programmable gate array, partitioning, reconfigurable computing, sequential circuit, force directed scheduling
26	Jeffrey A. Jacob, Paul Chow	Memory Interfacing and Instruction Specification for Reconfigurable Processors.	FPGA	1999	DBLP DOI BibTeX RDF	memory interfacing, FPGA, reconfigurable computer, reconfigurable processor, memory coherence
26	Sanguthevar Rajasekaran	Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing and Sorting.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	mesh with reconfigurable buses, mesh with fixed buses, k?k routing, k?k sorting, parallel computing, randomized algorithms, sorting, mesh, packet routing, Reconfigurable networks
26	Ridha Djemal, Guy Mazaré, Gérard Michel	Toward reconfigurable associative architecture for high speed communication operators.	ECBS	1996	DBLP DOI BibTeX RDF	reconfigurable associative architecture, high speed communication operators, associative organization, complex data structures, structured addressable associative memory, high speed communication protocols, CAM architectures, SYMOPSYS tool, architecture validation, FPGA, real-time systems, real-time, asynchronous transfer mode, asynchronous transfer mode, local area networks, local area network, reconfigurable architectures, memory architecture, LAN, content-addressable storage
26	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
26	Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen	An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching network fault diagnosis, reconfigurable VLSI/WSI array processors, switching network defects, killing error, testing circuit overhead, diagnosis time, mesh array, VLSI, parallel architectures, fault diagnosis, reconfigurable architectures, multiple faults, switching networks, wafer-scale integration, testing quality
26	C. S. Yang, L. P. Zu, Y. N. Wu	A Reconfigurable Modular Fault-Tolerant Hypercube Architecture.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	reconfigurable modular fault-tolerant hypercube, modular hypercube, spare-sharing links, ring connection, local spares, FTM, switch failures, modular reconfiguration, reliability, parallel architectures, fault tolerant computing, reconfigurable architectures, hypercube networks, switches, system recovery, links, nodes, system reliability, link failures, fault-tolerant design, faulty nodes, hypercube system, hypercube architecture
26	Sy-Yen Kuo, W. Kent Fuchs	Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	reconfigurable PLAs, spare allocation, circuit density, chip size, fault diagnosis algorithm, computational complexity, fault tolerant computing, fault location, programmable logic arrays, multiple faults, logic arrays, yield enhancement, reconfigurable logic, memory structures, circuit reliability, manufacturing yield
26	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	A 3d-audio reconfigurable processor.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable computing, communication systems, beamforming, 3d-audio, wave field synthesis
26	Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
26	Kristian Stevens, Henry Chen, Terry Filiba, Peter L. McMahon, Yun S. Song	Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	genome resequencing, fpga, acceleration, reconfigurable logic
26	Zhimin Chen 0002, Richard Neil Pittman, Alessandro Forin	Combining multicore and reconfigurable instruction set extensions.	FPGA	2010	DBLP DOI BibTeX RDF	extensible microprocessors, reconfigurable instruction set extensions, embedded, multi-core
26	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
26	Vincenzo Rana, Donatella Sciuto	A novel design framework for the design of reconfigurable systems based on NoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	network-on-chip, reconfigurable computing, design flow, mapping algorithm
26	Sansiri Tanachutiwat, Ji Ung Lee, Wei Wang 0003, Chun Yung Sung	Reconfigurable multi-function logic based on graphene P-N junctions.	DAC	2010	DBLP DOI BibTeX RDF	graphene, p-n junction, logic gate, device, reconfigurable logic
26	Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol	An efficient dynamically reconfigurable on-chip network architecture.	DAC	2010	DBLP DOI BibTeX RDF	performance, reconfigurable, topology, power, NoC
26	Yong Dou, Guiming Wu, Jinhui Xu 0002, Xingming Zhou	A coarse-grained reconfigurable computing architecture with loop self-pipelining.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	reconfigurable computing, data driven, loop pipelining, register promotion
26	Byunghyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim	Thermal sensor allocation and placement for reconfigurable systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimal placement, unate-covering problem, reconfigurable system, Thermal sensor
26	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
26	Jason Cong, Karthik Gururaj, Guoling Han	Synthesis of reconfigurable high-performance multicore systems.	FPGA	2009	DBLP DOI BibTeX RDF	coprocessor synthesis, reconfigurable high-performance computing, design space exploration
26	Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, Kiwook Yoon	Coarse-grained reconfigurable architecture for multiple application domains: a case study.	ICHIT	2009	DBLP DOI BibTeX RDF	system design, coarse-grained reconfigurable architecture
26	Björn Osterloh, Harald Michalik, Björn Fiethe	SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs.	ARCS	2009	DBLP DOI BibTeX RDF	SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC
26	Yupeng Chen, Bertil Schmidt, Douglas L. Maskell	A Reconfigurable Bloom Filter Architecture for BLASTN.	ARCS	2009	DBLP DOI BibTeX RDF	genomic sequence analysis, bioinformatics, reconfigurable computing, Bloom filter
26	Juan Fernando Eusse Giraldo, Michael Hübner 0001, Ricardo Pezzuol Jacobi	BRICK: a multi-context expression grained reconfigurable architecture.	SBCCI	2009	DBLP DOI BibTeX RDF	validation, reconfigurable computing, MIMO, SystemC, co-simulation, coarse grain
26	Yoonjin Kim, Rabi N. Mahapatra	Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems.	DAC	2009	DBLP DOI BibTeX RDF	coarse-grained reconfigurable architecture (CGRA), computing hierarchy, embedded systems
26	Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont	Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW
26	D. Dhanasekaran, K. Boopathy Bagan	Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF	Virtual Reconfigurable circuit, element validation, Evolvable hardware
26	Dimitrios Lymberopoulos, Nissanka Bodhi Priyantha, Feng Zhao 0001	mPlatform: a reconfigurable architecture and efficient data sharing mechanism for modular sensor nodes.	IPSN	2007	DBLP DOI BibTeX RDF	high speed data bus, reconfigurable sensor node, CPLD, modular architecture
26	Marco Lanuzza, Stefania Perri, Pasquale Corsonello	MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing.	SAMOS	2007	DBLP DOI BibTeX RDF	coarse-grain array, multimedia applications, Reconfigurable systems
26	Suvda Myagmar, Roy H. Campbell, Marianne Winslett	Security Challenges of Reconfigurable Devices in the Power Grid.	Critical Infrastructure Protection	2007	DBLP DOI BibTeX RDF	reconfigurable devices, security, software defined radios, Power grid
26	Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara	Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers.	DATE	2007	DBLP DOI BibTeX RDF	reconfigurable union wrapper, system-on-a-chip, test scheduling, test access mechanism
26	Monica Magalhães Pereira, Bruno Cruz de Oliveira, Ivan Saraiva Silva	RoSA: a reconfigurable stream-based architecture.	SBCCI	2007	DBLP DOI BibTeX RDF	stream-based, reconfigurable architecture, coarse-grained
26	Wei-Min Shen, Maks Krivokon, Harris Chi Ho Chiu, Jacob Everist, Michael Rubenstein, Jagadesh Venkatesh	Multimode locomotion via SuperBot reconfigurable robots.	Auton. Robots	2006	DBLP DOI BibTeX RDF	Multifunctional and Self-reconfigurable robots, Multimode gaits, Modular, Space robots
26	Salvatore Carta, Danilo Pani, Luigi Raffo	Reconfigurable Coprocessor for Multimedia Application Domain.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	multimedia, reconfigurable computing, digital signal processing, domain-specific architectures