Search results for "sub-threshold"

Hits ?▲	Authors	Title	Venue	Year	Link
15	Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi	Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
15	Mahmoud Zangeneh, Ajay Joshi	Sub-threshold logic circuit design using feedback equalization.	DATE	2014	DBLP DOI BibTeX RDF
15	Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici	Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits.	DSD	2014	DBLP DOI BibTeX RDF
15	Tiansong Cui, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram	Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variation.	ASP-DAC	2014	DBLP DOI BibTeX RDF
15	Monther Abusultan, Sunil P. Khatri	Look-up Table Design for Deep Sub-threshold through Full-Supply Operation.	FCCM	2014	DBLP DOI BibTeX RDF
15	Yingbo Zhao, Yintang Yang, Kaushik Mazumdar, Xinfei Guo, Mircea R. Stan	A multi-output on-chip switched-capacitor DC-DC converter for near- and sub-threshold power modes.	ISCAS	2014	DBLP DOI BibTeX RDF
15	C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi	Single-ended sub-threshold finfet 7T SRAM cell without boosted supply.	ICICDT	2014	DBLP DOI BibTeX RDF
15	C. B. Kushwah, Santosh Kumar Vishvakarma	A sub-threshold eight transistor (8T) SRAM cell design for stability improvement.	ICICDT	2014	DBLP DOI BibTeX RDF
15	Yanqing Zhang 0002, Benton H. Calhoun	Fast, accurate variation-aware path timing computation for sub-threshold circuits.	ISQED	2014	DBLP DOI BibTeX RDF
15	Tiansong Cui, Shuang Chen 0001, Yanzhi Wang, Shahin Nazarian, Massoud Pedram	An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect.	ISQED	2014	DBLP DOI BibTeX RDF
15	Bo Liu, Maryam Ashouei, Tobias Gemmeke, José Pineda de Gyvez	Sub-threshold custom standard cell library validation.	ISQED	2014	DBLP DOI BibTeX RDF
15	Yu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wan-Yu Wen, Yiyu Shi 0001, Shih-Chieh Chang	Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs.	DAC	2014	DBLP DOI BibTeX RDF
15	Menka Yadav, Anand Bulusu, Sudeb Dasgupta	Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
15	P. Suveetha Dhanaselvam, N. B. Balamurugan, V. N. Ramakrishnan	A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
15	Yingbo Hu, Keshab K. Parhi	Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits.	J. Signal Process. Syst.	2013	DBLP DOI BibTeX RDF
15	Ali Sahafi, Jafar Sobhi, Ziaddin Daei Koozehkanani	Pico Watt sub-threshold CMOS voltage reference circuit.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
15	Amin Zafarian, Iraj Kalali Fard, Abbas Golmakani, Jalil Shirazi	A 0.4V 790μw CMOS low noise amplifier in sub-threshold region at 1.5GHz.	IDT	2013	DBLP DOI BibTeX RDF
15	KyungSoo Kim, Wansoo Nah, SoYoung Kim	Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits.	EMC Compo	2013	DBLP DOI BibTeX RDF
15	Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang I Vai, Rui Paulo Martins	Sub-threshold standard cell library design for ultra-low power biomedical applications.	EMBC	2013	DBLP DOI BibTeX RDF
15	Changhyuk Lee, Ben Johnson, Alyosha C. Molnar	A sub-threshold voltage ladder rectifier for orthogonal current-reuse neural amplifier.	BioCAS	2013	DBLP DOI BibTeX RDF
15	Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang	Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.	ISCAS	2013	DBLP DOI BibTeX RDF
15	Nandish Mehta, Kofi A. A. Makinwa	Minimum energy point tracking for sub-threshold digital CMOS circuits using an in-situ energy sensor.	ISCAS	2013	DBLP DOI BibTeX RDF
15	Robert Kappel, Mario Auer, Wolfgang Pribyl, Günter Hofer, Gerald Holweg	A process-variation compensation scheme to operate CMOS digital logic cells in deep sub-threshold region at 80mV.	ISCAS	2013	DBLP DOI BibTeX RDF
15	Jaeyoung Kim, Kwen-Siong Chong, Joseph Sylvester Chang, Pinaki Mazumder	A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
15	Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi, Roghayeh Saeidi	A novel low power 8T-cell sub-threshold SRAM with improved read-SNM.	DTIS	2013	DBLP DOI BibTeX RDF
15	Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi, Roghayeh Saeidi	A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM.	DTIS	2013	DBLP DOI BibTeX RDF
15	Nupur Navlakha, Lokesh Garg, Dharmendar Boolchandani, Vineet Sahula	Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals.	VDAT	2013	DBLP DOI BibTeX RDF
15	Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang	Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
15	Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin	Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
15	Meeta Srivastav, Michael B. Henry, Leyla Nazhandali	Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
15	Rohit Dhiman, Rajeevan Chandel	Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.	J. Low Power Electron.	2012	DBLP DOI BibTeX RDF
15	Jacopo Franco, S. Graziano, Ben Kaczer, Felice Crupi, Lars-Åke Ragnarsson, Tibor Grasser, Guido Groeseneken	BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
15	Yingchieh Ho, Hung-Kai Chen 0001, Chauchin Su	Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2012	DBLP DOI BibTeX RDF
15	Jornt R. De Gruijl, Paolo Bazzigaluppi, Marcel T. G. de Jeu, Chris I. De Zeeuw	Climbing Fiber Burst Size and Olivary Sub-threshold Oscillations in a Network Setting.	PLoS Comput. Biol.	2012	DBLP DOI BibTeX RDF
15	Nele Reynders, Wim Dehaene	Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Alicia Klinefelter, Yanqing Zhang 0002, Brian P. Otis, Benton H. Calhoun	A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Adam Teman, Anatoli Mordakhay, Janna Mezhibovsky, Alexander Fish	A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Jun Zhou 0017, Senthil Jayapal, Ben Busze, Li Huang, Jan Stuyt	A 40 nm Dual-Width Standard Cell Library for Near/Sub-Threshold Operation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
15	Tobias Gemmeke, Maryam Ashouei, Tobias G. Noll	Noise Margin Based Library Optimization Considering Variability in Sub-threshold.	PATMOS	2012	DBLP DOI BibTeX RDF
15	Yongsuk Choi, Yong-Bin Kim, Fabrizio Lombardi	Soft error masking latch for sub-threshold voltage operation.	MWSCAS	2012	DBLP DOI BibTeX RDF
15	Rajsaktish Sankaranarayanan, Matthew R. Guthaus	A single-VDD ultra-low energy sub-threshold FPGA.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
15	Nele Reynders, Wim Dehaene	Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency.	ESSCIRC	2012	DBLP DOI BibTeX RDF
15	Tobias Gemmeke, Maryam Ashouei	Variability aware cell library optimization for reliable sub-threshold operation.	ESSCIRC	2012	DBLP DOI BibTeX RDF
15	Abhijit Sil, Srikanth Bakkamanthala, Swetha Karlapudi, Magdy A. Bayoumi	Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application.	NEWCAS	2012	DBLP DOI BibTeX RDF
15	Aleksandar Pajkanovic, Tom J. Kazmierski, Branko Dokic	Minimum energy point of sub-threshold operated pass-transistor circuits.	FDL	2012	DBLP BibTeX RDF
15	Janna Mezhibovsky, Adam Teman, Alexander Fish	State space modeling for sub-threshold SRAM stability analysis.	ISCAS	2012	DBLP DOI BibTeX RDF
15	Marco Donato, Fabio Cremona, Warren Jin 0002, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy	A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
15	Meeta Srivastav, Michael B. Henry, Leyla Nazhandali	Design of low-power, scalable-throughput systems at near/sub threshold voltage.	ISQED	2012	DBLP DOI BibTeX RDF
15	Anis Feki, Bruno Allard, David Turgis, Jean-Christophe Lafont, Lorenzo Ciampolini	Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell.	ISOCC	2012	DBLP DOI BibTeX RDF
15	Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang	A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
15	Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang	Testing strategies for a 9T sub-threshold SRAM.	ITC	2012	DBLP DOI BibTeX RDF
15	Chandrabhan Kushwah, Santosh Kumar Vishvakarma	Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin.	VDAT	2012	DBLP DOI BibTeX RDF
15	Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry	Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
15	Kai Kinoshita, Hiroyuki Torikai	A Self-Organizing Pulse-Coupled Network of Sub-Threshold Oscillating Spiking Neurons.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
15	Hui Shao, Xing Li 0004, Chi-Ying Tsui	Low energy multi-stage level converter for sub-threshold logic.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
15	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
15	Jun Zhou, Maryam Ashouei, David Kinniment, Jos Huisken, Gordon Russell 0002, Alexandre Yakovlev	Sub-threshold synchronizer.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
15	Basab Datta, Wayne P. Burleson	Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
15	Wei Jin 0004, Sheng Lu, Weifeng He, Zhigang Mao	Robust design of sub-threshold flip-flop cells for wireless sensor network.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
15	Wei Jin 0004, Sheng Lu, Weifeng He, Zhigang Mao	A 230mV 8-bit sub-threshold microprocessor for wireless sensor network.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
15	Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni 0001, Israel Koren	Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation.	RFIDSec	2011	DBLP DOI BibTeX RDF
15	Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens	Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder.	DSD	2011	DBLP DOI BibTeX RDF
15	Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez	Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage.	DSD	2011	DBLP DOI BibTeX RDF
15	Jun Zhou, Senthil Jayapal, Jan Stuyt, Jos Huisken, Harmke de Groot	The impact of inverse narrow width effect on sub-threshold device sizing.	ASP-DAC	2011	DBLP DOI BibTeX RDF
15	Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao	Detecting stability faults in sub-threshold SRAMs.	ICCAD	2011	DBLP DOI BibTeX RDF
15	David Li, Pierce Chuang, David Nairn, Manoj Sachdev	Design and analysis of metastable-hardened flip-flops in sub-threshold region.	ISLPED	2011	DBLP BibTeX RDF
15	Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang	Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation.	ISLPED	2011	DBLP BibTeX RDF
15	Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang	8T single-ended sub-threshold SRAM with cross-point data-aware write operation.	ISLPED	2011	DBLP BibTeX RDF
15	Y. Joly, L. Truphemus, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Franck Julien, Pascal Fornara	Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area.	ISCAS	2011	DBLP DOI BibTeX RDF
15	Chenchang Zhan, Wing-Hung Ki	An output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction for SoC.	ISCAS	2011	DBLP DOI BibTeX RDF
15	Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato	A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization.	SoCC	2011	DBLP DOI BibTeX RDF
15	Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang	An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions.	SoCC	2011	DBLP DOI BibTeX RDF
15	Basab Datta, Wayne P. Burleson	A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
15	Basab Datta, Wayne P. Burleson	A 12.4μm2 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation.	ISQED	2011	DBLP DOI BibTeX RDF
15	Sandeep Sriram, Haiqing Nan, Ken Choi	Low power latch design in near sub-threshold region to improve reliability for soft error.	ISQED	2011	DBLP DOI BibTeX RDF
15	Nele Reynders, Wim Dehaene	A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques.	A-SSCC	2011	DBLP DOI BibTeX RDF
15	Seokjoong Kim, Matthew R. Guthaus	Leakage-aware redundancy for reliable sub-threshold memories.	DAC	2011	DBLP DOI BibTeX RDF
15	Jun Zhou 0017, Senthil Jayapal, Ben Busze, Li Huang, Jan Stuyt	A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library.	DAC	2011	DBLP DOI BibTeX RDF
15	Antonino Vallesi, Donald T. Stuss	Excessive sub-threshold motor preparation for non-target stimuli in normal aging.	NeuroImage	2010	DBLP DOI BibTeX RDF
15	Adelmo Ortiz-Conde, Francisco J. García-Sánchez, Juin J. Liou, Ching-Sung Ho	Integration-based approach to evaluate the sub-threshold slope of MOSFETs.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
15	Hiroyuki Mino, Dominique M. Durand	Enhancement of information transmission of sub-threshold signals applied to distal positions of dendritic trees in hippocampal CA1 neuron models with stochastic resonance.	Biol. Cybern.	2010	DBLP DOI BibTeX RDF
15	Mehrdad H. Zadeh, David Wang 0001, Eric Kubica	The effect of sub-threshold forces on human performance in multi-modal computer-aided design.	Comput. Aided Des.	2010	DBLP DOI BibTeX RDF
15	Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy 0001	Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
15	Farzan Jazayeri, Ahmad Sammak, Behjat Forouzandeh, Farshid Raissi	A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
15	Niklas Lotze, Jacob Göppert, Yiannos Manoli	Timing modeling for digital sub-threshold circuits.	DATE	2010	DBLP DOI BibTeX RDF
15	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study.	ASYNC	2010	DBLP DOI BibTeX RDF
15	Joseph F. Ryan 0002, Benton H. Calhoun	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
15	Mehrdad Khatir, Hassan Ghasemzadeh Mohammadi, Alireza Ejlali	Sub-threshold charge recovery circuits.	ICCD	2010	DBLP DOI BibTeX RDF
15	Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry	Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops.	ISCAS	2010	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Sudhanshu Khanna, Yanqing Zhang 0002, Joseph F. Ryan 0002, Brian P. Otis	System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms.	ISCAS	2010	DBLP DOI BibTeX RDF
15	Matthias W. Blesken, Sven Lütkemeier, Ulrich Rückert 0001	Multiobjective optimization for transistor sizing sub-threshold CMOS logic standard cells.	ISCAS	2010	DBLP DOI BibTeX RDF
15	Milad Ataei, Mohsen Tamaddon, Abumoslem Jannesari	A low-power sub-threshold CMOS continuous-time active-filter with reduced in-band noise for WiMAX applications.	APCCAS	2010	DBLP DOI BibTeX RDF
15	Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy 0001	A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
15	Apisak Worapishet, Phanumas Khumsat	Analysis and Design of Sub-Threshold R-MOSFET Tunable Resistor.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
15	Omer Can Akgun, Frank K. Gürkaynak, Yusuf Leblebici	A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime.	Int. J. Circuit Theory Appl.	2009	DBLP DOI BibTeX RDF
15	S. Ramasamy, B. Venkataramani, P. Meenatchisundaram	A low power CMOS voltage reference circuit with sub threshold MOSFETs.	Int. J. Inf. Commun. Technol.	2009	DBLP DOI BibTeX RDF
15	Wei Bian, Jin He 0003, Lining Zhang, Jian Zhang 0002, Mansun Chan	Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
15	Mark Tuckwell, Christos Papavassiliou	An Analog Gabor Transform Using Sub-Threshold 180-nm CMOS Devices.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Sudhanshu Khanna, Randy W. Mann, Jiajing Wang	Sub-threshold Circuit Design with Shrinking CMOS Devices.	ISCAS	2009	DBLP DOI BibTeX RDF