Search results for "CPU"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Shlomit S. Pinter, Marcel Zalmanovici	Data Sharing Conscious Scheduling for Multi-threaded Applications on SMP Machines.	Euro-Par	2006	DBLP DOI BibTeX RDF
18	Naga K. Govindaraju, Jim Gray 0001, Ritesh Kumar, Dinesh Manocha	GPUTeraSort: high performance graphics co-processor sorting for large database management.	SIGMOD Conference	2006	DBLP DOI BibTeX RDF
18	Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews 0001	Enabling a Uniform Programming Model Across the Software/Hardware Boundary.	FCCM	2006	DBLP DOI BibTeX RDF
18	Federico Rota, Shantanu Dutt, Sahithi Krishna	Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream.	DFT	2006	DBLP DOI BibTeX RDF
18	Soo-Cheol Oh, Seongwoon Kim	An Efficient Linux Kernel Module supporting TCP/IP Offload Engine on Grid.	GCC	2006	DBLP DOI BibTeX RDF
18	Torsten Hoefler, Jeffrey M. Squyres, Wolfgang Rehm, Andrew Lumsdaine	A Case for Non-blocking Collective Operations.	ISPA Workshops	2006	DBLP DOI BibTeX RDF	Non-blocking communication, Message passing (MPI), Collective communication, Overlap
18	Michael Kagan	InfiniBand interconnects - Application acceleration through MPI overlap.	SC	2006	DBLP DOI BibTeX RDF
18	Min Yeol Lim, Vincent W. Freeh, David K. Lowenthal	MPI and communication - Adaptive, transparent frequency and voltage scaling of communication phases in MPI programs.	SC	2006	DBLP DOI BibTeX RDF
18	Hyong-youb Kim, Scott Rixner	TCP offload through connection handoff.	EuroSys	2006	DBLP DOI BibTeX RDF	TCP offload, connection handoff, programmable network interface, operating system
18	Prakash Ishwar, Rohit Puri, Kannan Ramchandran, S. Sandeep Pradhan	On rate-constrained distributed estimation in unreliable sensor networks.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
18	Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, Steven K. Reinhardt	Performance Analysis of System Overheads in TCP/IP Workloads.	IEEE PACT	2005	DBLP DOI BibTeX RDF
18	Razali Jidin, David Andrews 0001, Wesley Peck, Dan Chirpich, Kevin Stout, John M. Gauch	Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild	FlexPath NP: a network processor concept with application-driven flexible processing paths.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	dynamically reconfigurable processors, network processors, hardware accelerators, IP networking, application-specific architectures
18	In-Su Yoon, Sang-Hwa Chung	Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
18	Aaron E. Lefohn, Ian Buck, Patrick S. McCormick, John D. Owens, Timothy J. Purcell, Robert Strzodka	General Purpose Computation on Graphics Hardware.	IEEE Visualization	2005	DBLP DOI BibTeX RDF
18	Seonho Choi	Denial-of-Service Resistant Multicast Authentication Protocol with Prediction Hashing and One-way Key Chain.	ISM	2005	DBLP DOI BibTeX RDF
18	Christian Poellabauer, Leo Singleton, Karsten Schwan	Feedback-Based Dynamic Voltage and Frequency Scaling for Memory-Bound Real-Time Applications.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
18	Sookyoung Kim, Thomas L. Martin	DIP: a double-interval-based dynamic voltage scaling scheme for dynamic priority-based task scheduling systems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dynamic priority-based task scheduling systems, dynamic voltage scaling, low energy
18	Le Yan, Lin Zhong 0001, Niraj K. Jha	User-perceived latency driven voltage scaling for interactive applications.	DAC	2005	DBLP DOI BibTeX RDF	adaptive body biasing, computer responsiveness, dynamic voltage scaling, power consumption
18	Ming Xiong, Krithi Ramamritham	Deriving Deadlines and Periods for Real-Time Update Transactions.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	temporal validity, deadline monotonic scheduling, real-time transaction processing, fixed priority scheduling, Real-time database systems
18	Kihwan Choi, Ramakrishna Soma, Massoud Pedram	Dynamic voltage and frequency scaling based on workload decomposition.	ISLPED	2004	DBLP DOI BibTeX RDF	workload decomposition, dynamic voltage and frequency scaling
18	Kihwan Choi, Ramakrishna Soma, Massoud Pedram	Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding.	DAC	2004	DBLP DOI BibTeX RDF	MPEG decoding, voltage and frequency scaling, low power
18	Jacob R. Lorch, Alan Jay Smith	Using User Interface Event Information in Dynamic Voltage Scaling Algorithms.	MASCOTS	2003	DBLP DOI BibTeX RDF	Workload characterization and generation, power management, dynamic voltage scaling, response time, modeling and simulation, energy management
18	Ariel Cohen 0003	A Performance Analysis of 4X InfiniBand Data Transfer Operations.	IPDPS	2003	DBLP DOI BibTeX RDF	performance, TCP, InfiniBand, RDMA, Gigabit Ethernet
18	DongWoo Lee, Rudrapatna S. Ramakrishna	Disk I/O Performance Forecast Using Basic Prediction Techniques for Grid Computing.	PaCT	2003	DBLP DOI BibTeX RDF
18	Francesco Quaglia, Andrea Santoro	Modeling and optimization of non-blocking checkpointing for optimistic simulation on myrinet clusters.	ICS	2003	DBLP DOI BibTeX RDF	checkpointing, performance optimization, DMA, optimistic simulation
18	Christian Böhm 0001, Hans-Peter Kriegel	Optimale Dimensionswahl bei der Bearbeitung des Similarity Join.	Inform. Forsch. Entwickl.	2002	DBLP DOI BibTeX RDF	hnlichkeitsverbund, Ähnlichkeitssuche, Multimedia-Datenbank, Indexstruktur, Data Mining
18	Sourav Ghosh, Ragunathan Rajkumar	Resource Management of the OS Network Subsystem.	Symposium on Object-Oriented Real-Time Distributed Computing	2002	DBLP DOI BibTeX RDF
18	Jens Ernst, William S. Evans, Christopher W. Fraser, Steven Lucco, Todd A. Proebsting	Code Compression.	PLDI	1997	DBLP DOI BibTeX RDF
18	Kin K. Leung	An Execution/Sleep Scheduling Policy for Serving an Additional Job in Priority Queueing Systems.	J. ACM	1993	DBLP DOI BibTeX RDF	server vacation models, time-limited service, performance evaluation, response times, priority queues, waiting times
18	Tony Zingale	Distributed processing with iAPX 186 microprocessor systems.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
18	Andrew Heller, Andries van Dam	Vertical and outboard migration: a progress report.	AFIPS National Computer Conference	1981	DBLP DOI BibTeX RDF
18	David S. Lindsay	A hardware monitor study of a CDC KRONOS system.	SIGMETRICS	1976	DBLP DOI BibTeX RDF
15		CPU Cache.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
15	Lokman A. Abbas-Turki, Stéphane Vialle, Bernard Lapeyre, Patrick P. Mercier	High dimensional pricing of exotic European contracts on a GPU Cluster, and comparison to a CPU cluster.	IPDPS	2009	DBLP DOI BibTeX RDF
15	Shinichi Yamagiwa, Koichi Wada 0002	Performance study of interference on GPU and CPU resources with multiple applications.	IPDPS	2009	DBLP DOI BibTeX RDF
15	Markus Happe, Enno Lübbers, Marco Platzner	A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.	ARC	2009	DBLP DOI BibTeX RDF
15	Sundaresan Venkatasubramanian, Richard W. Vuduc	Tuned and wildly asynchronous stencil kernels for hybrid CPU/GPU systems.	ICS	2009	DBLP DOI BibTeX RDF	none
15	Garnett Carl Wilson, Wolfgang Banzhaf	Deployment of CPU and GPU-based genetic programming on heterogeneous devices.	GECCO (Companion)	2009	DBLP DOI BibTeX RDF	XBOX 360, ZUNE, genetic programming, graphics processing unit, GPGPU, heterogeneous devices
15	Takanori Ueda, Yu Hirate, Hayato Yamana	Exploiting idle CPU cores to improve file access performance.	ICUIMC	2009	DBLP DOI BibTeX RDF	access pattern mining, many core, access pattern, replacement algorithm, buffer caching
15	Marta Beltrán, Antonio Guzmán, José Luis Bosque	A New CPU Availability Prediction Model for Time-Shared Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Monitors, Performance measures, Modeling and prediction
15	Jarle Hulaas, Walter Binder	Program transformations for light-weight CPU accounting and control in the Java virtual machine.	High. Order Symb. Comput.	2008	DBLP DOI BibTeX RDF	Java, Program transformations, Resource management, Bytecode engineering
15	Lodewijk Bonebakker	Comparison of the SPEC CPU Benchmarks with 499 Other Workloads Using Hardware Counters.	SIPEW	2008	DBLP DOI BibTeX RDF	SPEC CPU2000, SPEC CPU2006, benchmark, workloads, workload characterization, comparison
15	Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers	CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures.	FPL	2008	DBLP DOI BibTeX RDF
15	Adam Herout, Pavel Zemcík, Roman Juránek, Michal Hradis	Implementation of the "Local Rank Differences" Image Feature Using SIMD Instructions of CPU.	ICVGIP	2008	DBLP DOI BibTeX RDF
15	Kurt Vanmechelen, Wim Depoorter, Jan Broeckhove	Economic Grid Resource Management for CPU Bound Applications with Hard Deadlines.	CCGRID	2008	DBLP DOI BibTeX RDF	Scheduling, Resource Management, Reservation, Co-allocation, Grid Economics
15	Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella	Design and evaluation of an optical CPU-DRAM interconnect.	ICCD	2008	DBLP DOI BibTeX RDF
15	Joël Goossens, Dragomir Milojevic, Vincent Nélis	Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms.	OPODIS	2008	DBLP DOI BibTeX RDF
15	Emerson Loureiro, Paddy Nixon, Simon Dobson	A Fine-Grained Model for Adaptive On-Demand Provisioning of CPU Shares in Data Centers.	IWSOS	2008	DBLP DOI BibTeX RDF
15	Maxim Leonov, Vyacheslav V. Kitaev	Feasibility Study of Implementing Multi-Channel Correlation for DSP Applications on Reconfigurable CPU+FPGA Platform.	PDCAT	2008	DBLP DOI BibTeX RDF
15	Bugra Gedik, Kun-Lung Wu, Philip S. Yu, Ling Liu 0001	CPU load shedding for binary stream joins.	Knowl. Inf. Syst.	2007	DBLP DOI BibTeX RDF	Stream joins, Data streams, Load shedding
15	Nevine AbouGhazaleh, Alexandre Peixoto Ferreira, Cosmin Rusu, Ruibin Xu, Frank Liberato, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Integrated CPU and l2 cache voltage scaling using machine learning.	LCTES	2007	DBLP DOI BibTeX RDF	integrated DVS policy, machine learning, power management, multiple clock domains
15	Marcelo Panaro de Moraes Zamith, Esteban Walter Gonzalez Clua, Aura Conci, Anselmo Antunes Montenegro, Paulo A. Pagliosa, Luis Valente	Parallel processing between GPU and CPU: Concepts in a game architecture.	CGIV	2007	DBLP DOI BibTeX RDF	game loop, process distribution, GPGPU
15	Pablo San Segundo, Diego Rodríguez-Losada, Ramón Galán, Fernando Matía, Agustín Jiménez	Exploiting CPU Bit Parallel Operations to Improve Efficiency in Search.	ICTAI (1)	2007	DBLP DOI BibTeX RDF
15	Heinz Stockinger, Marco Pagni, Lorenzo Cerutti, Laurent Falquet	Grid Approach to Embarrassingly Parallel CPU-Intensive Bioinformatics Problems.	e-Science	2006	DBLP DOI BibTeX RDF
15	Hakduran Koc, Suleyman Tosun, Ozcan Ozturk 0001, Mahmut T. Kandemir	Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems.	ISVLSI	2006	DBLP DOI BibTeX RDF
15	Jason Agron, Wesley Peck, Erik K. Anderson, David Andrews 0001, Ed Komp, Ron Sass, Fabrice Baijot, Jim Stevens	Run-Time Services for Hybrid CPU/FPGA Systems on Chip.	RTSS	2006	DBLP DOI BibTeX RDF
15	Satoshi Ohshima, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba	Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment.	VECPAR	2006	DBLP DOI BibTeX RDF
15	Abhijeet Joglekar, Steve R. King	Software iSCSI over iWARP on a General Purpose CPU.	CLUSTER	2006	DBLP DOI BibTeX RDF
15	Daniel Große, Ulrich Kühne, Rolf Drechsler	HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.	MTV	2005	DBLP DOI BibTeX RDF
15	Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya	Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Balaji Raman 0001, Samarjit Chakraborty, Wei Tsang Ooi	Meeting CPU constraints by delaying playout of multimedia tasks.	NOSSDAV	2005	DBLP DOI BibTeX RDF	scheduling multimedia tasks, buffering, playout delay
15	Walter Binder, Jarle Hulaas	A Portable CPU-Management Framework for Java.	IEEE Internet Comput.	2004	DBLP DOI BibTeX RDF
15	David Andrews 0001, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge L. Ortiz, Ed Komp, Peter J. Ashenden	Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link.	IEEE Micro	2004	DBLP DOI BibTeX RDF
15	David Andrews 0001, Douglas Niehaus, Peter J. Ashenden	Programming Models for Hybrid CPU/FPGA Chips.	Computer	2004	DBLP DOI BibTeX RDF
15	Sören Grimm, Stefan Bruckner, Armin Kanitsar, M. Eduard Gröller	Memory Efficient Acceleration Structures and Techniques for CPU-Based Volume Raycasting of Large Data.	VolVis	2004	DBLP DOI BibTeX RDF	volume raycasting, acceleration techniques, large data
15	Alberto Avritzer, Johannes P. Ros, Elaine J. Weyuker	Estimating the CPU utilization of a rule-based system.	WOSP	2004	DBLP DOI BibTeX RDF	software testing, workload characterization, software performance testing
15	Zhao Dong 0001, Wei Chen 0001, Long Zhang 0001, Qunsheng Peng 0001	Balancing CPU and GPU: Real-Time Visualization of Large Scale 3D Scanning Models.	GCC Workshops	2004	DBLP DOI BibTeX RDF
15	Andrea S. Brogna, Franco Bigongiari, Fabrizio Bertuccelli, Walter Errico, Simone Giovannetti, Egidio Pescari, Roberto Saletti	SEU Protected CPU for Slow Control on Space Vehicles.	DELTA	2004	DBLP DOI BibTeX RDF
15	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Fine-Grain Phased Logic CPU.	ISVLSI	2003	DBLP DOI BibTeX RDF
15	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Coarse-Grain Phased Logic CPU.	ASYNC	2003	DBLP DOI BibTeX RDF
15	Chung-Hsing Hsu, Ulrich Kremer	The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction.	PLDI	2003	DBLP DOI BibTeX RDF	dynamic voltage scaling, energy savings
15	Radim Ballner, Pavel Tvrdík	MOOSS: CPU Architecture with Memory Protection and Support for OOP.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
15	Suntae Hwang, Karpjoo Jeong, Eun-Jin Im, Chongwoo Woo, Kwang-Soo Hahn, Moon-hae Kim, Sangsan Lee	An Analysis of Idle CPU Cycles at University Computer Labs.	ICCSA (1)	2003	DBLP DOI BibTeX RDF
15	Kazuo Goda, Takayuki Tamura, Masato Oguchi, Masaru Kitsuregawa	Run-Time Load Balancing System on SAN-connected PC Cluster for Dynamic Injection of CPU and Disk Resource - A Case Study of Data Mining Application.	DEXA	2002	DBLP DOI BibTeX RDF
15	Girish Venkataramani, Suraj Sudhir, Mihai Budiu, Seth Copen Goldstein	Factors Influencing the Performance of a CPU-RFU Hybrid Architecture.	FPL	2002	DBLP DOI BibTeX RDF
15	Goetz Graefe, Per-Åke Larson	B-Tree Indexes and CPU Caches.	ICDE	2001	DBLP DOI BibTeX RDF
15	Christian Poellabauer, Karsten Schwan, Richard West	Coordinated CPU and event scheduling for distributed multimedia applications.	ACM Multimedia	2001	DBLP DOI BibTeX RDF	scheduling, quality of Service, multimedia
15	Kozo Okano, Yuko Kitahama, Akira Kitajima, Teruo Higashino, Kenichi Taniguchi	Formal Verification of CPU in Laboratory Work.	MSE	2001	DBLP DOI BibTeX RDF
15	Charles D. Cranor, R. Gopalakrishnan, Peter Z. Onufryk	Architectural Considerations for CPU and Network Interface Integration.	IEEE Micro	2000	DBLP DOI BibTeX RDF
15	Peter A. Dinda, David R. O'Hallaron	Realistic CPU Workloads through Host Load Trace Playback.	LCR	2000	DBLP DOI BibTeX RDF
15	Sami Khuri, Hsiu-Chin Hsu	Visualizing the CPU scheduler and page replacement algorithms.	SIGCSE	1999	DBLP DOI BibTeX RDF	Java
15	Hao-Hua Chu, Klara Nahrstedt	CPU Service Classes for Multimedia Applications.	ICMCS, Vol. 1	1999	DBLP DOI BibTeX RDF
15	Raju Pandey, Manoj Lal	CPU Resource Control for Mobile Programs.	ASA/MA	1999	DBLP DOI BibTeX RDF
15	Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura	Memory-CPU Size Optimization for Embedded System Designs.	DAC	1997	DBLP DOI BibTeX RDF
15	L. S. Tang	A CPU scheduling simulation from structured programming to object-oriented design.	SIGCSE	1992	DBLP DOI BibTeX RDF	Ada, C++
15	Jim Gray 0001, Gianfranco R. Putzolu	The 5 Minute Rule for Trading Memory for Disk Accesses and The 10 Byte Rule for Trading Memory for CPU Time.	SIGMOD Conference	1987	DBLP DOI BibTeX RDF
15	Hisao Kameda	CPU scheduling for effective multiprogramming.	Operating Systems Engineering	1980	DBLP DOI BibTeX RDF
15	Erik R. Altman	CPUs and GPUs: Who Owns the Future?	IEEE Micro	2011	DBLP DOI BibTeX RDF	performance, field-programmable gate array, GPU, productivity, application-specific integrated circuit, programming model, CPU
15	David M. Brooks	CPUs, GPUs, and Hybrid Computing.	IEEE Micro	2011	DBLP DOI BibTeX RDF	GPU, high-performance computing, CPU, hybrid computing
15	Richard W. Vuduc, Kent Czechowski	What GPU Computing Means for High-End Systems.	IEEE Micro	2011	DBLP DOI BibTeX RDF	system balance, data-intensive processing, GPU, supercomputers, CPU, exascale
15	Siegfried Benkner, Sabri Pllana, Jesper Larsson Träff, Philippas Tsigas, Uwe Dolinsky, Cédric Augonnet, Beverly Bachmayer, Christoph W. Kessler, David Moloney, Vitaly Osipov	PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems.	IEEE Micro	2011	DBLP DOI BibTeX RDF	PEPPHER, GPU, multicore, CPU, hybrid computing
15	Alexander Lenk, Michael Menzel 0002, Johannes Lipsky, Stefan Tai, Philipp Offermann	What Are You Paying For? Performance Benchmarking for Infrastructure-as-a-Service Offerings.	IEEE CLOUD	2011	DBLP DOI BibTeX RDF	Rackspace, Flexiscale, Benchmarking, Cloud Computing, Method, CPU, Infrastructure as a Service, Amazon
15	Stanley Mazor	Intel's 8086.	IEEE Ann. Hist. Comput.	2010	DBLP DOI BibTeX RDF	8086, Pentium, Bill Davidow, Steve Morse, CPU, Intel
15	Pawel Gepner, Michal Filip Kowalik, David L. Fraser, Kazimierz Wackowski	Early Performance Evaluation of New Six-Core Intel® Xeon® 5600 Family Processors for HPC.	ISPDC	2010	DBLP DOI BibTeX RDF	Parallel computing, Hardware, HPC, CPU
15	Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe	SimFlex: Statistical Sampling of Computer System Simulation.	IEEE Micro	2006	DBLP DOI BibTeX RDF	SimFlex, CPU, statistical sampling, SPEC, computer system simulation
15	Rajaa S. Shindi, Shaun Cooper	Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated.	SIGAda	2006	DBLP DOI BibTeX RDF	sim-alpha, cache, cpu, context switches, processor simulators
15	Richard Han 0001	Factoring a Mobile Client's Effective Processing Speeed into the Image Transcoding Decision.	WOWMOM	1999	DBLP DOI BibTeX RDF	image processing, mobile, partitioning, PDA, transcoding, proxy, CPU
15	Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai	A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	CPI, operand cache, object compatibility, performance, pipeline, RISC, superscalar, CPU, OLTP, hardware cost, CISC, mainframe computer, Arithmetic unit
15	Bradford J. Rodriguez	A minimal TTL processor for architecture exploration.	SAC	1994	DBLP DOI BibTeX RDF	education, architecture, processors, CPU