Search results for "Hardware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Felix Schürmann, Steffen G. Hohmann, Johannes Schemmel, Karlheinz Meier	Towards an Artificial Neural Network Framework.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
24	José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Ricardo Tanscheit, Marley M. B. R. Vellasco, Marco Aurélio Cavalcanti Pacheco	Towards Evolvable Analog Fuzzy Logic Controllers.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
24	Derek S. Linden	A System For Evolving Antennas In-Situ.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
24	Gunnar Tufte, Pauline C. Haddow	Evolving an Adaptive Digital Filter.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
24	Gordon Hollingworth, Steve Smith, Andrew M. Tyrrell	Safe Intrinsic Evolution of Virtex Devices.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
24	Jordan B. Pollack, Hod Lipson, Pablo Funes, Sevan G. Ficici, Gregory Hornby	Coevolutionary Robotics.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
24	Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Meng	FeRAM Circuit Technology for System on a Chip.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
24	Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves	The MorphoSys Dynamically Reconfigurable System-on-Chip.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
24	Algirdas Avizienis	The Hundred Year Spacecraft.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
24	Rishiyur S. Nikhil	Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design).	GPCE	2009	DBLP DOI BibTeX RDF	bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
24	Ben I. Hounsell, Tughrul Arslan, Robert Thomson 0003	Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Robust hardware, Finite impulse response filters, Genetic algorithms, Fault tolerant, Programmable logic arrays, PLAs, FIR filters, Evolvable hardware
24	Kris Gaj, Tarek A. El-Ghazawi, Nikitas A. Alexandridis, Jacek R. Radzikowski, Mohamed Taher, Frederic Vroman	Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems.	IPDPS	2003	DBLP DOI BibTeX RDF	distributed hardware resources, Job Management Systems, accelerator boards, FPGA, job scheduling, reconfigurable hardware
24	Eike Grimpe, Frank Oppenheimer	Extending the SystemC synthesis subset by object-oriented features.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	C/C++ based design, object-orientation, high-level synthesis, SystemC, system level design, hardware description language, hardware synthesis
24	Brian Grattan, Greg Stitt, Frank Vahid	Codesign-extended applications.	CODES	2002	DBLP DOI BibTeX RDF	hardware/software cospecification, system-on-a-chip, hardware/software partitioning, platform-based design, configurable logic
24	John R. Budenske, Ranga S. Ramanujan, Howard Jay Siegel	On-line use of off-line derived mappings for iterative automatic target recognition tasks and a particular class of hardware platforms.	Heterogeneous Computing Workshop	1997	DBLP DOI BibTeX RDF	online use, offline derived mappings, iterative automatic target recognition tasks, real-time on-line input-data dependent remappings, heterogeneous hardware platform, operating system, program verification, heterogeneous computing, application domain, hardware platforms
24	P. Bosch, A. Carloganu, Daniel Etiemble	Complete x86 instruction trace generation from hardware bus collect.	EUROMICRO	1997	DBLP DOI BibTeX RDF	complete x86 instruction trace generation, hardware bus collect, architectural improvements, benchmark traces, hardware/software approach, x86 execution traces, commercial analyzer, computer architecture, microprocessors, memory hierarchies, trace driven simulation, performance data
24	Reinhard Rauscher, Dieter Klawan, Hans-Jürgen Bandelt	Results Given by a New Evaluation System for Placement and Routing Heuristics.	EUROMICRO	1996	DBLP DOI BibTeX RDF	routing heuristics, placement heuristics, minimal hardware requirements, fabrication processes, algorithm development, VLSI, programming languages, VLSI layouts, evaluation system, hardware platforms
24	Jay K. Adams, Donald E. Thomas	Multiple-process behavioral synthesis for mixed hardware-software systems.	ISSS	1995	DBLP DOI BibTeX RDF	automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis
24	Raj S. Mitra, Mahmood G. Qadir, Anupam Basu	A consistent labeling approach to hardware software partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	consistent labeling problem, implementation sets, real-time systems, heuristics, CAD, CAD, computer aided software engineering, hardware/software codesign, hardware/software partitioning, embedded systems design, combinatorial problem, combinatorial mathematics
24	Michael Deering, David Naegle	The SAGE graphics architecture.	ACM Trans. Graph.	2002	DBLP DOI BibTeX RDF	video, graphics hardware, anti-aliasing, graphics systems, rendering hardware, hardware systems, frame buffer algorithms
24	Ken Perlin, Salvatore Paxia, Joel S. Kollin	An autostereoscopic display.	SIGGRAPH	2000	DBLP DOI BibTeX RDF	virtual reality, graphics hardware, object tracking, optics, hardware systems, user interface hardware
23	Guido Arnout	C for System Level Design.	DATE	1999	DBLP DOI BibTeX RDF
23	Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam	Relax: an architectural framework for software recovery of hardware faults.	ISCA	2010	DBLP DOI BibTeX RDF	software recovery, reliability
23	Ildar Z. Batyrshin, Antonio Hernández Zavala, Oscar Camacho Nieto, Luis A. Villa Vargas	Generalized Fuzzy Operations for Digital Hardware Implementation.	MICAI	2007	DBLP DOI BibTeX RDF	Fuzzy system, digital system, conjunction, disjunction
23	Pao-Ann Hsiung, Chih-Wen Liu	Exploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems.	FPL	2007	DBLP DOI BibTeX RDF
23	Wei Wang, Qiang Wu, Wei Xie	Hardware-Software Co-design for Dynamic Reconfigurable Computing with Collaborative Supports of Architecture and Operating System.	CSCWD	2007	DBLP DOI BibTeX RDF
23	Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
23	Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser E. Alexander	Automated Design Space Exploration for DSP Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	VLSI, Synthesis, Throughput, DSP, RTL, FIR filter, Hardware design, Power dissipation, Area
23	Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan	Dynamic FPGA routing for just-in-time FPGA compilation.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
23	Ted Huffmire, Jonathan Valamehr, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine	Trustworthy System Security through 3-D Integrated Hardware.	HOST	2008	DBLP DOI BibTeX RDF
23	Wenjian Luo, Xin Wang, Ying Tan 0002, Yiguo Zhang, Xufa Wang	An Adaptive Self-tolerant Algorithm for Hardware Immune System.	ICES	2005	DBLP DOI BibTeX RDF
23	Jesper Grode, Peter Voigt Knudsen, Jan Madsen	Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System.	DATE	1998	DBLP DOI BibTeX RDF	Cosynthesis, LYCOS System, Resource Allocation, HW/SW Partitioning
23	Mikhail J. Atallah, Eric Bryant, John T. Korb, John R. Rice	Binding software to specific native hardware in a VM environment: the puf challenge and opportunity.	VMSec	2008	DBLP DOI BibTeX RDF	anti-tamper, binding software to hardware, virtualization, software protection, physically unclonable functions
23	Alexander Klimm, Oliver Sander, Jürgen Becker 0001, Sylvain Subileau	A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.	ARCS	2008	DBLP DOI BibTeX RDF	Hyperelliptic Curve Cryptography (HECC), FPGA, embedded systems, Public Key Cryptography (PKC), reconfigurable hardware
23	J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw	Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	Anton, simulation, embedded software, special-purpose hardware
23	Sesh Commuri, Viswanath Tadigotla, L. Sliger	Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs.	J. Intell. Robotic Syst.	2007	DBLP DOI BibTeX RDF	autonomous ground vehicles, fault-tolerance, FPGA, intelligent robots, hardware reconfiguration
23	Quanxi Li, Jingsong He	A Sophisticated Architecture for Evolutionary Multiobjective Optimization Utilizing High Performance DSP.	ICES	2007	DBLP DOI BibTeX RDF	Evolvable Hardware, Digital Signal Processor, Evolutionary Multi-objective Optimization
23	Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha	HybDTM: a coordinated hardware-software approach for dynamic thermal management.	DAC	2006	DBLP DOI BibTeX RDF	hybrid hardware-software management, thermal model, dynamic thermal management
23	Youfeng Wu, Yong-Fong Lee	Hardware-Software Collaborative Techniques for Runtime Profiling and Phase Transition Detection.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	runtime profiling, phase transition detection, hardware-software collaboration, dynamic optimizations
23	Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Cheng-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, Tihao Chiang	A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	advanced video coding (AVC), joint video team (JVT), software-hardware co-implementation, MB level pipelining, H.264, MPEG-4, task partition
23	Jifeng He 0001, Dang Van Hung, Geguang Pu, Zongyan Qiu, Wang Yi 0001	Exploring optimal solution to hardware/software partitioning for synchronous model.	Formal Aspects Comput.	2005	DBLP DOI BibTeX RDF	Timed automata, Scheduling algorithm, Reachability, Hardware/software partitioning
23	Yuan-Hsiu Chen, Pao-Ann Hsiung	Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC.	EUC	2005	DBLP DOI BibTeX RDF	Operating System for Reconfigurable SoC, Hardware Scheduling, Placement, Dynamic Partial Reconfiguration
23	Roman L. Lysecky, Frank Vahid	A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning.	DATE	2004	DBLP DOI BibTeX RDF	FPGA fabric, self-improving chips, synthesis, reconfigurable computing, dynamic optimization, system-on-a-chip, platforms, codesign, Hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
23	Jorji Nonaka, Nobuyuki Kukimoto, Naohisa Sakamoto, Hiroshi Hazama, Yasuhiro Watashiba, Xuezhen Liu, Masato Ogata, Masanori Kanazawa, Koji Koyamada	Hybrid Hardware-Accelerated Image Composition for Sort-Last Parallel Rendering on Graphics Clusters with Commodity Image Compositor.	VolVis	2004	DBLP DOI BibTeX RDF	Sort-Last, Hardware-Assisted, Cluster Computing, Parallel Rendering, Image Compositing
23	Geguang Pu, Dang Van Hung, Jifeng He 0001, Wang Yi 0001	An Optimal Approach to Hardware/Software Partitioning for Synchronous Model.	IFM	2004	DBLP DOI BibTeX RDF	timed automata, scheduling algorithm, reachability, Hardware/software partitioning
23	John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, David Lim	Automated tools to implement and test Internet systems in reconfigurable hardware.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF	network intrusion detection and prevention, Internet, Field Programmable Gate Array (FPGA), networks, tools, firewall, reconfigurable hardware
23	Sebastian Lange, Udo Kebschull	Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems.	DATE	2003	DBLP DOI BibTeX RDF	Virtual Hardware Machine, Byte Code, FPGA
23	Smita Bakshi, Daniel Gajski	A Scheduling and Pipelining Algorithm for Hardware/Software Systems.	ISSS	1997	DBLP DOI BibTeX RDF	throughput-constrained, scheduling, pipelining, high-performance, Hardware/software codesign
23	Rachid Helaihel, Kunle Olukotun	Java as a specification language for hardware-software systems.	ICCAD	1997	DBLP DOI BibTeX RDF	java, Java, specification languages, hardware-software co-design
22	Patrick Schaumont, Doris Ching, Ingrid Verbauwhede	An interactive codesign environment for domain-specific coprocessors.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	hardware description language, hardware-software codesign, Cosimulation
22	Sharon Barner, Shoham Ben-David, Anna Gringauze, Baruch Sterin, Yaron Wolfsthal	An Algorithmic Approach to Design Exploration.	FME	2002	DBLP DOI BibTeX RDF	hardware debugging, hardware exploration, Model checking
22	Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez	Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.	CHES	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, FPGA, elliptic curve, hardware accelerator, Tate pairing, finite field arithmetic, ? T pairing
22	Stanislaw Deniziak, Adam Gorski	Hardware/Software Co-synthesis of Distributed Embedded Systems Using Genetic Programming.	ICES	2008	DBLP DOI BibTeX RDF	Genetic programming, hardware/software co-design
22	Stephen L. Smith 0002, Andrew J. Greensted, Jon Timmis	Hardware Acceleration of an Immune Network Inspired Evolutionary Algorithm for Medical Diagnosis.	ICES	2008	DBLP DOI BibTeX RDF	Parkinson’s disease, Evolutionary algorithm, Artificial immune systems, Hardware acceleration, Immune networks
22	Rui Yao, Youren Wang, Sheng-lin Yu, Guijun Gao	Research on the Online Evaluation Approach for the Digital Evolvable Hardware.	ICES	2007	DBLP DOI BibTeX RDF	online evolution, digital circuit, Evolvable hardware, incremental evaluation
22	Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth	Hardware/software partitioning of software binaries: a case study of H.264 decode.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	FPGA, embedded systems, synthesis, H.264, hardware/software partitioning, binaries
22	Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke	SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers.	CHES	2005	DBLP DOI BibTeX RDF	GNFS, lattice sieving, RSA 1024 bit, Integer factorization, special hardware
22	Radu Muresan, Catherine H. Gebotys	Current flattening in software and hardware for security applications.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	current flattening, hardware architecture, power analysis attacks
22	Hyunok Oh, Soonhoi Ha	Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints.	CODES	2002	DBLP DOI BibTeX RDF	hardware-software cosynthesis, multi-task, multi-mode
22	Alberto Allara, S. Filipponi, Fabio Salice, William Fornaciari, Donatella Sciuto	A Flexible Model for Evaluating the Behavior of Hardware/Software Systems.	CODES	1997	DBLP DOI BibTeX RDF	hardware-software co-simulation, embedded system design
22	Fred Rose, Todd Carpenter, Sanjaya Kumar, John Shackleton, Todd Steeves Honeywell	A Model for the Coanalysis of Hardware and Software Architectures.	CODES	1996	DBLP DOI BibTeX RDF	RASSP, performance modeling, VHDL, hardware/software codesign
22	Michael Sheliga, Nelson L. Passos, Edwin Hsing-Mean Sha	Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications.	CODES	1996	DBLP DOI BibTeX RDF	Multi-Dimensional Systems, High Level Synthesis, Hardware/Software Codesign
22	Markus Voss, Tarek Ben Ismail, Ahmed Amine Jerraya, Karl-Heinz Kapp	Towards a theory for hardware/software codesign.	CODES	1994	DBLP DOI BibTeX RDF	Design Process, System-Level Design, Hardware/Software Codesign, Design Theory
22	Markus Grimmer	Extending the Range of C-XSC: Some Tools and Applications for the Use in Parallel and Other Environments.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	C-XSC, Verified Linear System Solver, MPI, Maple, Interval Arithmetic, Integral Equations, Parallel Environment
22	Carlos D. Correa, Deborah Silver	Programmable shaders for deformation rendering.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
22	Alan Heirich	Optimal automatic multi-pass shader partitioning by dynamic programming.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
22	Daniel Wexler, Larry Gritz, Eric Enderton, Jonathan Rice	GPU-accelerated high-quality hidden surface removal.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
22	Justin Hensley, Montek Singh, Anselmo Lastra	A fast, energy-efficient z-comparator.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
22	James M. Hereford, Tüze Kuyucu	Robust Neural Networks Using Motes.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Leone Pereira Masiero, Marco Aurélio Cavalcanti Pacheco, Carlos R. Hall Barbosa, Cristina Costa Santini	Molecular Circuit Design.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Shuguang Zhao, Jianxun Zhao, Licheng Jiao	Adaptive Genetic Algorithm Based Approach for Evolutionary Design and Multi-objective Optimization of Logic Circuits.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Shuguang Zhao, Licheng Jiao, Jianxun Zhao, Yuping Wang 0003	Evolutionary Design of Analog Circuits with a Uniform-Design Based Multi-Objective Adaptive Genetic Algorithm.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Edward Ramsden, Garrison W. Greenwood, David Hunter	EARP-1 - An Evolvable Analog Research Platform.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Shivakumar Viswanathan, Jordan B. Pollack	On the Robustness Achievable with Stochastic Development Processes.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Lukás Sekanina, Ricardo Salem Zebulum	Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Garrison W. Greenwood	Practical Concerns When Evolving Circuits Impervious to Anticipated Faults.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Richard Terrile, Hrand Aghazarian, Michael I. Ferguson, Wolfgang Fink, Terrance L. Huntsberger, Didier Keymeulen, Gerhard Klimeck, Mark A. Kordon, Seungwon Lee, Paul von Allmen	Evolutionary Computation Technologies for the Automated Design of Space Systems.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Mikhail Prokopenko, Peter Wang, Don Price	Complexity Metrics for Self-monitoring Impact Sensing Networks.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Morten Hartmann, Per Kristian Lehre, Pauline C. Haddow	Evolved Digital Circuits and Genome Complexity.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert, N. Lipnitsakya, Y. Yatskevich	On Evolution of Relatively Large Combinational Logic Circuits.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Jorge Luís Machado do Amaral, José Franco Machado do Amaral, Ricardo Tanscheit, Marco Aurélio Cavalcanti Pacheco, Antonio Carneiro de Mesquita Filho	Tuning Evolvable PID Controllers through a Clonal Selection Algorithm.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Gianluca Tempesti, Pierre-André Mudry, Ralph Hoffmann	A Move Processor for Bio-Inspired Systems.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
22	Peter Kipfer, Mark Segal, Rüdiger Westermann	UberFlow: a GPU-based particle engine.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
22	Pradeep Sen	Silhouette maps for improved texture magnification.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
22	Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron	A flexible simulation framework for graphics architectures.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
22	Kayvon Fatahalian, Jeremy Sugerman, Pat Hanrahan	Understanding the efficiency of GPU algorithms for matrix-matrix multiplication.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
22	José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Ricardo Tanscheit, Marley M. B. R. Vellasco, Marco Aurélio Cavalcanti Pacheco	Towards Evolvable Analog Artificial Neural Networks Controllers.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	A. P. Shanthi, P. Muruganandam, Ranjani Parthasarathi	Enhancing the Development Based Evolution of Digital Circuits.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, Martin Trefzer	Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Michael L. Harrison, James A. Foster	Improving the Survivability of a Simple Evolved Circuit through Co-evolution.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Felix Streichert, Christian Spieth, Holger Ulmer, Andreas Zell	How to Evolve the Head-Tail Pattern from Reaction-Diffusion Systems.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho	Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Lukás Sekanina, Stepan Friedl	On Routine Implementation of Virtual Evolvable Devices Using COMBO6.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Urs Kanus, Gregor Wetekam, Johannes Hirche	VoxelCache: a cache-based memory architecture for volume graphics.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
22	Nathan A. Carr, Jesse D. Hall, John C. Hart	GPU algorithms for radiosity and subsurface scattering.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
22	Kenneth Moreland, Edward Angel	The FFT on a GPU.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
22	Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong, Xin Guo 0002, Michael I. Ferguson, Adrian Stoica	Experimental Results in Evolutionary Fault-Recovery for Field Programmable.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
22	André Stauffer, Moshe Sipper	Data and Signals: A New Kind of Cellular Automaton for Growing Systems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
22	Jason D. Lohn, Derek S. Linden, Gregory Hornby, William F. Kraus, Adaan Rodriguez-Arroyo	Evolutionary Design of an X-Band Antenna for NASA's Space Technology 5 Mission.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
22	Lirong Tian, Tughrul Arslan	An Evolutionary Power Management Algorithm for SoC Based EHWSystems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF