Search results for "VLIW"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
23	Minjoong Rim, Rajiv Jain	Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	super-scalar, loop compilation, High-level synthesis, VLIW, loop transformations, loop optimization, pipeline scheduling
23	Jian Wang, Guang R. Gao	Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops.	CC	1996	DBLP DOI BibTeX RDF	Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism
23	Toshio Nakatani, Kemal Ebcioglu	Making Compaction-Based Parallelization Affordable.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc
18	Mei Wen, Nan Wu 0003, Maolin Guan, Chunyuan Zhang	Load scheduling: Reducing pressure on distributed register files for free.	ASP-DAC	2008	DBLP DOI BibTeX RDF
18	Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu	Improving datapathutilization of programmable DSP with composite functional units.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu	Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes.	ASP-DAC	2007	DBLP DOI BibTeX RDF
18	Micha Nelissen, Kees van Berkel 0001, Sergei Sawitzki	Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance.	FPL	2007	DBLP DOI BibTeX RDF
18	Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan	Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems.	IPDPS	2007	DBLP DOI BibTeX RDF
18	Hyojin Choi, Wonchul Lee, Wonyong Sung	Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Ashish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia	JouleQuest: An Accurate Power Model for the StarCore DSP Platform.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley	Merging Head and Tail Duplication for Convergent Hyperblock Formation.	MICRO	2006	DBLP DOI BibTeX RDF
18	Hai-Chen Wang, Chung-Kwong Yuen	Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor.	IPDPS	2006	DBLP DOI BibTeX RDF
18	Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo	Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications.	ICME	2006	DBLP DOI BibTeX RDF
18	Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001	Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck	L0 Cluster Synthesis and Operation Shuffling.	PATMOS	2004	DBLP DOI BibTeX RDF
18	Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek	Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.	FPL	2004	DBLP DOI BibTeX RDF
18	Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich	A 800 MHz System-on-Chip for Wireless Infrastructure Applications.	VLSI Design	2004	DBLP DOI BibTeX RDF
18	Bogong Su, Jian Wang 0046, Erh-Wen Hu, Joseph B. Manzano	Software De-Pipelining Technique.	SCAM	2004	DBLP DOI BibTeX RDF
18	Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das	Evaluating the Imagine Stream Architecture.	ISCA	2004	DBLP DOI BibTeX RDF
18	Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel	Instruction Set Emulation for Rapid Prototyping of SoCs .	DATE	2003	DBLP DOI BibTeX RDF
18	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing
18	Norbert A. Pilz, Kenneth Adamson	Code Optimization Techniques of Data-Intensive Tasks onto Statically Scheduled Architectures: Optimal Performance on the TigerSharc.	PARA	2002	DBLP DOI BibTeX RDF
18	Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch	Hardware/Software Trade-Offs for Advanced 3G Channel Coding.	DATE	2002	DBLP DOI BibTeX RDF
18	Walter Lee, Diego Puppin, Shane Swenson, Saman P. Amarasinghe	Convergent scheduling.	MICRO	2002	DBLP DOI BibTeX RDF
18	Weiping Liao, Joseph M. Basile, Lei He 0001	Leakage power modeling and reduction with data retention.	ICCAD	2002	DBLP DOI BibTeX RDF
18	Zhining Huang, Sharad Malik	Exploiting operation level parallelism through dynamically reconfigurable datapaths.	DAC	2002	DBLP DOI BibTeX RDF
18	Jan Hoogerbrugge, Lex Augusteijn	Pipelined Java Virtual Machine Interpreters.	CC	2000	DBLP DOI BibTeX RDF
18	Bruce Schulman, Gerald G. Pechanek	A 90k Gate "CLB" for Parallel Distributed Computing.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
18	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-based register coalescing.	ICS	2000	DBLP DOI BibTeX RDF
18	Mark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong	Reducing Cost and Tolerating Defects in Page-based Intelligent Memory.	ICCD	2000	DBLP DOI BibTeX RDF
18	Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham	Distributed Modulo Scheduling.	HPCA	1999	DBLP DOI BibTeX RDF
18	Gerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans	TriMedia CPU64 Design Space Exploration.	ICCD	1999	DBLP DOI BibTeX RDF
18	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Han-Saem Yun	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	LCPC	1999	DBLP DOI BibTeX RDF
18	Sung-Soo Lim, Jihong Kim 0001, Sang Lyul Min	A Worst Case Timing Analysis Technique for Optimized Programs.	RTCSA	1998	DBLP DOI BibTeX RDF	real-time systems, compiler optimization, worst case execution time
18	Ravi Nair, Martin E. Hopkins	Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups.	ISCA	1997	DBLP DOI BibTeX RDF
18	Mark G. Stoodley, Corinna G. Lee	Software Pipelining Loops with Conditional Branches.	MICRO	1996	DBLP DOI BibTeX RDF
18	Adrian Slowik, Georg Piepenbrock, Peter Pfahler	Compiling Nested Loops for Limited Connectivity VLIWs.	CC	1994	DBLP DOI BibTeX RDF
18	Gabriel M. Silberman, Kemal Ebcioglu	An architectural framework for migration from CISC to higher performance platforms.	ICS	1992	DBLP DOI BibTeX RDF
18	James C. Dehnert, Peter Y.-T. Hsu, Joseph P. Bratt	Overlapped Loop Support in the Cydra 5.	ASPLOS	1989	DBLP DOI BibTeX RDF	Cydra 5
18	David M. Lewis	A Programmable Hardware Accelerator for Compiled Electrical Simulation.	DAC	1988	DBLP BibTeX RDF
16	Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury	30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.	ISSCC	2024	DBLP DOI BibTeX RDF
16	Lucas Ferreira, Steffen Malkowsky, Patrik Persson, Sven Karlsson, Kalle Åström, Liang Liu 0002	Design of an Application-specific VLIW Vector Processor for ORB Feature Extraction.	J. Signal Process. Syst.	2023	DBLP DOI BibTeX RDF
16	Hao Yu, Jun Wu, Haoqi Ren, Zhifeng Zhang, Bin Tan	An Efficient and Secure Inline Assembly Design for VLIW DSP.	ICCT	2023	DBLP DOI BibTeX RDF
16	Xin Xiao, Zhong Liu	ISADL: An Instruction Set Architecture Description Language for VLIW.	ICPADS	2023	DBLP DOI BibTeX RDF
16	Xin Xiao, Zhong Liu	An Adaptive Instruction Set Encoding Automatic Generation Method for VLIW.	ICA3PP (1)	2023	DBLP DOI BibTeX RDF
16	Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini	Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
16	Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys	Dynamic fault-tolerant VLIW processor with heterogeneous Function Units.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
16	Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen	Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling.	ASP-DAC	2022	DBLP DOI BibTeX RDF
16	Chia-Heng Hu, I-Hao Tseng, Pei-Hsuan Kuo, Juinn-Dar Huang	An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability.	AICAS	2022	DBLP DOI BibTeX RDF
16	Ashish Shrivastava, Alan Gatherer, Tong Sun, Sushma Wokhlu, Alex Chandra	SLAP: A Split Latency Adaptive VLIW pipeline architecture which enables on-the-fly variable SIMD vector-length.	CoRR	2021	DBLP BibTeX RDF
16	Ashish Shrivastava, Alan Gatherer, Tong Sun, Sushma Wokhlu, Alex Chandra	SLAP: a Split Latency Adaptive VLIW Pipeline Architecture Which Enables on-The-Fly Variable SIMD Vector-Length.	ICASSP	2021	DBLP DOI BibTeX RDF
16	Aiqing Wu, Mengni Bie, Longmei Nan, Wei Li 0131	Effective Register Allocation for Configurable VLIW Crypto-Processor.	ASICON	2021	DBLP DOI BibTeX RDF
16	Cyril Six	Compilation optimisante et formellement prouvée pour un processeur VLIW.		2021	RDF
16	Cyril Six, Sylvain Boulmé, David Monniaux	Certified and efficient instruction scheduling: application to interlocked VLIW processors.	Proc. ACM Program. Lang.	2020	DBLP DOI BibTeX RDF
16	Gongli Li, Yingying Hou, Junzhe Zhu	An Efficient and Fast VLIW Compression Scheme for Stream Processor.	IEEE Access	2020	DBLP DOI BibTeX RDF
16	Mohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini	Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
16	Florian Giesemann, Lukas Gerlach 0001, Guillermo Payá Vayá	Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers.	J. Signal Process. Syst.	2020	DBLP DOI BibTeX RDF
16	David Uzan, Roger Kahn, Shlomo Weiss	Perceptron based filtering of futile prefetches in embedded VLIW DSPs.	J. Syst. Archit.	2020	DBLP DOI BibTeX RDF
16	Rama Venkatasubramanian, Don Steiss, Greg Shurtz, Tim Anderson, Kai Chirca, Raghavendra Santhanagopal, Niraj Nandan, Anish Reghunath, Hetul Sanghvi, Daniel Wu, Abhijeet Chachad, Brian Karguth, Denis Beaudoin, Charles Fuoco, Lewis Nardini, Chunhua Hu, Sam Visalli, Amrit Mundra, Devanathan Varadarajan, Frank Cano, Shane Stelmach, Mihir Mody, Arthur Redfern, Haydar Bilhan, Maher Sarraj, Ali Siddiki, Anthony Lell, Eldad Falik, Anthony M. Hill, Abhinay Armstrong, Todd Beck, Vijay Kanumuri, Steven Mullinnix, Darnell Moore, Jason Jones, Manoj Koul, Sanjive Agarwala	2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration.	ISSCC	2020	DBLP DOI BibTeX RDF
16	Adrian Florea, Teodora Vasilas	Optimizing the Integration Area and Performance of VLIW Architectures by Hardware/Software Co-design.	MDIS	2020	DBLP DOI BibTeX RDF
16	Lukas Gerlach 0001, Fabian Stuckmann, Holger Blume, Guillermo Payá Vayá	Issue-Slot Based Predication Encoding Technique for VLIW Processors.	MOCAST	2020	DBLP DOI BibTeX RDF
16	Ricardo S. Ferreira 0001, Cristoferson Bueno, Marcone Laure, Monica Magalhães Pereira, Luigi Carro	A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.	Trans. High Perform. Embed. Archit. Compil.	2019	DBLP DOI BibTeX RDF
16	Sensen Hu, Jing Huang	Exploring Adaptive Cache for Reconfigurable VLIW Processor.	IEEE Access	2019	DBLP DOI BibTeX RDF
16	Yumin Hou, Xu Wang, Jiawei Fu, Junping Ma, Hu He 0001, Xu Yang 0003	Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
16	Simon Rokicki, Erven Rohou, Steven Derrien	Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
16	Elena Limonova, N. A. Bocharov, N. B. Paramonov, D. S. Bogdanov, Vladimir V. Arlazarov, O. A. Slavin, Dmitry P. Nikolaev	Performance Evaluation of a Recognition System on the VLIW Architecture by the Example of the Elbrus Platform.	Program. Comput. Softw.	2019	DBLP DOI BibTeX RDF
16	Keni Qiu, Yujie Zhu, Yuanchao Xu 0002, Qirun Huo, Chun Jason Xue	BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
16	Binbin Liu, Qilong Zheng	Realize special instructions on clustering VLIW DSP: multiplication-accumulation instruction.	CoRR	2019	DBLP BibTeX RDF
16	Andreas Bytyn, Rainer Leupers, Gerd Ascheid	An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration.	CoRR	2019	DBLP BibTeX RDF
16	Paras Jain 0001, Xiangxi Mo, Ajay Jain, Alexey Tumanov, Joseph E. Gonzalez, Ion Stoica	The OoO VLIW JIT Compiler for GPU Inference.	CoRR	2019	DBLP BibTeX RDF
16	Xuesong Su, Hui Wu 0001, Jingling Xue	WCET-aware hyper-block construction for clustered VLIW processors.	LCTES	2019	DBLP DOI BibTeX RDF
16	Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys	Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units.	DATE	2019	DBLP DOI BibTeX RDF
16	Andreas Bytyn, Rainer Leupers, Gerd Ascheid	An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration.	ISCAS	2019	DBLP DOI BibTeX RDF
16	Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys, Emmanuel Casseau	Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors.	DASIP	2019	DBLP DOI BibTeX RDF
16	Dilshan Kumarathunga, Omega Gamage, Asitha Samarasinghe, Nipuna Saranga, Ranga Rodrigo, Ajith A. Pasqual	VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing.	ASAP	2019	DBLP DOI BibTeX RDF
16	Anderson Luiz Sartor, Pedro Henrique Exenberger Becker, Joost Hoozemans, Stephan Wong, Antonio C. S. Beck	Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW Processor.	IEEE Trans. Multi Scale Comput. Syst.	2018	DBLP DOI BibTeX RDF
16	Hong Ye, Naijie Gu, Xiaoci Zhang, Chuanwen Lin	Design and implementation of a conflict-free memory accessing technique for FFT on multicluster VLIW DSP.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
16	Joost Hoozemans, Jeroen van Straten, Stephan Wong	Increasing resource utilization in mixed-criticality systems using a polymorphic VLIW processor.	J. Syst. Archit.	2018	DBLP DOI BibTeX RDF
16	Elena Limonova, Natalya Skoryukina, Murad I. Neiman-zade	Fast Hamming distance computation for 2D art recognition on VLIW-architecture in case of Elbrus platform.	ICMV	2018	DBLP DOI BibTeX RDF
16	Marco Spaziani Brunella, Salvatore Pontarelli, Marco Bonola, Giuseppe Bianchi 0001	V- PMP: A VLIW Packet Manipulator Processor.	EuCNC	2018	DBLP DOI BibTeX RDF
16	Guillermo Talavera, Antoni Portero, Francky Catthoor	Impact of Address Generation on Multimedia Embedded VLIW Processors.	CISIM	2018	DBLP DOI BibTeX RDF
16	Anderson Luiz Sartor, Arthur Francisco Lorenzon, Sandip Kundu, Israel Koren, Antonio C. S. Beck	Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance.	CF	2018	DBLP DOI BibTeX RDF
16	Vladimir V. Stegailov, Alexey Timofeev	Deploying Elbrus VLIW CPU Ecosystem for Materials Science Calculations: Performance and Problems.	RuSCDays	2018	DBLP DOI BibTeX RDF
16	Miroslav N. Velev	Survey of Techniques for Efficient Solving of Boolean Formulas from Formal Verification of Pipelined, Superscalar, and VLIW Microprocessors at a High Level of Abstraction.	ISAIM	2018	DBLP BibTeX RDF
16	Joost Hoozemans	Targeting static and dynamic workloads with a reconfigurable VLIW processor.		2018	RDF
16	Xuesong Su	WCET-aware compilation techniques for clustered VLIW processors.		2018	RDF
16	Renan Augusto Starke, Andreu Carminati, Rômulo Silva de Oliveira	Evaluation of a low overhead predication system for a deterministic VLIW architecture targeting real-time applications.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
16	Roel Jordans, Lech Józwiak, Henk Corporaal, Rosilde Corvino	Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
16	Jingchuan Dong, Taiyong Wang, Bo Li, Zhe Liu, Zhiqiang Yu	An FPGA-based low-cost VLIW floating-point processor for CNC applications.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
16	Mohamed Najoui, Mounir Bahtat, Anas Hatim, Said Belkouch, Noureddine Chabini	VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
16	Luc Michel, Frédéric Pétrot	Dynamic Binary Translation of VLIW Codes on Scalar Architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
16	Xuesong Su, Hui Wu 0001, Jingling Xue	An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors.	ACM Trans. Embed. Comput. Syst.	2017	DBLP DOI BibTeX RDF
16	Jukka Teittinen, Markus Hiienkari, Indre Zliobaite, Jaakko Hollmén, Heikki Berg, Juha Heiskala, Timo Viitanen, Jesse Simonsson, Lauri Koskinen	A 5.3 pJ/op approximate TTA VLIW tailored for machine learning.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
16	Hu He 0001, Xu Yang 0003, Yanjun Zhang	On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage.	Comput. J.	2017	DBLP DOI BibTeX RDF
16	Paolo Meloni, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo	Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs.	J. Syst. Archit.	2017	DBLP DOI BibTeX RDF
16	Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys	NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Debjyoti Bhattacharjee, Rajeswari Devadoss, Anupam Chattopadhyay	ReVAMP: ReRAM based VLIW architecture for in-memory computing.	DATE	2017	DBLP DOI BibTeX RDF
16	Omayma Matoussi, Frédéric Pétrot	Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation.	DATE	2017	DBLP DOI BibTeX RDF
16	Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich	Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors.	MCSoC	2017	DBLP DOI BibTeX RDF