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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 908 occurrences of 401 keywords
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Results
Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Michael J. Flynn |
What's ahead in computer design? ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 4-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size |
23 | Minjoong Rim, Rajiv Jain |
Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(4), pp. 399-410, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
super-scalar, loop compilation, High-level synthesis, VLIW, loop transformations, loop optimization, pipeline scheduling |
23 | Jian Wang, Guang R. Gao |
Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 1-17, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism |
23 | Toshio Nakatani, Kemal Ebcioglu |
Making Compaction-Based Parallelization Affordable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(9), pp. 1014-1029, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc |
18 | Mei Wen, Nan Wu 0003, Maolin Guan, Chunyuan Zhang |
Load scheduling: Reducing pressure on distributed register files for free. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 340-345, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu |
Improving datapathutilization of programmable DSP with composite functional units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3438-3441, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu |
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 110-111, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Micha Nelissen, Kees van Berkel 0001, Sergei Sawitzki |
Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 521-524, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan |
Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-7, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Hyojin Choi, Wonchul Lee, Wonyong Sung |
Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2898-2901, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Ashish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia |
JouleQuest: An Accurate Power Model for the StarCore DSP Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 521-526, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley |
Merging Head and Tail Duplication for Convergent Hyperblock Formation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 65-76, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Hai-Chen Wang, Chung-Kwong Yuen |
Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo |
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, ICME 2006, July 9-12 2006, Toronto, Ontario, Canada, pp. 25-28, 2006, IEEE Computer Society, 1-4244-0367-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 |
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck |
L0 Cluster Synthesis and Operation Shuffling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 311-321, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek |
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 781-790, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich |
A 800 MHz System-on-Chip for Wireless Infrastructure Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 381-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Bogong Su, Jian Wang 0046, Erh-Wen Hu, Joseph B. Manzano |
Software De-Pipelining Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCAM ![In: 4th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2004), 15-16 September 2004, Chicago, IL, USA, pp. 7-16, 2004, IEEE Computer Society, 0-7695-2144-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das |
Evaluating the Imagine Stream Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 14-25, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel |
Instruction Set Emulation for Rapid Prototyping of SoCs . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10562-10569, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu |
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(9), pp. 977-994, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing |
18 | Norbert A. Pilz, Kenneth Adamson |
Code Optimization Techniques of Data-Intensive Tasks onto Statically Scheduled Architectures: Optimal Performance on the TigerSharc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing Advanced Scientific Computing, 6th International Conference, PARA 2002, Espoo, Finland, June 15-18, 2002, Proceedings, pp. 172-184, 2002, Springer, 3-540-43786-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch |
Hardware/Software Trade-Offs for Advanced 3G Channel Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 396-401, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Walter Lee, Diego Puppin, Shane Swenson, Saman P. Amarasinghe |
Convergent scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 111-122, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Weiping Liao, Joseph M. Basile, Lei He 0001 |
Leakage power modeling and reduction with data retention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 714-719, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Zhining Huang, Sharad Malik |
Exploiting operation level parallelism through dynamically reconfigurable datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 337-342, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Jan Hoogerbrugge, Lex Augusteijn |
Pipelined Java Virtual Machine Interpreters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 9th International Conference, CC 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 35-49, 2000, Springer, 3-540-67263-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Bruce Schulman, Gerald G. Pechanek |
A 90k Gate "CLB" for Parallel Distributed Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 831-838, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu |
Unroll-based register coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 296-305, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Mark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong |
Reducing Cost and Tolerating Defects in Page-based Intelligent Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 276-284, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham |
Distributed Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 130-134, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Gerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans |
TriMedia CPU64 Design Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 599-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Han-Saem Yun |
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 12th International Workshop, LCPC'99, La Jolla/San Diego, CA, USA, August 4-6, 1999, Proceedings, pp. 85-99, 1999, Springer, 3-540-67858-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Sung-Soo Lim, Jihong Kim 0001, Sang Lyul Min |
A Worst Case Timing Analysis Technique for Optimized Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 5th International Workshop on Real-Time Computing Systems and Applications (RTCSA '98), 27-29 October 1998, Hiroshima, Japan, pp. 151-157, 1998, IEEE Computer Society, 0-8186-9209-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
real-time systems, compiler optimization, worst case execution time |
18 | Ravi Nair, Martin E. Hopkins |
Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 13-25, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Mark G. Stoodley, Corinna G. Lee |
Software Pipelining Loops with Conditional Branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 262-273, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Adrian Slowik, Georg Piepenbrock, Peter Pfahler |
Compiling Nested Loops for Limited Connectivity VLIWs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 5th International Conference, CC'94, Edinburgh, UK, April 7-9, 1994, Proceedings, pp. 143-157, 1994, Springer, 3-540-57877-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Gabriel M. Silberman, Kemal Ebcioglu |
An architectural framework for migration from CISC to higher performance platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 6th international conference on Supercomputing, ICS 1992, Washington, DC, USA, July 19-24, 1992, pp. 198-215, 1992, ACM, 0-89791-485-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | James C. Dehnert, Peter Y.-T. Hsu, Joseph P. Bratt |
Overlapped Loop Support in the Cydra 5. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 26-38, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
Cydra 5 |
18 | David M. Lewis |
A Programmable Hardware Accelerator for Compiled Electrical Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 172-177, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
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16 | Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury |
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 482-484, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Lucas Ferreira, Steffen Malkowsky, Patrik Persson, Sven Karlsson, Kalle Åström, Liang Liu 0002 |
Design of an Application-specific VLIW Vector Processor for ORB Feature Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 95(7), pp. 863-875, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hao Yu, Jun Wu, Haoqi Ren, Zhifeng Zhang, Bin Tan |
An Efficient and Secure Inline Assembly Design for VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCT ![In: 23rd IEEE International Conference on Communication Technology, ICCT 2023, Wuxi, China, October 20-22, 2023, pp. 123-127, 2023, IEEE, 979-8-3503-2595-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Xin Xiao, Zhong Liu |
ISADL: An Instruction Set Architecture Description Language for VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 29th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2023, Ocean Flower Island, China, December 17-21, 2023, pp. 92-99, 2023, IEEE, 979-8-3503-3071-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Xin Xiao, Zhong Liu |
An Adaptive Instruction Set Encoding Automatic Generation Method for VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (1) ![In: Algorithms and Architectures for Parallel Processing - 23rd International Conference, ICA3PP 2023, Tianjin, China, October 20-22, 2023, Proceedings, Part I, pp. 283-300, 2023, Springer, 978-981-97-0833-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini |
Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 102, pp. 108294, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys |
Dynamic fault-tolerant VLIW processor with heterogeneous Function Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 93, pp. 104564, September 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen |
Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 256-261, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Chia-Heng Hu, I-Hao Tseng, Pei-Hsuan Kuo, Juinn-Dar Huang |
An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICAS ![In: 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022, Incheon, Republic of Korea, June 13-15, 2022, pp. 246-249, 2022, IEEE, 978-1-6654-0996-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Ashish Shrivastava, Alan Gatherer, Tong Sun, Sushma Wokhlu, Alex Chandra |
SLAP: A Split Latency Adaptive VLIW pipeline architecture which enables on-the-fly variable SIMD vector-length. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2102.13301, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
16 | Ashish Shrivastava, Alan Gatherer, Tong Sun, Sushma Wokhlu, Alex Chandra |
SLAP: a Split Latency Adaptive VLIW Pipeline Architecture Which Enables on-The-Fly Variable SIMD Vector-Length. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2021, Toronto, ON, Canada, June 6-11, 2021, pp. 7868-7872, 2021, IEEE, 978-1-7281-7606-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Aiqing Wu, Mengni Bie, Longmei Nan, Wei Li 0131 |
Effective Register Allocation for Configurable VLIW Crypto-Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Cyril Six |
Compilation optimisante et formellement prouvée pour un processeur VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2021 |
RDF |
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16 | Cyril Six, Sylvain Boulmé, David Monniaux |
Certified and efficient instruction scheduling: application to interlocked VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Program. Lang. ![In: Proc. ACM Program. Lang. 4(OOPSLA), pp. 129:1-129:29, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Gongli Li, Yingying Hou, Junzhe Zhu |
An Efficient and Fast VLIW Compression Scheme for Stream Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 224817-224824, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Mohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini |
Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(12), pp. 2050200:1-2050200:23, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Florian Giesemann, Lukas Gerlach 0001, Guillermo Payá Vayá |
Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 92(7), pp. 655-678, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | David Uzan, Roger Kahn, Shlomo Weiss |
Perceptron based filtering of futile prefetches in embedded VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 110, pp. 101826, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Rama Venkatasubramanian, Don Steiss, Greg Shurtz, Tim Anderson, Kai Chirca, Raghavendra Santhanagopal, Niraj Nandan, Anish Reghunath, Hetul Sanghvi, Daniel Wu, Abhijeet Chachad, Brian Karguth, Denis Beaudoin, Charles Fuoco, Lewis Nardini, Chunhua Hu, Sam Visalli, Amrit Mundra, Devanathan Varadarajan, Frank Cano, Shane Stelmach, Mihir Mody, Arthur Redfern, Haydar Bilhan, Maher Sarraj, Ali Siddiki, Anthony Lell, Eldad Falik, Anthony M. Hill, Abhinay Armstrong, Todd Beck, Vijay Kanumuri, Steven Mullinnix, Darnell Moore, Jason Jones, Manoj Koul, Sanjive Agarwala |
2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 52-54, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Adrian Florea, Teodora Vasilas |
Optimizing the Integration Area and Performance of VLIW Architectures by Hardware/Software Co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MDIS ![In: Modelling and Development of Intelligent Systems - 7th International Conference, MDIS 2020, Sibiu, Romania, October 22-24, 2020, Revised Selected Papers, pp. 35-51, 2020, Springer, 978-3-030-68526-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Lukas Gerlach 0001, Fabian Stuckmann, Holger Blume, Guillermo Payá Vayá |
Issue-Slot Based Predication Encoding Technique for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020, Bremen, Germany, September 7-9, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-6687-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Ricardo S. Ferreira 0001, Cristoferson Bueno, Marcone Laure, Monica Magalhães Pereira, Luigi Carro |
A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Trans. High Perform. Embed. Archit. Compil. 5, pp. 121-139, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Sensen Hu, Jing Huang |
Exploring Adaptive Cache for Reconfigurable VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 72634-72646, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Yumin Hou, Xu Wang, Jiawei Fu, Junping Ma, Hu He 0001, Xu Yang 0003 |
Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(2), pp. 1950020:1-1950020:20, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Simon Rokicki, Erven Rohou, Steven Derrien |
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10), pp. 1872-1885, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Elena Limonova, N. A. Bocharov, N. B. Paramonov, D. S. Bogdanov, Vladimir V. Arlazarov, O. A. Slavin, Dmitry P. Nikolaev |
Performance Evaluation of a Recognition System on the VLIW Architecture by the Example of the Elbrus Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Program. Comput. Softw. ![In: Program. Comput. Softw. 45(1), pp. 12-17, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Keni Qiu, Yujie Zhu, Yuanchao Xu 0002, Qirun Huo, Chun Jason Xue |
BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 83, pp. 137-146, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Binbin Liu, Qilong Zheng |
Realize special instructions on clustering VLIW DSP: multiplication-accumulation instruction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.05982, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
16 | Andreas Bytyn, Rainer Leupers, Gerd Ascheid |
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1904.05106, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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16 | Paras Jain 0001, Xiangxi Mo, Ajay Jain, Alexey Tumanov, Joseph E. Gonzalez, Ion Stoica |
The OoO VLIW JIT Compiler for GPU Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1901.10008, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
16 | Xuesong Su, Hui Wu 0001, Jingling Xue |
WCET-aware hyper-block construction for clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2019, Phoenix, AZ, USA, June 23-23, 2019, pp. 110-122, 2019, ACM, 978-1-4503-6724-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys |
Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, pp. 976-979, 2019, IEEE, 978-3-9819263-2-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Andreas Bytyn, Rainer Leupers, Gerd Ascheid |
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys, Emmanuel Casseau |
Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: 2019 Conference on Design and Architectures for Signal and Image Processing, DASIP 2019, Montreal, QC, Canada, October 16-18, 2019, pp. 23-28, 2019, IEEE, 978-1-7281-4074-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Dilshan Kumarathunga, Omega Gamage, Asitha Samarasinghe, Nipuna Saranga, Ranga Rodrigo, Ajith A. Pasqual |
VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019, pp. 103-106, 2019, IEEE, 978-1-7281-1601-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Anderson Luiz Sartor, Pedro Henrique Exenberger Becker, Joost Hoozemans, Stephan Wong, Antonio C. S. Beck |
Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multi Scale Comput. Syst. ![In: IEEE Trans. Multi Scale Comput. Syst. 4(3), pp. 327-339, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Hong Ye, Naijie Gu, Xiaoci Zhang, Chuanwen Lin |
Design and implementation of a conflict-free memory accessing technique for FFT on multicluster VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(18), pp. 20180674, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Joost Hoozemans, Jeroen van Straten, Stephan Wong |
Increasing resource utilization in mixed-criticality systems using a polymorphic VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 84, pp. 2-11, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Elena Limonova, Natalya Skoryukina, Murad I. Neiman-zade |
Fast Hamming distance computation for 2D art recognition on VLIW-architecture in case of Elbrus platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMV ![In: Eleventh International Conference on Machine Vision, ICMV 2018, Munich, Germany, 1-3 November 2018, pp. 110411N, 2018, SPIE. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Marco Spaziani Brunella, Salvatore Pontarelli, Marco Bonola, Giuseppe Bianchi 0001 |
V- PMP: A VLIW Packet Manipulator Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuCNC ![In: 2018 European Conference on Networks and Communications, EuCNC 2018, Ljubljana, Slovenia, June 18-21, 2018, pp. 1-9, 2018, IEEE, 978-1-5386-1478-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Talavera, Antoni Portero, Francky Catthoor |
Impact of Address Generation on Multimedia Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISIM ![In: Computer Information Systems and Industrial Management - 17th International Conference, CISIM 2018, Olomouc, Czech Republic, September 27-29, 2018, Proceedings, pp. 417-433, 2018, Springer, 978-3-319-99953-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Anderson Luiz Sartor, Arthur Francisco Lorenzon, Sandip Kundu, Israel Koren, Antonio C. S. Beck |
Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: Proceedings of the 15th ACM International Conference on Computing Frontiers, CF 2018, Ischia, Italy, May 08-10, 2018, pp. 54-61, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Vladimir V. Stegailov, Alexey Timofeev |
Deploying Elbrus VLIW CPU Ecosystem for Materials Science Calculations: Performance and Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RuSCDays ![In: Supercomputing - 4th Russian Supercomputing Days, RuSCDays 2018, Moscow, Russia, September 24-25, 2018, Revised Selected Papers, pp. 543-553, 2018, Springer, 978-3-030-05806-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Miroslav N. Velev |
Survey of Techniques for Efficient Solving of Boolean Formulas from Formal Verification of Pipelined, Superscalar, and VLIW Microprocessors at a High Level of Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAIM ![In: International Symposium on Artificial Intelligence and Mathematics, ISAIM 2018, Fort Lauderdale, Florida, USA, January 3-5, 2018., 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
16 | Joost Hoozemans |
Targeting static and dynamic workloads with a reconfigurable VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2018 |
RDF |
|
16 | Xuesong Su |
WCET-aware compilation techniques for clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2018 |
RDF |
|
16 | Renan Augusto Starke, Andreu Carminati, Rômulo Silva de Oliveira |
Evaluation of a low overhead predication system for a deterministic VLIW architecture targeting real-time applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 49, pp. 1-8, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Roel Jordans, Lech Józwiak, Henk Corporaal, Rosilde Corvino |
Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 51, pp. 114-133, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Jingchuan Dong, Taiyong Wang, Bo Li, Zhe Liu, Zhiqiang Yu |
An FPGA-based low-cost VLIW floating-point processor for CNC applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 50, pp. 14-25, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Mohamed Najoui, Mounir Bahtat, Anas Hatim, Said Belkouch, Noureddine Chabini |
VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(9), pp. 1750129:1-1750129:26, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Luc Michel, Frédéric Pétrot |
Dynamic Binary Translation of VLIW Codes on Scalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5), pp. 789-800, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Xuesong Su, Hui Wu 0001, Jingling Xue |
An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 16(5s), pp. 120:1-120:21, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Jukka Teittinen, Markus Hiienkari, Indre Zliobaite, Jaakko Hollmén, Heikki Berg, Juha Heiskala, Timo Viitanen, Jesse Simonsson, Lauri Koskinen |
A 5.3 pJ/op approximate TTA VLIW tailored for machine learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 61, pp. 106-113, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Hu He 0001, Xu Yang 0003, Yanjun Zhang |
On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 60(9), pp. 1338-1352, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Paolo Meloni, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo |
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 76, pp. 89-101, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys |
NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 391-396, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Debjyoti Bhattacharjee, Rajeswari Devadoss, Anupam Chattopadhyay |
ReVAMP: ReRAM based VLIW architecture for in-memory computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 782-787, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Omayma Matoussi, Frédéric Pétrot |
Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 266-269, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich |
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2017, Seoul, South Korea, September 18-20, 2017, pp. 5-12, 2017, IEEE Computer Society, 978-1-5386-3441-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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