Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | Masashi Hashimoto |
Adder Merged DRAM Architecture. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Oscar Gustafsson, Andrew G. Dempster, Lars Wanhammar |
Extended results for minimum-adder constant integer multipliers. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Ayman A. Fayed, Magdy A. Bayoumi |
Noise-tolerant design and analysis for a low-voltage dynamic full adder cell. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman |
A robust self-resetting CMOS 32-bit parallel adder. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Satoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi |
Flexible processor based on full-adder/ d-flip-flop merged module. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang |
A 1.25 GHz 32-bit tree-structured carry lookahead adder. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Phillip Benachour, Patrick Guy Farrell, Bahram Honary |
A Line Code Construction for the Adder Channel with Rates Higher than Time-Sharing. |
IMACC |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Hak-soo Yu, Songjun Lee, Jacob A. Abraham |
An Adder Using Charge Sharing and its Application in DRAMs. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
21 | David M. Russinoff |
A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
21 | J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak |
SOI Implementation of a 64-Bit Adder. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Taewhan Kim, William Jao, Steven W. K. Tjiang |
Circuit optimization using carry-save-adder cells. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Alejandro F. González, Pinaki Mazumder |
Compact Signed-Digit Adder Using Multiple-Valued Logic. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Dietmar Fey |
Transformation of a 2-D VLSI Systolic Adder Circuit in 3-D Circuits Using Optical Interconnections. |
Euro-Par, Vol. II |
1996 |
DBLP DOI BibTeX RDF |
|
21 | Stuart F. Oberman, Michael J. Flynn |
A Variable Latency Pipelined Floating-Point Adder. |
Euro-Par, Vol. II |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee |
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
Boolean logic minimization, energy-efficient electronics, laterally-actuated NEMS, nanoelectromechanical switches, XOR gates |
16 | Faizal Karim, Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Konrad Walus, André Ivanov, Fabrizio Lombardi |
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits. |
J. Electron. Test. |
2009 |
DBLP DOI BibTeX RDF |
Quantum-dot cellular automata (QCA), Clocked QCA, Emerging nanotechnologies, Phase shift |
16 | Yee Jern Chong, Sri Parameswaran |
Flexible multi-mode embedded floating-point unit for field programmable gate arrays. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture |
16 | Krishna K. Nagar, Yan Zhang, Jason D. Bakos |
An integrated reduction technique for a double precision accumulator. |
HPRCTA@SC |
2009 |
DBLP DOI BibTeX RDF |
high-performance computing, reconfigurable computing, scientific computing, reduction, accumulator, IEEE 754, double precision |
16 | Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz |
A fault tolerant, area efficient architecture for Shor's factoring algorithm. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
ion trap, control, quantum computing, layout, cad |
16 | Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds |
Bridge Floating-Point Fused Multiply-Add Design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | I-Chyn Wey, You-Gang Chen, An-Yeu Wu |
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001 |
A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita |
Arithmetic Circuits Verification without Looking for Internal Equivalences. |
MEMOCODE |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Haridimos T. Vergos, Dimitris Bakalis |
On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Shai Erez, Guy Even |
An improved micro-architecture for function approximation using piecewise quadratic interpolation. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Chong-Yu Huang, Lien-Fei Chen, Yeong-Kang Lai |
A high-speed 2-D transform architecture with unique kernel for multi-standard video applications. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Anas A. Hamoui, Mohammad Sukhon, Franco Maloberti |
Digitally-enhanced 2nd-order DeltaSigma modulator with unity-gain signal transfer function. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima |
ROM based logic (RBL) design: High-performance and low-power adders. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Álvaro Vázquez, Elisardo Antelo |
New insights on Ling adders. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Tae Ho Kim, Sang Chul Kim, Chang Hoon Kim, Chun Pyo Hong |
Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m). |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
Multi-Precision CSA, Scalable Multiplier, VLSI, Montgomery Multiplication |
16 | Sabyasachi Das, Sunil P. Khatri |
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Sundeepkumar Agarwal, Pavankumar V. K., Yokesh R. |
Energy-Efficient, High Performance Circuits for Arithmetic Units. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Tad Hogg, Greg Snider |
Defect-tolerant Logic with Nanoscale Crossbar Circuits. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
fault modeling, nanotechnology, molecular electronics, circuit reliability |
16 | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii |
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. |
ICESS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Akashi Satoh, Takeshi Sugawara 0001, Takafumi Aoki |
High-Speed Pipelined Hardware Architecture for Galois Counter Mode. |
ISC |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Henning Gundersen, Yngvar Berg |
Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Jain 0004, Preeti Ranjan Panda |
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu |
Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Zhiyu Liu, Volkan Kursun |
Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Akashi Satoh |
High-Speed Parallel Hardware Architecture for Galois Counter Mode. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | S. Vijay, A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Zhiyu Liu, Volkan Kursun |
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling |
16 | George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing |
16 | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Fault tolerance, error checking, high-speed arithmetic |
16 | William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski |
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi |
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
(4,2)-compressor, digit set, signed digit, computer arithmetic, redundant number system, carry-free addition |
16 | Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim |
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | K. Scott Hemmert, Keith D. Underwood |
Open Source High Performance Floating-Point Modules. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
IEEE floating point, FPGA, reconfigurable computing |
16 | Kwangsup So, Jin-Sang Kim, Won-Kyung Cho, Young Soo Kim, Doug Young Suh |
Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Fault tolerant design of signed digit based FIR filters. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Ravi Kumar Satzoda, Chip-Hong Chang |
A fast kernel for unifying GF(p) and GF(2m) Montgomery multiplications in a scalable pipelined architecture. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Petros Oikonomakos, Paul Fox |
Error Correction in Arithmetic Operations by I/O Inversion. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel |
A New Self-Checking and Code-Disjoint Non-Restoring Array Divider. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas |
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Uwe Meyer-Bäse, Jiajia Chen 0002, Chip-Hong Chang, Andrew G. Dempster |
A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Shibu Menon, Chip-Hong Chang |
A Reconfigurable Multi-Modulus Modulo Multiplier. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Robert D. Kenney, Michael J. Schulte |
High-Speed Multioperand Decimal Adders. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic |
16 | Shugang Wei |
Number conversions between RNS and mixed-radix number system based on Modulo (2p - 1) signed-digit arithmetic. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Hanho Lee |
Reconfigurable Power-Aware Scalable Booth Multiplier. |
KES (1) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Ilya Obridko, Ran Ginosar |
Low energy asynchronous architectures. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Ge Zhang 0007, Zichu Qi, Weiwu Hu |
A novel design of leading zero anticipation circuit with parallel error detection. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
Optimizing vertical common subexpression elimination using coefficient partitioning for designing low complexity software radio channelizers. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Y. Ibrahim, William C. Miller, Graham A. Jullien, Vassil S. Dimitrov |
DBNS addition using cellular neural networks. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | James E. Stine, Christopher R. Babb, Vibhuti B. Dave |
Constant addition utilizing flagged prefix structures. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Srivathsan Krishnamohan, Nihar R. Mahapatra |
Increasing the energy efficiency of pipelined circuits via slack redistribution. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
slack passing, time borrowing, low-power design |
16 | Tomás Lang, Javier D. Bruguera |
Floating-Point Multiply-Add-Fused with Reduced Latency. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Robert D. Kenney, Michael J. Schulte |
Multioperand Decimal Addition. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris |
Fast adders in modern FPGAs. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel |
High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. |
ASYNC |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Woo-Chan Park, Tack-Don Han, Sung-Bong Yang |
A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel. |
Asia-Pacific Computer Systems Architecture Conference |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang |
Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Ge Yang 0004, Zhongda Wang, Sung-Mo Kang |
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
Easily Testable Cellular Carry Lookahead Adders. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model |
16 | Jen-Shiun Chiang, Min-Shiou Tsai |
A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling. |
J. VLSI Signal Process. |
2003 |
DBLP DOI BibTeX RDF |
floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system |
16 | Javier D. Bruguera, Tomás Lang |
Multilevel Reverse-Carry Addition: Single and Dual Adders. |
J. VLSI Signal Process. |
2003 |
DBLP DOI BibTeX RDF |
prefix adders, dual adders, most-significant-carry detection, computer arithmetic, VLSI design |
16 | Javier Ramírez 0001, Uwe Meyer-Bäse, Antonio García 0001, Antonio Lloris-Ruíz |
Design and Implementation of RNS-Based Adaptive Filters. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Hossam A. H. Fahmy, Michael J. Flynn |
The Case for a Redundant Format in Floating Point Arithmetic. |
IEEE Symposium on Computer Arithmetic |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Zhijun Huang, Milos D. Ercegovac |
High-Performance Left-to-Right Array Multiplier Design. |
IEEE Symposium on Computer Arithmetic |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng |
An Algorithmic Approach for Generic Parallel Adders. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi 0001 |
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms. |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Daeik D. Kim, Martin A. Brooke |
A 1.4G samples/sec comb filter design for decimation of sigma-delta modulator output. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
16 | B. Kiran Kumar, Parag K. Lala |
On-line Detection of Faults in Carry-Select Adders. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
VLSI circuits for low-power high-speed asynchronous addition. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | E. Islas Pérez, Carlos A. Coello Coello, Arturo Hernández Aguirre, Alejandro Villavicencio Ramírez |
Genetic Algorithms and Case-Based Reasoning as a Discovery and Learning Machine in the Optimization of Combinational Logic Circuits. |
MICAI |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara |
Folding of logic functions and its application to look up table compaction. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Tomás Lang, Javier D. Bruguera |
Floating-Point Fused Multiply-Add with Reduced Latency. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
16 | G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith |
Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis |
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Peter Kornerup |
Reviewing 4-to-2 Adders for Multi-Operand Addition. |
ASAP |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi |
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Jaroslaw Pykacz, Bart D'Hooghe, Roman R. Zapatrin |
Quantum Computers as Fuzzy Computers. |
Fuzzy Days |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Kiwon Choi, Minkyu Song |
Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder. |
ISCAS (2) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Andreas Wassatsch, Dirk Timmermann |
Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Hong-Yi Huang, Teng-Neng Wang |
High-speed CMOS logic circuits in capacitor coupling technique. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Athanasios Kakarountas, Kyriakos Papadomanolakis, Vasileios Kokkinos, Constantinos E. Goutis |
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Chanyutt Arjhan, Raghvendra G. Deshmukh |
A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier |
16 | Miguel A. Sacristán, María Victoria Rodellar Biarge, Antonio Diaz, V. Garcia, Pedro Gómez 0001 |
A Reusable Inner Product Unit for DSP Applications. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Christian Pacha, Peter Glösekötter, Karl Goser, Uwe Auer, Werner Prost, Franz-Josef Tegude |
Resonant Tunneling Transistors for Threshold Logic Circuit Applications. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Shugang Wei, Kensuke Shimizu |
Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|