Search results for "capacitance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Aditya P. Karmarkar, Xiaopeng Xu, Victor Moroz, Greg Rollins, Xiao Lin	Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
15	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
15	Kostas Siozios, Dimitrios Soudris	An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.	PATMOS	2008	DBLP DOI BibTeX RDF	P? CAD Algorithm, FPGA, Management, Power, 3D
15	Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings	A technique for minimizing power during FPGA placement.	FPL	2008	DBLP DOI BibTeX RDF
15	Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng	Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction.	ISPD	2008	DBLP DOI BibTeX RDF	crosstalk reduction, full-chip routing, gridless routing, implicit connection graph-based router, non-slicing floorplanning, detailed routing
15	Jae-Seok Yang, David Z. Pan	Overlay aware interconnect and timing variation modeling for double patterning technology.	ICCAD	2008	DBLP DOI BibTeX RDF
15	Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin, Mark G. Karpovsky	Asynchronous balanced gates tolerant to interconnect variability.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Ioannis Savidis, Eby G. Friedman	Electrical modeling and characterization of 3-D vias.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Equivalent rise time for resonance in power/ground noise estimation.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Yu-Huei Lee, Shih-Jung Wang, Chun-Yu Hsieh, Ke-Horng Chen	Current mode DC-DC buck converters with optimal fast-transient control.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale	Low-voltage LDO Compensation Strategy based on Current Amplifiers.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Robert Kolm, Weixun Yan, Horst Zimmermann	Current-mode filter in 65nm CMOS for a software-radio application.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Liu Jianfeng, Jiang Yong, Ding Chuanhong	Research on the Measurement System of Gyro Rotor.	CSSE (5)	2008	DBLP DOI BibTeX RDF
15	Mark M. Budnik, Eric W. Johnson, Joshua D. Wood	Electrical models for vertical carbon nanotube capacitors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	interconnect, carbon nanotube, via, capacitor
15	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.	ISQED	2008	DBLP DOI BibTeX RDF	signal integrity, mixed-signal circuits, Substrate coupling
15	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
15	Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri	A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen	Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Parameterized Non-Gaussian Variational Gate Timing Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay	An Approach for Pre-Silicon Power Modeling.	ICCTA	2007	DBLP DOI BibTeX RDF
15	Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay	A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs.	ISVLSI	2007	DBLP DOI BibTeX RDF
15	Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail	Including inductance in static timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
15	Sandeep Patil, Michael Wieckowski, Martin Margala	A Self-Biased Charge-Transfer Sense Amplifier.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Ebrahim Ghafar-Zadeh, Mohamad Sawan	A CMOS-Based Capacitive Sensor for Laboratory-On-Chips: Design and Experimental Results.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Yanming Jia, Yici Cai, Xianlong Hong	Dummy fill aware buffer insertion during routing.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	routing, VLSI, DFM, buffer insertion, dummy fill
15	Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham	Estimating path delay distribution considering coupling noise.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	dynamic delay variation, coupling, crosstalk
15	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Delay-Balanced Smart Repeaters for On-Chip Global Signaling.	VLSI Design	2007	DBLP DOI BibTeX RDF
15	Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan	Interframe Bus Encoding Technique for Low Power Video Compression.	VLSI Design	2007	DBLP DOI BibTeX RDF
15	Janet Meiling Wang, Jun Li 0066, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla	Modeling the Driver Load in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang	Crosstalk minimization in logic synthesis for PLAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	synthesis, Crosstalk, PLA, domino logic
15	Minoru Watanabe, Fuminori Kobayashi	A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ARC	2006	DBLP DOI BibTeX RDF
15	Byungsub Kim, Soumyajit Mandal, Rahul Sarpeshkar	Power-adaptive operational amplifier with positive-feedback self biasing.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Milan Daphtary, Sameer Sonkusale	Broadband capacitive sensor CMOS interface circuit for dielectric spectroscopy.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri	Memory-based crosstalk canceling CODECs for on-chip buses.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Georgios Vitzilaios, Yannis Papananos, Gerasimos Theodoratos, Athanasios Vasilopoulos	A low-voltage CMOS LNA with multiple magnetic feedback for WLAN applications.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Cheng-Ta Chan, Oscal T.-C. Chen	Inductor-less 10Gb/s CMOS transimpedance amplifier using source-follower regulated cascode and double three-order active feedback.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Chunyan Wang 0004	Implementation of space-efficient voltage-insensitive capacitances in integrated circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Huawei Li, Yu Fan, Rong Shi	Chaos and Ferroresonance.	CCECE	2006	DBLP DOI BibTeX RDF
15	A. Bendali, R. Labedan, F. Domingue, V. Nerguizian	Holes Effects on RF MEMS Parallel Membranes Capacitors.	CCECE	2006	DBLP DOI BibTeX RDF
15	Daisuke Suzuki, Minoru Saeki	Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.	CHES	2006	DBLP DOI BibTeX RDF
15	Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang	Timing-driven Steiner trees are (practically) free.	DAC	2006	DBLP DOI BibTeX RDF	arborescence, timing-driven, rectilinear Steiner tree
15	Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy 0001	A high density, carbon nanotube capacitor for decoupling applications.	DAC	2006	DBLP DOI BibTeX RDF	interconnect, carbon nanotube, three-dimensional, capacitor
15	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
15	Kai Wang 0011, Malgorzata Marek-Sadowska	On-chip power-supply network optimization using multigrid-based technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Kavel M. Büyüksahin, Farid N. Najm	Early power estimation for VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware low-power high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Ali Manzak, Hüseyin Göksu	Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design.	SAMOS	2005	DBLP DOI BibTeX RDF
15	Siobhán Launders, Colin Doyle, Wesley Cooper	Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.	PATMOS	2005	DBLP DOI BibTeX RDF
15	Laurent Lopez, Jean-Michel Portal, Didier Née	A New Embedded Measurement Structure for eDRAM Capacitor.	DATE	2005	DBLP DOI BibTeX RDF
15	Paul Zuber, Armin Windschiegl, Raúl Medina Beltrán de Otálora, Walter Stechele, Andreas Herkersdorf	Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization.	DATE	2005	DBLP DOI BibTeX RDF
15	Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
15	Dennis Buss	Technology and design challenges for mobile communication and computing products.	ISLPED	2005	DBLP DOI BibTeX RDF
15	Brock J. LaMeres, Sunil P. Khatri	Broadband Impedance Matching for Inductive Interconnect in VLSI Packages.	ICCD	2005	DBLP DOI BibTeX RDF
15	Chiara Ghidini, J. G. Aranda, Danilo Gerna, K. Kelliher, Christoph Baumhof	A digitally programmable on-chip RC-oscillator in 0.25µm CMOS logic process.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	Gabriel Abadal, Jaume Verd, Jordi Teva, Arantxa Uranga, Núria Barniol, Jaume Esteve, Marta Duch, Francesc Pérez-Murano	High-sensitivity capacitive readout system for resonant submicrometer-scale cantilevers based sensors.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Chun-Ming Chang	Voltage-mode high-order OTA-only-without-C low-pass (from 215 M to 705 M Hz) and band-pass (from 214 M to 724 M Hz) filter structure.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Kishore Kumar Muchherla, Pinhong Chen, Janet Meiling Wang	A non-iterative equivalent waveform model for timing analysis in presence of crosstalk.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Mikko Saukoski, Lasse Aaltonen, Teemu Salo, Kari Halonen	Fully integrated charge sensitive amplifier for readout of micromechanical capacitive sensors.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Antônio Carlos M. de Queiroz	Multiple resonance networks with incomplete energy transfer and operating with zero-state response.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	Lu Liu, Zhihua Wang 0001, Guolin Li	Calculation of intermodulation distortion in CMOS transconductance stage.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
15	Sani R. Nassif, Zhuo Li 0001	A More Effective CEFF.	ISQED	2005	DBLP DOI BibTeX RDF
15	N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell	The Impact of Inductance on Transients Affecting Gate Oxide Reliability.	VLSI Design	2005	DBLP DOI BibTeX RDF
15	Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob K. White 0001	A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
15	Chunjie Duan, Sunil P. Khatri	Exploiting Crosstalk to Speed up On-Chip Buse.	DATE	2004	DBLP DOI BibTeX RDF
15	Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu	A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
15	Jaidilson Jó da Silva, Felix Rodrigues Neto, Manoel Alves Filho, Alfranque A. da Silva, Orlei de Oliveira Barbosa, Miguel Gonçalves Wanzeller, José Sérgio da Rocha Neto	Microconverter Aided Time Constant Measurement.	CONIELECOMP	2004	DBLP DOI BibTeX RDF
15	Takao Tsuchiya, Yukio Kagawa	On the Passive Vibration Damping by Piezoelectric Transducers with Inductive Loading.	AsiaSim	2004	DBLP DOI BibTeX RDF
15	P. D. Grant, M. W. Denhoff, Raafat R. Mansour	A Comparison between RF MEMS Switches and Semiconductor Switches.	ICMENS	2004	DBLP DOI BibTeX RDF
15	Nima Maghari, Mohammad Yavari, Omid Shoaei	An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Jorge R. Fernandes, Manuel Medeiros Silva	A very low-power CMOS parallel A/D converter for embedded applications.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Sean Nicolson, Khoman Phang	Improvements in biasing and compensation of CMOS opamps.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Li Ding 0002, Pinaki Mazumder	Dynamic Noise Margin: Definitions and Model.	VLSI Design	2004	DBLP DOI BibTeX RDF
15	Tina Lindkvist, Jacob Löfvenberg, Henrik Ohlsson, Kenny Johansson, Lars Wanhammar	A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances.	IWSOC	2004	DBLP DOI BibTeX RDF
15	Razak Hossain, Fabrizio Viglione, Marco Cavalli	Designing fast on-chip interconnects for deep submicrometer technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
15	Kianosh Rahimi, Mani Soma	Layout driven synthesis of multiple scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
15	Charles J. Alpert, Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu, Alexander Zelikovsky	Minimum buffered routing with bounded capacitive load for slew rate and reliability control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
15	Ryon M. Smey, Bill Swartz, Patrick H. Madden	Crosstalk Reduction in Area Routing.	DATE	2003	DBLP DOI BibTeX RDF
15	Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle	Design of Resonant Global Clock Distributions.	ICCD	2003	DBLP DOI BibTeX RDF
15	Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas, M. Gloanec, E. Leclerc, Bernard Lefebvre	High gain GaAs 10Gbps transimpedance amplifier with integrated bondwire effects.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
15	Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re	Power-delay tradeoffs in residue number system.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Drazen Jurisic, George S. Moschytz, Neven Mijat	Low-noise low-power allpole active-RC filters minimizing resistor level.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	J. Shorb, Xiaoyong Li 0001, David J. Allstot	A resonant pad for ESD protected narrowband CMOS RF applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	on-chip inductance, shielding effect, propagation delay, interconnect modeling, gate delay
15	Dhruva Acharyya, Jim Plusquellic	Impedance Profile of a Commercial Power Grid and Test System.	ITC	2003	DBLP DOI BibTeX RDF
15	Kaushik Gala, David T. Blaauw, Vladimir Zolotov, Pravin M. Vaidya, Anil Joshi	Inductance model and analysis methodology for high-speed on-chip interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
15	Kaustav Banerjee, Amit Mehrotra	Analysis of on-chip inductance effects for distributed RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
15	Weiping Shi, Jianguo Liu 0001, Naveen Kakani, Tiejun Yu	A fast hierarchical algorithm for three-dimensional capacitanceextraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
15	R. M. Nussbaumer, D. G. Rüegg, L. M. Studer, J.-P. Gabriel	Computer simulation of the motoneuron pool-muscle complex. I. Input system and motoneuron pool.	Biol. Cybern.	2002	DBLP DOI BibTeX RDF
15	Armin Windschiegl, Paul Zuber, Walter Stechele	Exploiting Metal Layer Characteristics for Low-Power Routing.	PATMOS	2002	DBLP DOI BibTeX RDF
15	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Congestion-Aware Logic Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
15	Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka	Efficient Power Reduction Techniques for Time Multiplexed Address Buses.	ISSS	2002	DBLP DOI BibTeX RDF	address encoding techniques, time-multiplexed addressing, low power
15	Unni Narayanan, Ki-Seok Chung, Taewhan Kim	Enhanced bus invert encodings for low-power.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
15	Jacqueline S. Pereira, Antonio Petraglia, Mauricio F. Quélhas	Approximating linear phase with IIR SC filters.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
15	Martin Kuhlmann, Sachin S. Sapatnekar	Exact and efficient crosstalk estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Angelo Brambilla, Paolo Maffezzoni	Statistical method for the analysis of interconnects delay insubmicrometer layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Interconnect sizing and spacing with consideration of couplingcapacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Daniel Eckerbert, Per Larsson-Edefors	Interconnect-Driven Short-Circuit Power Modeling.	DSD	2001	DBLP DOI BibTeX RDF
15	Ivan E. Sutherland, Jon K. Lexau	Designing Fast Asynchronous Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
15	Denis Deschacht, Grégory Servel	On-chip interconnections: impact of adjacent lines on timing.	ASP-DAC	2001	DBLP DOI BibTeX RDF