Search results for "decoder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Anthony Vetro, Huifang Sun, Jay Bao, Tommy Poon	Frequency Domain Down Conversion of HDTV Using Adaptive Motion Compensation.	ICIP (1)	1997	DBLP DOI BibTeX RDF	adaptive motion compensation, NTSC monitor, frequency domain down-conversion, HDTV signal, frequency synthesis algorithm, down-conversion decoder, adaptive motion compensation algorithm, complexity, image sequences, image quality, digital TV, DCT coefficients, high definition television
22	Laurent Bonnaud, Claude Labit	Multiple Occluding Objects Tracking Using a Non-Redundant Boundary-Based Representation for Image Sequence Interpolation After Decoding.	ICIP (2)	1997	DBLP DOI BibTeX RDF	multiple occluding objects, nonredundant boundary-based representation, image sequence interpolation, motion-based image sequence segmentation, adjacent regions, polygonal line, predictive tracking, region fusion, motion-compensated compression, temporal interpolation, coder/decoder chain, interpolation, coding, decoding, multimedia application, layering, image sequence analysis, receiver, structural information, object manipulation, partial occlusions, tracking algorithm
22	Kei Karasawa, Makoto Iwata, Hiroaki Terada	Direct Generation of Data-Driven Program for Stream-Oriented Processing.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Parallel processing system specifications, Multiple data streams, Direct program generation, Data-driven paradigm, HDTV signal decoder
22	M. Balakrishnan	Buffer constraints in a variable-rate packetized video system.	ICIP	1995	DBLP DOI BibTeX RDF	variable rate codes, variable rate packetized video system, variable rate video encoding system, encoder buffer control mechanism, decoder buffers, logical buffer sizes, channel rate, algorithm, video coding, packet switching, decoding, buffer storage, telecommunication control, necessary conditions, buffer constraints
22	Serafim N. Efstratiadis, Michael G. Strintzis, Aggelos K. Katsaggelos	Motion field prediction and restoration for low bit-rate video coding.	ICIP	1995	DBLP DOI BibTeX RDF	motion field prediction, motion vector field prediction methods, motion compensated video coding, low bit rate transmission, spatiotemporally adaptive regularization, neighborhood information, initial prediction estimate, Kalman MVF restoration, image intensity temporal updates, restoration method, transmission cost reduction, videoconference image sequences, performance, motion estimation, image sequences, experiments, video coding, image restoration, image restoration, encoder, adaptive systems, image representation, decoder, motion compensation, teleconferencing, prediction theory, low bit-rate video coding
22	Jiann-Jone Chen, David W. Lin	Optimal coding of video sequence over ATM networks.	ICIP	1995	DBLP DOI BibTeX RDF	finite encoder buffer size, finite decoder buffer size, transmission rates, picture property variation, leaky bucket policing mechanism, rate constraints, motion JPEG, hierarchical characteristics, monotonic characteristics, nonconvex distortion rate relations, optimization, asynchronous transfer mode, optimisation, image sequences, video coding, video coding, ATM networks, MPEG, buffer storage, video sequence, tree structure, switching networks, telecommunication networks, rate distortion theory, optimal coding, coding quality
22	Kees van Berkel 0001, Ferry Huberts, Ad M. G. Peeters	Stretching quasi delay insensitivity by means of extended isochronic forks.	ASYNC	1995	DBLP DOI BibTeX RDF	extended isochronic forks, isochronic-fork assumption, double-rail data paths, DCC error decoder, logic design, asynchronous circuits, asynchronous circuits, arbiter, delay insensitivity, handshake circuits
22	Menghui Zheng, Alexander Albicki	Low power and high speed multiplication design through mixed number representations.	ICCD	1995	DBLP DOI BibTeX RDF	high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
22	Stephen C. Glinski, David B. Roe	Spoken Language Recognition on a DSP Array Processor.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	speechrecognition, spoken language recognition, DSP array processor, real-time large-vocabulary speaker-independent continuous speech recognizers, multiplehigh-performance central processing units, high interprocessor communication bandwidth, feature extractor, mixture probability computer, state probability computer, word probability computer, phrase probability computer, traceback computer, multistage stack decoder, parallel architectures, partitioning, message passing, array processor, array signal processing, linear predictive coding, linear predictive coding
20	Domenic Forte, Ankur Srivastava 0001	Energy and thermal-aware video coding via encoder/decoder workload balancing.	ISLPED	2010	DBLP DOI BibTeX RDF	distibuted video coding, multimedia applications, energy management, dynamic thermal management
20	Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto	A high performance LDPC decoder for IEEE802.11n standard.	ASP-DAC	2009	DBLP DOI BibTeX RDF
20	Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula	A scalable parallel H.264 decoder on the cell broadband engine architecture.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	code overlay, scalable, parallel, video, multicore, H.264, cell broadband engine, MPEG4
20	Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan	Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder.	ARC	2009	DBLP DOI BibTeX RDF
20	Kai Zhang 0025, Xinming Huang 0001, Zhongfeng Wang	An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems.	ASAP	2009	DBLP DOI BibTeX RDF
20	Tsu-Ming Liu, Chen-Yi Lee	Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	prediction, memory hierarchy, H.264/AVC, lookahead
20	Yu Li, Yun He	Bandwidth Optimized and High Performance Interpolation Architecture in Motion Compensation for H.264/AVC HDTV Decoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	video coding, H.264/AVC, motion compensation, VLSI design
20	Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro	Configurable LDPC Decoder Architectures for Regular and Irregular Codes.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	Error correcting codes, Reconfigurable architectures, Low density parity check codes
20	Steffen Kamp, Michael Evertz, Mathias Wien	Decoder side motion vector derivation for inter frame video coding.	ICIP	2008	DBLP DOI BibTeX RDF
20	Namyoon Lee, Heesun Park, Joohwan Chun	Linear Precoder and Decoder Design for Two-Way AF MIMO Relaying System.	VTC Spring	2008	DBLP DOI BibTeX RDF
20	Sook Min Park, Jaeyoung Kwak, Kwyro Lee	Extrinsic Information Memory Reduced Architecture for Non-Binary Turbo Decoder Implementation.	VTC Spring	2008	DBLP DOI BibTeX RDF
20	Kim Grüttner, Frank Oppenheimer, Wolfgang Nebel, Fabien Colas-Bigey, Anne-Marie Fouilliart	SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder.	DATE	2008	DBLP DOI BibTeX RDF
20	Sébastien Bilavarn, Cécile Belleudy, Michel Auguin, T. Dupont, Anne-Marie Fouilliart	Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations.	DSD	2008	DBLP DOI BibTeX RDF
20	Jinjin He, Zhongfeng Wang 0001, Huaping Liu	Low-complexity high-speed 4-D TCM decoder.	SiPS	2008	DBLP DOI BibTeX RDF
20	Dandan Ding, Lu Yu 0003, Christophe Lucarz, Marco Mattavelli	Video decoder reconfigurations and AVS extensions in the new MPEG reconfigurable video coding framework.	SiPS	2008	DBLP DOI BibTeX RDF
20	Ruchira Yasaratna, Pradeepa Yahampath	Cosntruction of a scalable decoder for a wireless sensor network using Bayesian networks.	ICASSP	2008	DBLP DOI BibTeX RDF
20	Mahdi Shabany, Krishna Su, P. Glenn Gulak	A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder.	ICASSP	2008	DBLP DOI BibTeX RDF
20	Gopal Santhanam, Byron M. Yu, Vikash Gilja, Stephen I. Ryu, Afsheen Afshar, Maneesh Sahani, Krishna V. Shenoy	A factor-analysis decoder for high-performance neural prostheses.	ICASSP	2008	DBLP DOI BibTeX RDF
20	Ting-Yu Huang, Guo-An Jian, Jui-Chin Chu, Ching-Lung Su, Jiun-In Guo	Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications.	ICASSP	2008	DBLP DOI BibTeX RDF
20	Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua	Multi-mode message passing switch networks applied for QC-LDPC decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Yang Liu 0016, Fei Sun, Tong Zhang 0002	Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park	A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Wan Chaodon, Wang Yujun	The Multimedia Teaching System Based on Infrared Remote-Control Signal Decoder.	CSSE (5)	2008	DBLP DOI BibTeX RDF
20	Marcos B. S. Tavares, Steffen Kunze, Emil Matús, Gerhard P. Fettweis	Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes.	ASAP	2008	DBLP DOI BibTeX RDF
20	Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto	A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	ldpc, message passing algorithm
20	A. Saroka, Dan Raphaeli	Joint Carrier Phase Estimation and Turbo Decoding Using Bit Carrier Phase APP Decoder.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
20	Ivy H. Tseng, Antonio Ortega	Rate-Distortion Analysis and Bit Allocation Strategy for Motion Estimation at the Decoder using Maximum Likelihood Technique in Distributed Video Coding.	ICIP (2)	2007	DBLP DOI BibTeX RDF
20	Marco Tagliasacchi, Laura Frigerio, Stefano Tubaro	Analysis of Coding Efficiency of Motion-Compensated Interpolation at the Decoder in Distributed Video Coding.	ICIP (3)	2007	DBLP DOI BibTeX RDF
20	Miha Smolnikar, Tomaz Javornik, Mihael Mohorcic	Channel Decoder Assisted Adaptive Coding and Modulation for HAP Communications.	VTC Spring	2007	DBLP DOI BibTeX RDF
20	Weihuang Wang, Gwan Choi	Minimum-energy LDPC decoder for real-time mobile application.	DATE	2007	DBLP DOI BibTeX RDF
20	Giuseppe Gentile, Massimo Rovini, Luca Fanucci	Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes.	DSD	2007	DBLP DOI BibTeX RDF
20	Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, Wei-Cheng Hung, Kai-Yuan Jan	A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform.	ASP-DAC	2007	DBLP DOI BibTeX RDF
20	Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi	Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.	ICCD	2007	DBLP DOI BibTeX RDF
20	Emil Matús, Marcos B. S. Tavares, Marcel Bimberg, Gerhard P. Fettweis	Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Daesun Oh, Keshab K. Parhi	Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Mei Guo, Yan Lu 0001, Feng Wu 0001, Shipeng Li 0001, Wen Gao 0001	Distributed Video Coding with Spatial Correlation Exploited Only at the Decoder.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Yu Li, Yanmei Qu, Yun He	Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Yi-Hsing Chien, Mong-Kai Ku	A High Throughput H-QC LDPC Decoder.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Sang-Moon Soak, David W. Corne, Byung-Ha Ahn	The Edge-Window-Decoder Representation for Tree-Based Problems.	IEEE Trans. Evol. Comput.	2006	DBLP DOI BibTeX RDF
20	Xiaolin Luo, Mostofa K. Howlader	Noncoherent decoder-assisted frame synchronization for packet transmission.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
20	Recep O. Ozdag, Peter A. Beerel	An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
20	Jae Hyun Baek, Myung Hoon Sunwoo	New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
20	Arul D. Murugan, Hesham El Gamal, Mohamed Oussama Damen, Giuseppe Caire	A unified framework for tree search decoding: rediscovering the sequential decoder.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
20	Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin 0001	G729 Voice Decoder Design.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	CELP coders, G729 standard, Hw/Sw design, LPC analysis, voice decoding, IP, VLSI design
20	Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi	Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
20	Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni	A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks.	DSD	2006	DBLP DOI BibTeX RDF
20	Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi	A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
20	Youngsoo Kim, William W. Edmonson	H.264 Video Decoder Design: Beyond RTL Design Implementation.	SiPS	2006	DBLP DOI BibTeX RDF
20	Jie Jin, Chi-Ying Tsui	A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications.	ISLPED	2006	DBLP DOI BibTeX RDF	low power, convolutional code, Viterbi algorithm
20	Zhiqiang Cui, Zhongfeng Wang 0001	Area-efficient parallel decoder architecture for high rate QC-LDPC codes.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Jin Lee, Sin-Chong Park, Sungchung Park	A pipelined VLSI architecture for a list sphere decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Zhiqiang Cui, Zhongfeng Wang 0001	A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Zhaohui Cai, Jianzhong Hao, Sumei Sun, Francois Poshin Chin	A high-speed Reed-Solomon decoder for correction of both errors and erasures.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang	A bit-serial approximate min-sum LDPC decoder and FPGA implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro	Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation.	ASAP	2006	DBLP DOI BibTeX RDF
20	Thomas Warsaw, Marcin Lukowiak	Architecture design of an H.264/AVC decoder for real-time FPGA implementation.	ASAP	2006	DBLP DOI BibTeX RDF
20	Yongmei Dai, Zhiyuan Yan 0001, Ning Chen 0004	Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	quasi-cyclic (QC) codes, sum-product decoding, turbo decoding, low-density parity-check (LDPC) codes
20	Qi Zhang 0024, Yunyang Dai, Siwei Ma, C.-C. Jay Kuo	Decoder-Friendly Subpel MV Selection for H.264/AVC Video Encoding.	IIH-MSP	2006	DBLP DOI BibTeX RDF
20	Peter J. Green, Desmond P. Taylor	Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array.	DELTA	2006	DBLP DOI BibTeX RDF
20	Geoffrey G. Messier, Witold A. Krzymien	Improving channel decoder performance on the CDMA forward link.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
20	Fei Sun, Tong Zhang 0002	Parallel high-throughput limited search trellis decoder VLSI design.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
20	Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson	A reconfigurable, power-efficient adaptive Viterbi decoder.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
20	Libero Dinoi, Sergio Benedetto	Variable-size interleaver design for parallel turbo decoder architectures.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
20	Massimo Rovini, Nicola E. L'Insalata, Francesco Rossi, Luca Fanucci	VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes.	DSD	2005	DBLP DOI BibTeX RDF
20	Lei Yang 0019, Manyuan Shen, Hui Liu 0011, C.-J. Richard Shi	An FPGA implementation of low-density parity-check code decoder with multi-rate capability.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Imran Ahmed 0001, Tughrul Arslan, Sajid Baloch, Ian Underwood, Robin Woodburn	Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication.	IPDPS	2005	DBLP DOI BibTeX RDF
20	Jing Ma 0006, Xinming Huang 0001	A System-on-Programmable Chip Approach for MIMO Sphere Decoder.	FCCM	2005	DBLP DOI BibTeX RDF
20	Yanxing Zeng, Qinye Yin 0001, Le Ding, Jianguo Zhang	DOA-Matrix Decoder for STBC-MC-CDMA Systems.	ICN (2)	2005	DBLP DOI BibTeX RDF
20	To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen	Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
20	In-Cheol Park, Se-Hyeon Kang	Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee	An H.264/AVC decoder with 4×4-block level pipeline.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Zhongfeng Wang, Qingwei Jia	Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala	256-State Rate 1/2 Viterbi Decoder on TTA Processor.	ASAP	2005	DBLP DOI BibTeX RDF
20	Syed Masood Ali, Rabin Raut, Mohamad Sawan	A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture.	IWSOC	2005	DBLP DOI BibTeX RDF
20	Khairul Munadi, Masayuki Kurosaki, Kiyoshi Nishikawa, Hitoshi Kiya	Efficient packet loss protection for JPEG2000 images enabling backward compatibility with a standard decoder.	ICIP	2004	DBLP DOI BibTeX RDF
20	Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens	Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements.	SAMOS	2004	DBLP DOI BibTeX RDF
20	Sophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine	Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA.	ISVLSI	2004	DBLP DOI BibTeX RDF
20	Recep O. Ozdag, Peter A. Beerel	A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates.	ASYNC	2004	DBLP DOI BibTeX RDF
20	Hyongsuk Kim, Hongrak Son, Tamás Roska, Leon O. Chua	Very high speed Viterbi decoder with circularly connected analog CNN cell array.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
20	Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley	Designing a High Speed Decoder for Cyclic Codes.	IOLTS	2004	DBLP DOI BibTeX RDF
20	Philipp Koehn	Pharaoh: A Beam Search Decoder for Phrase-Based Statistical Machine Translation Models.	AMTA	2004	DBLP DOI BibTeX RDF
20	Xun Liu, Marios C. Papaefthymiou	Design of a 20-mb/s 256-state Viterbi decoder.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
20	Jaeyoung Kwak, Sook Min Park, Sang-Sic Yoon, Kwyro Lee	Implementation of a parallel turbo decoder with dividable interleaver.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
20	Zhongfeng Wang, Yiyan Tang, Yuke Wang	Low hardware complexity parallel turbo decoder architecture.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
20	Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke	Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory.	DATE	2002	DBLP DOI BibTeX RDF
20	Abdulfattah Mohammad Obeid, Alberto García Ortiz, Ralf Ludewig, Manfred Glesner	Prototyping of a High Performance Generic Viterbi Decoder.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
20	Zhipei Chi, Keshab K. Parhi	High speed VLSI architecture design for block turbo decoder.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
20	Dongxiao Li, Qingdong Yao, Peng Liu 0016, Li Zhou	A bus arbitration scheme for HDTV decoder SoC.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
20	Kaharudin Dimyati, M. F. Ismail	Implementing a reconfigurable MAP decoder on a soft core processor system.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
20	L. Zhou, Q. D. Yao, P. Liu, D. X. Li	Influence of buffers on RISC core performance [HDTV source decoder system].	APCCAS (2)	2002	DBLP DOI BibTeX RDF
20	Xun Liu, Marios C. Papaefthymiou	Design of a high-throughput low-power IS95 Viterbi decoder.	DAC	2002	DBLP DOI BibTeX RDF	bus reduction, communications, pipelining