Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Gaurav Kumar Bharti, Jayanta Kumar Rakshit |
Design of all-optical JK, SR and T flip-flops using micro-ring resonator-based optical switch. |
Photonic Netw. Commun. |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Sahel Sahhaf, Abhishek Dixit, Wouter Tavernier, Didier Colle, Mario Pickavet, Piet Demeester |
All-optical tree-based greedy router using optical logic gates and optical flip-flops. |
Photonic Netw. Commun. |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Arunkumar Vijayan, Saman Kiamehr, Fabian Oboril, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori |
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Riadul Islam |
Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops. |
J. Electron. Test. |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Inhak Han, Youngsoo Shin |
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. |
ACM Trans. Design Autom. Electr. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami |
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Chuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh |
Clustering of flip-flops for useful-skew clock tree synthesis. |
ASP-DAC |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Mehrdad Biglari, Tobias Lieske, Dietmar Fey |
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. |
NANOARCH |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Sandeep Krishna Thirumala, Arnab Raha, Hrishikesh Jayakumar, Kaisheng Ma, Narayanan Vijaykrishnan, Vijay Raghunathan, Sumeet Kumar Gupta |
Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems. |
ISLPED |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory |
An LSSD Compliant Scan Cell for Flip-Flops. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti |
Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Mili Ghosh, Debarka Mukhopadhyay, Paramartha Dutta |
Energy Efficient Designing Approach of Flip-Flops Using 2-Dot 1-Electron QCA. |
CICBA (1) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori |
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops. |
IEEE Trans. Very Large Scale Integr. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Sébastien Ordas, Ludovic Guillaume-Sage, Philippe Maurine |
Electromagnetic fault injection: the curse of flip-flops. |
J. Cryptogr. Eng. |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima |
Applying Razor Flip-Flops to SRAM Read Circuits. |
IEICE Trans. Electron. |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Usman Khalid, Antonio Mastrandrea, Mauro Olivieri |
Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
30 | Shiva Taghipour, Rahebeh Niaraki Asli |
Aging comparative analysis of high-performance FinFET and CMOS flip-flops. |
Microelectron. Reliab. |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Xueqing Li, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Meng-Fan Chang, Yongpan Liu, Suman Datta, Vijaykrishnan Narayanan |
Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Yunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski |
Evaluation and analysis of single-phase clock flip-flops for NTV applications. |
PATMOS |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Masaru Kudo, Kimiyoshi Usami |
Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. |
NVMSA |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Arunkumar Vijayan, Saman Kiamehr, Fabian Oboril, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori |
Workload-aware static aging monitoring of timing-critical flip-flops. |
ASP-DAC |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale |
Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers. |
ECCTD |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Mehrdad Biglari, Dietmar Fey |
Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. |
MEMSYS |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Chinmay Deshpande, Bilgiday Yuce, Leyla Nazhandali, Patrick Schaumont |
Employing dual-complementary flip-flops to detect EMFI attacks. |
AsianHOST |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle |
Reliability of computing systems: From flip flops to variables. |
IOLTS |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Yuwen Dave Lin, Charles H.-P. Wen, Herming Chiueh |
Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops. |
ACM Great Lakes Symposium on VLSI |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens |
An analytical model for interdependent setup/hold-time characterization of flip-flops. |
ISQED |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Xijiang Lin |
On applying scan based structural test for designs with dual-edge triggered flip-flops. |
ITC |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Jasmine Kaur Gulati, Bhanu Prakash, Sumit Jagdish Darak |
An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula |
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. |
IEEE Trans. Very Large Scale Integr. Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Liang Geng, Jizhong Shen, Congyuan Xu |
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. |
IET Comput. Digit. Tech. |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Bingbing Xia, Jun Wu, Hongjin Liu, Kai Zhou, Zhifu Miao |
Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process. |
J. Circuits Syst. Comput. |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol |
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. |
Microelectron. J. |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Myeong-Eun Hwang, Sungoh Kwon |
DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling. |
J. Electr. Comput. Eng. |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Mahendra Sakare, Sadhu Pavan Kumar, Shalabh Gupta |
Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits. |
IEEE Trans. Circuits Syst. II Express Briefs |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Stepan Lapshev, S. M. Rezaul Hasan |
New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Takeo Katayama, Kazuya Nakao, Daisuke Hayashi, Hitoshi Kawaguchi |
Flip-flops using polarization bistable VCSEL with AND-gate functionality by two wavelength inputs. |
IEICE Electron. Express |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Xunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu |
Design of latches and flip-flops using emerging tunneling devices. |
DATE |
2016 |
DBLP BibTeX RDF |
|
30 | Ghaith Tarawneh, Andrey Mokhov, Alex Yakovlev |
Formal verification of clock domain crossing using gate-level models of metastable flip-flops. |
DATE |
2016 |
DBLP BibTeX RDF |
|
30 | Hyoungseok Moon, Taewhan Kim |
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization. |
ASP-DAC |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Dongyoun Yi, Taewhan Kim |
Allocation of multi-bit flip-flops in logic synthesis for power optimization. |
ICCAD |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Naoya Onizawa, Takahiro Hanyu |
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. |
NEWCAS |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Nenad Jovanovic, Olivier Thomas, Elisa Vianello, Bosko Nikolic, Lirida A. B. Naviner |
Design considerations for reliable OxRAM-based non-volatile flip-flops in 28nm FD-SOI technology. |
ISCAS |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Shaahin Angizi, Samira Sayedsalehi, Arman Roohi, Nader Bagherzadeh, Keivan Navi |
Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops. |
J. Circuits Syst. Comput. |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Ramin Razmdideh, Mohsen Saneei |
Two novel low power and very high speed pulse triggered flip-flops. |
Int. J. Circuit Theory Appl. |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Ruiqiang Song, Shuming Chen, Yibai He, Yankang Du |
Flip-flops soft error rate evaluation approach considering internal single-event transient. |
Sci. China Inf. Sci. |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Debarka Mukhopadhyay, Paramartha Dutta |
A study on energy optimized 4 dot 2 electron two dimensional quantum dot cellular automata logical reversible flip-flops. |
Microelectron. J. |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Usman Khalid, Antonio Mastrandrea, Mauro Olivieri |
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. |
Microelectron. Reliab. |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Vladimir Petrovic, Milos Krstic |
Design Flow for Radhard TMR Flip-Flops. |
DDECS |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis 0001 |
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim |
Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. |
VLSI-SoC |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Jerome Cox, George Engel, David M. Zar, Ian W. Jones |
Synchronizers and Data Flip-Flops are Different. |
ASYNC |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Gaetano Palumbo, Elio Consoli |
PVT variations in differential flip-flops: A comparative analysis. |
ECCTD |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet |
4 Sub-/near-threshold flip-flops with application to frequency dividers. |
ECCTD |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Alexandro Giron-Allende, Victor Avendaño, Esteban Martinez Guerrero |
A design methodology using flip-flops controlled by PVT variation detection. |
LASCAS |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Comparative analysis of the robustness of master-slave flip-flops against variations. |
ICECS |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Osama Abdelkader, Hassan Mostafa, Hamdy Abd Elhamid, Ahmed M. Soliman |
Impact of technology scaling on the minimum energy point for FinFET based flip-flops. |
ICECS |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Gaetano Palumbo, Elio Consoli |
Variability budgetin pulsed flip-flops. |
NEWCAS |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Patrick Nsengiyumva, Qiaoyan Yu |
Investigation of single-event upsets in dynamic logic based flip-flops. |
ISCAS |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif |
Analysis and optimization of flip-flops under process and runtime variations. |
ISQED |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Yasmin Ammar, Sadok Bdiri, Faouzi Derbel |
An ultra-low power wake up receiver with flip flops based address decoder. |
SSD |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Christoph Werner, Benedikt Backs, Martin Wirnshofer, Doris Schmitt-Landsiedel |
Resilience and yield of flip-flops in future CMOS technologies under process variations and aging. |
IET Circuits Devices Syst. |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Jitendra Kanungo, S. Dasgupta |
Sinusoidal Clocked Sense-amplifier-Based Energy Recovery flip-Flops. |
J. Circuits Syst. Comput. |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Mariam Zomorodi Moghadam, Keivan Navi, Mahmood Kalemati |
A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits. |
Comput. Syst. Sci. Eng. |
2014 |
DBLP BibTeX RDF |
|
30 | P. A. Gowri Sankar, K. Udhayakumar |
Ternary Flip-Flops Based on Emerging Sub-32 nm Technology Nodes. |
J. Low Power Electron. |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Shmuel Wimer, Arye Albahari |
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol |
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. |
PATMOS |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Usman Khalid, Antonio Mastrandrea, Mauro Olivieri |
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. |
DSD |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Edward Jung, Chih-Cheng Hung, Seonho Choi |
FSM watermarks based on ordering of flip flops. |
RACS |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Magne Voernes, Trond Ytterdal, Snorre Aunet |
Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. |
NORCHIP |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Marco Lanuzza, Ramiro Taco |
Improving speed and power characteristics of pulse-triggered flip-flops. |
LASCAS |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Masashi Imai, Tomohiro Yoneda |
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. |
ISCAS |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Mahendra Sakare, Shalabh Gupta |
A high-speed PRBS generator using flip-flops employing feedback for distributed equalization. |
ISCAS |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera |
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. |
SoCC |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark |
Methodology to optimize critical node separation in hardened flip-flops. |
ISQED |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Seyed Ebrahim Esmaeili, Asim J. Al-Khalili |
10 GHz throughput FinFET dual-edge triggered flip-flops. |
CCECE |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner |
Reliability-aware delay faults evaluation of CMOS flip-flops. |
MIXDES |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Ajay N. Bhoj, Niraj K. Jha |
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. |
IEEE Trans. Very Large Scale Integr. Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang |
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. |
IEEE Trans. Very Large Scale Integr. Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Naoya Okada, Yuichi Nakamura 0002, Shinji Kimura |
Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Keisuke Inoue, Mineo Kaneko |
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Hamed Abrishami, Safar Hatami, Massoud Pedram |
Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip-Flops Under the Negative Bias Temperature Instability Effect. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Marco Lanuzza |
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops. |
J. Low Power Electron. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas |
BTI, HCI and TDDB aging impact in flip-flops. |
Microelectron. Reliab. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Sheng Yang 0003, S. Saqib Khursheed, Bashir M. Al-Hashimi, David Flynn, Geoff V. Merrett |
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Ramen Dutta, Eric A. M. Klumperink, Xiang Gao 0002, Zhiyu Ru, Ronan A. R. van der Zee, Bram Nauta |
Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic. |
IEEE Trans. Circuits Syst. II Express Briefs |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Xiaowen Wang, William H. Robinson |
Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Mohamed O. Shaker, Magdy A. Bayoumi |
Novel clock gating techniques for low power flip-flops and its applications. |
MWSCAS |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman |
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. |
DATE |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas |
A methodology to evaluate the aging impact on flip-flops performance. |
SBCCI |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Taehui Na, Kyungho Ryu, Jisu Kim, Seung-Hyuk Kang, Seong-Ook Jung |
A comparative study of STT-MTJ based non-volatile flip-flops. |
ISCAS |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Min-Su Kim, Hyoungwook Lee, Jin-Soo Park, Chunghee Kim, Juhyun Kang, Ken Shin, Emil Kagramanyan, Gunok Jung, Ukrae Cho, Youngmin Shin, Jae-Cheol Son |
Scan-controlled pulse flip-flops for mobile application processors. |
ISCAS |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat |
An efficient metric of setup time for pulsed flip-flops based on output transition time. |
ICICDT |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Inhak Han, Youngsoo Shin |
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. |
ICICDT |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Adrian Evans, Michael Nicolaidis, Shi-Jie Wen, Thiago Asis |
Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flops. |
ISQED |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao |
Testing retention flip-flops in power-gated designs. |
VTS |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Guoqiang Hang, Xiaohui Hu, Danyan Zhang, Yang Yang 0013, Xiaohu You 0001 |
Novel Differential Flip-Flops Using Neuron-MOS Transistors. |
DASC |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Guoqiang Hang, Xiaohui Hu, Hongli Zhu, Xiaohu You 0001 |
Differential Edge-Triggered Flip-Flops Using Neuron-MOS Transistors. |
CIS |
2013 |
DBLP DOI BibTeX RDF |
|