Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Gaurav Kumar Bharti, Jayanta Kumar Rakshit |
Design of all-optical JK, SR and T flip-flops using micro-ring resonator-based optical switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 35(3), pp. 381-391, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Sahel Sahhaf, Abhishek Dixit, Wouter Tavernier, Didier Colle, Mario Pickavet, Piet Demeester |
All-optical tree-based greedy router using optical logic gates and optical flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 35(1), pp. 109-121, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Arunkumar Vijayan, Saman Kiamehr, Fabian Oboril, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori |
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10), pp. 2098-2110, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Riadul Islam |
Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 34(4), pp. 471-485, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Inhak Han, Youngsoo Shin |
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 23(5), pp. 61:1-61:21, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami |
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018, pp. 1-6, 2018, IEEE, 978-1-7281-1968-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Chuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh |
Clustering of flip-flops for useful-skew clock tree synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 507-512, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Mehrdad Biglari, Tobias Lieske, Dietmar Fey |
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018, Athens, Greece, July 17-19, 2018, pp. 19-24, 2018, ACM, 978-1-4503-5815-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Sandeep Krishna Thirumala, Arnab Raha, Hrishikesh Jayakumar, Kaisheng Ma, Narayanan Vijaykrishnan, Vijay Raghunathan, Sumeet Kumar Gupta |
Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2018, Seattle, WA, USA, July 23-25, 2018, pp. 31:1-31:6, 2018, ACM, 978-1-4503-5704-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory |
An LSSD Compliant Scan Cell for Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti |
Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Mili Ghosh, Debarka Mukhopadhyay, Paramartha Dutta |
Energy Efficient Designing Approach of Flip-Flops Using 2-Dot 1-Electron QCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICBA (1) ![In: Computational Intelligence, Communications, and Business Analytics - Second International Conference, CICBA 2018, Kalyani, India, July 27-28, 2018, Revised Selected Papers, Part I, pp. 477-490, 2018, Springer, 978-981-13-8577-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori |
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(4), pp. 1421-1432, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Sébastien Ordas, Ludovic Guillaume-Sage, Philippe Maurine |
Electromagnetic fault injection: the curse of flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptogr. Eng. ![In: J. Cryptogr. Eng. 7(3), pp. 183-197, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima |
Applying Razor Flip-Flops to SRAM Read Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 100-C(3), pp. 245-258, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Usman Khalid, Antonio Mastrandrea, Mauro Olivieri |
Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1712.06934, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
30 | Shiva Taghipour, Rahebeh Niaraki Asli |
Aging comparative analysis of high-performance FinFET and CMOS flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 69, pp. 52-59, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Xueqing Li, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Meng-Fan Chang, Yongpan Liu, Suman Datta, Vijaykrishnan Narayanan |
Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(11), pp. 2907-2919, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Yunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski |
Evaluation and analysis of single-phase clock flip-flops for NTV applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6462-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Masaru Kudo, Kimiyoshi Usami |
Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NVMSA ![In: IEEE 6th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017, Hsinchu, Taiwan, August 16-18, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-1768-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Arunkumar Vijayan, Saman Kiamehr, Fabian Oboril, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori |
Workload-aware static aging monitoring of timing-critical flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, pp. 176-181, 2017, IEEE, 978-1-5090-1558-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale |
Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 2017 European Conference on Circuit Theory and Design, ECCTD 2017, Catania, Italy, September 4-6, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-3974-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Mehrdad Biglari, Dietmar Fey |
Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017, pp. 217-222, 2017, ACM, 978-1-4503-5335-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Chinmay Deshpande, Bilgiday Yuce, Leyla Nazhandali, Patrick Schaumont |
Employing dual-complementary flip-flops to detect EMFI attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsianHOST ![In: 2017 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2017, Beijing, China, October 19-20, 2017, pp. 109-114, 2017, IEEE Computer Society, 978-1-5386-1421-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle |
Reliability of computing systems: From flip flops to variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017, pp. 196-198, 2017, IEEE, 978-1-5386-0352-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Yuwen Dave Lin, Charles H.-P. Wen, Herming Chiueh |
Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017, pp. 197-202, 2017, ACM, 978-1-4503-4972-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens |
An analytical model for interdependent setup/hold-time characterization of flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, CA, USA, March 14-15, 2017, pp. 209-214, 2017, IEEE, 978-1-5090-5404-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Xijiang Lin |
On applying scan based structural test for designs with dual-edge triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-3413-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Jasmine Kaur Gulati, Bhanu Prakash, Sumit Jagdish Darak |
An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 581-593, 2017, Springer, 978-981-10-7469-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula |
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(9), pp. 2873-2886, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Liang Geng, Jizhong Shen, Congyuan Xu |
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 10(4), pp. 193-201, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Bingbing Xia, Jun Wu, Hongjin Liu, Kai Zhou, Zhifu Miao |
Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 25(12), pp. 1650163:1-1650163:19, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol |
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 57, pp. 76-86, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Myeong-Eun Hwang, Sungoh Kwon |
DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2016, pp. 8268917:1-8268917:10, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Mahendra Sakare, Sadhu Pavan Kumar, Shalabh Gupta |
Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(8), pp. 768-772, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Stepan Lapshev, S. M. Rezaul Hasan |
New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10), pp. 1673-1681, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Takeo Katayama, Kazuya Nakao, Daisuke Hayashi, Hitoshi Kawaguchi |
Flip-flops using polarization bistable VCSEL with AND-gate functionality by two wavelength inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 13(5), pp. 20160064, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Xunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu |
Design of latches and flip-flops using emerging tunneling devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 367-372, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
30 | Ghaith Tarawneh, Andrey Mokhov, Alex Yakovlev |
Formal verification of clock domain crossing using gate-level models of metastable flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 1060-1065, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
30 | Hyoungseok Moon, Taewhan Kim |
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016, pp. 268-273, 2016, IEEE, 978-1-4673-9569-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Dongyoun Yi, Taewhan Kim |
Allocation of multi-bit flip-flops in logic synthesis for power optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016, pp. 33, 2016, ACM, 978-1-4503-4466-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Naoya Onizawa, Takahiro Hanyu |
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 14th IEEE International New Circuits and Systems Conference, NEWCAS 2016, Vancouver, BC, Canada, June 26-29, 2016, pp. 1-4, 2016, IEEE, 978-1-4673-8900-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Nenad Jovanovic, Olivier Thomas, Elisa Vianello, Bosko Nikolic, Lirida A. B. Naviner |
Design considerations for reliable OxRAM-based non-volatile flip-flops in 28nm FD-SOI technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 1146-1149, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Shaahin Angizi, Samira Sayedsalehi, Arman Roohi, Nader Bagherzadeh, Keivan Navi |
Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(10), pp. 1550153:1-1550153:17, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Ramin Razmdideh, Mohsen Saneei |
Two novel low power and very high speed pulse triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 43(12), pp. 1925-1934, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Ruiqiang Song, Shuming Chen, Yibai He, Yankang Du |
Flip-flops soft error rate evaluation approach considering internal single-event transient. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 58(6), pp. 1-12, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Debarka Mukhopadhyay, Paramartha Dutta |
A study on energy optimized 4 dot 2 electron two dimensional quantum dot cellular automata logical reversible flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 46(6), pp. 519-530, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Usman Khalid, Antonio Mastrandrea, Mauro Olivieri |
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(12), pp. 2614-2626, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3), pp. 835-843, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8), pp. 2035-2043, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Vladimir Petrovic, Milos Krstic |
Design Flow for Radhard TMR Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015, pp. 203-208, 2015, IEEE Computer Society, 978-1-4799-6779-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis 0001 |
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, pp. 521-526, 2015, IEEE Computer Society, 978-1-4799-8719-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim |
Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 159-164, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Jerome Cox, George Engel, David M. Zar, Ian W. Jones |
Synchronizers and Data Flip-Flops are Different. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 21st IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2015, Mountain View, CA, USA, May 4-6, 2015, pp. 19-20, 2015, IEEE Computer Society, 978-1-4799-8716-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Gaetano Palumbo, Elio Consoli |
PVT variations in differential flip-flops: A comparative analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-9877-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet |
4 Sub-/near-threshold flip-flops with application to frequency dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-9877-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Alexandro Giron-Allende, Victor Avendaño, Esteban Martinez Guerrero |
A design methodology using flip-flops controlled by PVT variation detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8332-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Comparative analysis of the robustness of master-slave flip-flops against variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 117-120, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Osama Abdelkader, Hassan Mostafa, Hamdy Abd Elhamid, Ahmed M. Soliman |
Impact of technology scaling on the minimum energy point for FinFET based flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 462-465, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Massimo Alioto, Gaetano Palumbo, Elio Consoli |
Variability budgetin pulsed flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8893-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Patrick Nsengiyumva, Qiaoyan Yu |
Investigation of single-event upsets in dynamic logic based flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 818-821, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif |
Analysis and optimization of flip-flops under process and runtime variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 191-196, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Yasmin Ammar, Sadok Bdiri, Faouzi Derbel |
An ultra-low power wake up receiver with flip flops based address decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSD ![In: 12th IEEE International Multi-Conference on Systems, Signals & Devices, SSD 2015, Mahdia, Tunisia, March 16-19, 2015, pp. 1-5, 2015, IEEE, 978-1-4799-1758-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Christoph Werner, Benedikt Backs, Martin Wirnshofer, Doris Schmitt-Landsiedel |
Resilience and yield of flip-flops in future CMOS technologies under process variations and aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 8(1), pp. 19-26, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Jitendra Kanungo, S. Dasgupta |
Sinusoidal Clocked Sense-amplifier-Based Energy Recovery flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 23(5), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Mariam Zomorodi Moghadam, Keivan Navi, Mahmood Kalemati |
A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Syst. Sci. Eng. ![In: Comput. Syst. Sci. Eng. 29(3), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
30 | P. A. Gowri Sankar, K. Udhayakumar |
Ternary Flip-Flops Based on Emerging Sub-32 nm Technology Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 10(4), pp. 602-616, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Shmuel Wimer, Arye Albahari |
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5), pp. 1465-1472, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol |
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014, pp. 1-7, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Usman Khalid, Antonio Mastrandrea, Mauro Olivieri |
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, August 27-29, 2014, pp. 488-495, 2014, IEEE Computer Society, 978-1-4799-5793-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Edward Jung, Chih-Cheng Hung, Seonho Choi |
FSM watermarks based on ordering of flip flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RACS ![In: Proceedings of the 2014 Conference on Research in Adaptive and Convergent Systems, RACS 2014, Towson, Maryland, USA, October 5-8, 2014, pp. 258-262, 2014, ACM, 978-1-4503-3060-2. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Magne Voernes, Trond Ytterdal, Snorre Aunet |
Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Marco Lanuzza, Ramiro Taco |
Improving speed and power characteristics of pulse-triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, February 25-28, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Masashi Imai, Tomohiro Yoneda |
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 141-144, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Mahendra Sakare, Shalabh Gupta |
A high-speed PRBS generator using flip-flops employing feedback for distributed equalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 746-749, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera |
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 27th IEEE International System-on-Chip Conference, SOCC 2014, Las Vegas, NV, USA, September 2-5, 2014, pp. 42-47, 2014, IEEE, 978-1-4799-3378-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark |
Methodology to optimize critical node separation in hardened flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pp. 486-490, 2014, IEEE, 978-1-4799-3945-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Seyed Ebrahim Esmaeili, Asim J. Al-Khalili |
10 GHz throughput FinFET dual-edge triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE 27th Canadian Conference on Electrical and Computer Engineering, CCECE 2014, Toronto, ON, Canada, May 4-7, 2014, pp. 1-4, 2014, IEEE, 978-1-4799-3099-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner |
Reliability-aware delay faults evaluation of CMOS flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2014, Lviv, Ukraine, June 19-21, 2014, pp. 385-389, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Ajay N. Bhoj, Niraj K. Jha |
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(11), pp. 1975-1988, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang |
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(4), pp. 624-635, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Naoya Okada, Yuichi Nakamura 0002, Shinji Kimura |
Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6), pp. 1264-1272, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Keisuke Inoue, Mineo Kaneko |
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(8), pp. 1712-1722, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Hamed Abrishami, Safar Hatami, Massoud Pedram |
Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip-Flops Under the Negative Bias Temperature Instability Effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6), pp. 869-881, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Marco Lanuzza |
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 9(4), pp. 445-451, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas |
BTI, HCI and TDDB aging impact in flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 53(9-11), pp. 1355-1359, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Sheng Yang 0003, S. Saqib Khursheed, Bashir M. Al-Hashimi, David Flynn, Geoff V. Merrett |
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11), pp. 2953-2961, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Ramen Dutta, Eric A. M. Klumperink, Xiang Gao 0002, Zhiyu Ru, Ronan A. R. van der Zee, Bram Nauta |
Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 60-II(7), pp. 422-426, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Xiaowen Wang, William H. Robinson |
Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9), pp. 2401-2411, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Mohamed O. Shaker, Magdy A. Bayoumi |
Novel clock gating techniques for low power flip-flops and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 420-424, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman |
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 1077-1082, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas |
A methodology to evaluate the aging impact on flip-flops performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 26th Symposium on Integrated Circuits and Systems Design, SBCCI 2013, Curitiba, Brazil, September 2-6, 2013, pp. 1-6, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Taehui Na, Kyungho Ryu, Jisu Kim, Seung-Hyuk Kang, Seong-Ook Jung |
A comparative study of STT-MTJ based non-volatile flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, pp. 109-112, 2013, IEEE, 978-1-4673-5760-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Min-Su Kim, Hyoungwook Lee, Jin-Soo Park, Chunghee Kim, Juhyun Kang, Ken Shin, Emil Kagramanyan, Gunok Jung, Ukrae Cho, Youngmin Shin, Jae-Cheol Son |
Scan-controlled pulse flip-flops for mobile application processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, pp. 769-772, 2013, IEEE, 978-1-4673-5760-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat |
An efficient metric of setup time for pulsed flip-flops based on output transition time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: Proceedings of 2013 International Conference on IC Design & Technology, ICICDT 2013, Pavia, Italy, May 29-31, 2013, pp. 9-12, 2013, IEEE, 978-1-4673-4740-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Inhak Han, Youngsoo Shin |
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: Proceedings of 2013 International Conference on IC Design & Technology, ICICDT 2013, Pavia, Italy, May 29-31, 2013, pp. 17-20, 2013, IEEE, 978-1-4673-4740-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Adrian Evans, Michael Nicolaidis, Shi-Jie Wen, Thiago Asis |
Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013, pp. 727-732, 2013, IEEE, 978-1-4673-4951-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao |
Testing retention flip-flops in power-gated designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, pp. 1-6, 2013, IEEE Computer Society, 978-1-4673-5542-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Guoqiang Hang, Xiaohui Hu, Danyan Zhang, Yang Yang 0013, Xiaohu You 0001 |
Novel Differential Flip-Flops Using Neuron-MOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASC ![In: IEEE 11th International Conference on Dependable, Autonomic and Secure Computing, DASC 2013, Chengdu, China, December 21-22, 2013, pp. 264-268, 2013, IEEE Computer Society, 978-1-4799-3380-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Guoqiang Hang, Xiaohui Hu, Hongli Zhu, Xiaohu You 0001 |
Differential Edge-Triggered Flip-Flops Using Neuron-MOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS ![In: Ninth International Conference on Computational Intelligence and Security, CIS 2013, Emei Mountain, Sichan Province, China, December 14-15, 2013, pp. 313-317, 2013, IEEE Computer Society, 978-1-4799-2548-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|