Search results for "floorplan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Kotaro Terada, Masao Yanagisawa, Nozomu Togawa	A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration.	ISCAS	2015	DBLP DOI BibTeX RDF
18	Gaurav Narang, Alexander Fell, Prakhar Raj Gupta, Anuj Grover	Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems.	SoCC	2015	DBLP DOI BibTeX RDF
18	Shuo Wang, Yue Gao, Melvin A. Breuer	GlYFF: A framework for global yield and floorplan aware design optimization.	ISQED	2015	DBLP DOI BibTeX RDF
18	Zhehui Wang, Jiang Xu 0001, Xiaowen Wu, Yaoyao Ye, Wei Zhang 0012, Mahdi Nikdast, Xuan Wang 0001, Zhe Wang 0003	Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
18	Jackey Z. Yan, Natarajan Viswanathan, Chris Chu	An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
18	Chao Lu, Shaoli Liu, Lei Wang 0015, Longbing Zhang, Meng Wen	Archipelago: A Floorplan Optimized for Concurrent Multiple Applications on Network-on-Chip.	NAS	2014	DBLP DOI BibTeX RDF
18	Ricardo Cabral, Yasutaka Furukawa	Piecewise Planar and Compact Floorplan Reconstruction from Images.	CVPR	2014	DBLP DOI BibTeX RDF
18	Kotaro Terada, Masao Yanagisawa, Nozomu Togawa	A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration.	APCCAS	2014	DBLP DOI BibTeX RDF
18	Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa	A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs.	APCCAS	2014	DBLP DOI BibTeX RDF
18	Vivek S. Nandakumar, Malgorzata Marek-Sadowska	System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs.	DAC	2014	DBLP DOI BibTeX RDF
18	Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa	Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF
18	Kai Feng, Yaoyao Ye, Jiang Xu 0001	A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
18	Yifei Jiang, Xiang Yun, Xin Pan, Kun Li, Qin Lv, Robert P. Dick, Li Shang, Michael Hannigan	Hallway based automatic indoor floorplan construction using room fingerprints.	UbiComp	2013	DBLP DOI BibTeX RDF
18	Ahmad Movahedian Attar, M. Hamed Izadi, Maedeh Movahedian, Shantia Yarahmadian	Coverage Estimation in Floorplan Visual Sensor Networks.	BWCCA	2013	DBLP DOI BibTeX RDF
18	Debora Matos, Cezar Reinbrecht, Márcio Eduardo Kreutz, Gianluca Palermo, Luigi Carro, Altamiro Amadeu Susin	Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability.	ARC	2013	DBLP DOI BibTeX RDF
18	Minoru Iizuka, Hiroshi Saito	A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation.	NEWCAS	2013	DBLP DOI BibTeX RDF
18	Guoming Lai 0002, Xiaola Lin	Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique.	J. Supercomput.	2012	DBLP DOI BibTeX RDF
18	Dhiraj, Seema Verma, Rajesh Kumar 0002, Himanshu Choudhary	A enhanced algorithm for floorplan design using evolutionary technique.	Artif. Intell. Res.	2012	DBLP DOI BibTeX RDF
18	Hiroshi Tezuka, Kunihiro Fujiyoshi	An efficient solution space for floorplan of 3D-LSI.	ICECS	2012	DBLP DOI BibTeX RDF
18	Debora Matos, Cezar Reinbrecht, Gianluca Palermo, Jonathan Martinelli, Altamiro Amadeu Susin, Cristina Silvano, Luigi Carro	Floorplan-aware hierarchical NoC topology with GALS interfaces.	ISCAS	2012	DBLP DOI BibTeX RDF
18	Ignacio Arnaldo, Alessandro Vincenzi, José Luis Ayala, José Luis Risco-Martín, José Ignacio Hidalgo, Martino Ruggiero, David Atienza	Fast and scalable temperature-driven floorplan design in 3D MPSoCs.	LATW	2012	DBLP DOI BibTeX RDF
18	Antoni Roca 0001, Carles Hernández 0001, José Flich, Federico Silla, José Duato	Enabling High-Performance Crossbars through a Floorplan-Aware Design.	ICPP	2012	DBLP DOI BibTeX RDF
18	Dong Oh Son, Young Jin Park, Jin Woo Ahn, Jaehyung Park, Jong-Myon Kim, Cheol Hong Kim	Thermal-Aware Floorplan Schemes for Reliable 3D Multi-core Processors.	ICCSA (2)	2011	DBLP DOI BibTeX RDF
18	Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin	Thermal signature: a simple yet accurate thermal index for floorplan optimization.	DAC	2011	DBLP DOI BibTeX RDF
18	Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods.	ACM Trans. Reconfigurable Technol. Syst.	2010	DBLP DOI BibTeX RDF
18	Qiang Ma 0002, Evangeline F. Y. Young	Multivoltage Floorplan Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
18	Li Li, Yuchun Ma, Ning Xu 0006, Yu Wang 0002, Xianlong Hong	PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.	ASP-DAC	2010	DBLP DOI BibTeX RDF
18	Paul Falkenstern, Yuan Xie 0001, Yao-Wen Chang, Yu Wang 0002	Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.	ASP-DAC	2010	DBLP DOI BibTeX RDF
18	Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation.	ISCAS	2010	DBLP DOI BibTeX RDF
18	Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya	A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs.	ISCAS	2010	DBLP DOI BibTeX RDF
18	Xianwu Xing, Ching-Chuen Jong	Floorplan-Driven Multivoltage High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
18	Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu	Handling routability in floorplan design with twin binary trees.	Integr.	2009	DBLP DOI BibTeX RDF
18	Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi	Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
18	Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
18	Pritha Banerjee 0001, Susmita Sur-Kolay, Arijit Bishnu	Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
18	Hariharan Sankaran, Srinivas Katkoori	Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs.	ISVLSI	2009	DBLP DOI BibTeX RDF
18	Chia-Pin R. Liu	Floorplan Optimization for Hierarchical VLSI Design.	CAINE	2009	DBLP BibTeX RDF
18	Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic	Floorplan-based FPGA interconnect power estimation in DSP circuits.	SLIP	2009	DBLP DOI BibTeX RDF	fpga, low power, interconnects, power estimation
18	Hidenori Ohta, Kunihiro Fujiyoshi	Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection.	ISCAS	2009	DBLP DOI BibTeX RDF
18	Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini	A floorplan-aware interactive tool flow for NoC design and synthesis.	SoCC	2009	DBLP DOI BibTeX RDF
18	Evangeline F. Y. Young	Floorplan Representations.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
18	Tung-Chieh Chen, Yao-Wen Chang	Packing Floorplan Representations.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
18	Evangeline F. Y. Young	Slicing Floorplan Orientation.	Encyclopedia of Algorithms	2008	DBLP DOI BibTeX RDF
18	Yoji Kajitani	Floorplan and Placement.	Encyclopedia of Algorithms	2008	DBLP DOI BibTeX RDF
18	Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures.	IPSJ Trans. Syst. LSI Des. Methodol.	2008	DBLP DOI BibTeX RDF
18	Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong	Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
18	Toshihiko Takahashi, Ryo Fujimaki	Fujimaki-Takahashi Squeeze: Linear Time Construction of Constraint Graphs of Floorplan for a Given Permutation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
18	G. E. Livesey, H. A. Donegan	Using classical graph theory to generate non-isomorphic floorplan distributions in the measurement of egress complexity.	Math. Comput. Model.	2008	DBLP DOI BibTeX RDF
18	Abheek Saha	A fast and efficient two-dimensional frame composer for OFDMA WiMAX base-stations using floorplan slicing.	EW	2008	DBLP BibTeX RDF
18	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu	On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
18	Maolin Tang, Raymond Y. K. Lau	A Parallel Genetic Algorithm for Floorplan Area Optimization.	ISDA	2007	DBLP DOI BibTeX RDF
18	Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu	Using power gating techniques in area-array SoC floorplan design.	SoCC	2007	DBLP DOI BibTeX RDF
18	Lin Yu Tseng, Tuan-Yung Han	A Genetic Local Search Algorithm for the Floorplan Problem with Boundary Constraints.	GEM	2007	DBLP BibTeX RDF
18	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze	Accurate estimation of global buffer delay within a floorplan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Lei Cheng 0001, Martin D. F. Wong	Floorplan Design for Multimillion Gate FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Yosuke Kimura, Kenichi Ida	Improved genetic algorithm for VLSI floorplan design with non-slicing structure.	Comput. Ind. Eng.	2006	DBLP DOI BibTeX RDF
18	Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001	Reliability-Aware SOC Voltage Islands Partition and Floorplan.	ISVLSI	2006	DBLP DOI BibTeX RDF
18	Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai	Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation.	IEEE Congress on Evolutionary Computation	2006	DBLP DOI BibTeX RDF
18	Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu	Area-Driven White Space Distribution for Detailed Floorplan Design.	ICECS	2006	DBLP DOI BibTeX RDF
18	Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang	Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design.	SoCC	2006	DBLP DOI BibTeX RDF
18	Song Chen 0001, Takeshi Yoshimura	On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Chikaaki Kodama, Kunihiro Fujiyoshi	Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge.	IEICE Trans. Inf. Syst.	2005	DBLP DOI BibTeX RDF
18	Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi	A Graph Based Soft Module Handling in Floorplan.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
18	Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong	Simultaneous power supply planning and noise avoidance in floorplan design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
18	Renshen Wang, Sheqin Dong, Xianlong Hong	An improved P-admissible floorplan representation based on Corner Block List.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo	LB-packing-based floorplan design on DBL representation.	ICECS	2005	DBLP DOI BibTeX RDF
18	Jin-Tai Yan, Chia-Fang Lee, Tzu-Ya Wang	Floorplan-aware Steiner tree reconstruction for optimal buffer insertion.	ICECS	2005	DBLP DOI BibTeX RDF
18	Mario R. Casu, Luca Macchiarulo	Floorplan assisted data rate enhancement through wire pipelining: a real assessment.	ISPD	2005	DBLP DOI BibTeX RDF	through-put, systems-on-chip, floorplanning, wire pipelining
18	Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran	Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	Floorplan-aware automated synthesis of bus-based communication architectures.	DAC	2005	DBLP DOI BibTeX RDF	systems-on-chip, communication synthesis
18	Zhou Feng, Bo Yao, Chung-Kuan Cheng	Floorplan Representation in VLSI.	Handbook of Data Structures and Applications	2004	DBLP DOI BibTeX RDF
18	Subhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya	On Finding A Staircase Channel With Minimum Crossing Nets In A VLSI Floorplan.	J. Circuits Syst. Comput.	2004	DBLP DOI BibTeX RDF
18	Yosuke Kimura, Kenichi Ida	Floorplan design problem using improved genetic algorithm.	Artif. Life Robotics	2004	DBLP DOI BibTeX RDF
18	Yosuke Kimura, Kenichi Ida	Floorplan design problem using improved genetic algorithm.	Artif. Life Robotics	2004	DBLP DOI BibTeX RDF
18	Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu	Corner block list representation and its application to floorplan optimization.	IEEE Trans. Circuits Syst. II Express Briefs	2004	DBLP DOI BibTeX RDF
18	Yi-Lin Hsieh, Tsai-Ming Hsieh	A New Effective Congestion Model in Floorplan Design.	DATE	2004	DBLP DOI BibTeX RDF
18	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze	Accurate estimation of global buffer delay within a floorplan.	ICCAD	2004	DBLP DOI BibTeX RDF
18	Lei Cheng 0001, Martin D. F. Wong	Floorplan design for multi-million gate FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
18	Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai	S-sequence: a new floorplan representation method preserving room abutment relationships.	ISCAS (4)	2004	DBLP BibTeX RDF
18	Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou 0001, Yici Cai, Yongqiang Lu 0001	Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.	ISCAS (5)	2004	DBLP BibTeX RDF
18	Dongku Kang, Mark C. Johnson, Kaushik Roy 0001	Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan.	ISQED	2004	DBLP DOI BibTeX RDF
18	Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin 0001	Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
18	Teng-Sheng Moh, Tsu-Shuan Chang	Comments on "Handling soft modules in general nonslicing floorplan using Lagrangian relaxation".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
18	Vladimir G. Deineko, Gerhard J. Woeginger	Complexity and approximability results for slicing floorplan designs.	Eur. J. Oper. Res.	2003	DBLP DOI BibTeX RDF
18	Ana Maria de Almeida 0002, Rosália Rodrigues	Trees, slices, and wheels: On the floorplan area minimization problem.	Networks	2003	DBLP DOI BibTeX RDF
18	Keishi Sakanushi, Zhonglin Wu, Yoji Kajitani	Recognition of Floorplan by Parametric BSG for Reuse of Layout Design.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
18	Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh	A New Formulation for SOC Floorplan Area Minimization Problem.	DATE	2002	DBLP DOI BibTeX RDF
18	Chris C. N. Chu, Evangeline F. Y. Young	Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design.	DATE	2002	DBLP DOI BibTeX RDF
18	Minghorng Lai, D. F. Wong 0001	Slicing tree is a complete floorplan representation.	DATE	2001	DBLP DOI BibTeX RDF
18	En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang	Slicing floorplan design with boundary-constrained modules.	ISPD	2001	DBLP DOI BibTeX RDF
18	Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu	Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application.	ASP-DAC	2000	DBLP DOI BibTeX RDF
18	Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong	Floorplan area minimization using Lagrangian relaxation.	ISPD	2000	DBLP DOI BibTeX RDF
18	Ralph H. J. M. Otten	What is a floorplan?.	ISPD	2000	DBLP DOI BibTeX RDF
18	Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura	An enhanced perturbing algorithm for floorplan design using the O-tree representation.	ISPD	2000	DBLP DOI BibTeX RDF
18	Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu	Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.	ICCAD	2000	DBLP DOI BibTeX RDF
18	En-Cheng Liu, Tu-Hsing Lin, Ting-Chi Wang	On accelerating slicing floorplan design with boundary constraints.	ISCAS	2000	DBLP DOI BibTeX RDF
18	Priyalal Kulasinghe, Saïd Bettayeb	An optimal algorithm for layered wheel floorplan designs.	Networks	1999	DBLP DOI BibTeX RDF
18	Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura	An O-Tree Representation of Non-Slicing Floorplan and Its Applications.	DAC	1999	DBLP DOI BibTeX RDF
18	Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung	A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs.	DAC	1999	DBLP DOI BibTeX RDF
18	Tomonori Izumi, Atsushi Takahashi 0001, Yoji Kajitani	Air-Pressure-Model-Based Fast Algorithms for General Floorplan.	ASP-DAC	1998	DBLP DOI BibTeX RDF