Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Kotaro Terada, Masao Yanagisawa, Nozomu Togawa |
A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2129-2132, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Gaurav Narang, Alexander Fell, Prakhar Raj Gupta, Anuj Grover |
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015, pp. 105-110, 2015, IEEE, 978-1-4673-9094-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Shuo Wang, Yue Gao, Melvin A. Breuer |
GlYFF: A framework for global yield and floorplan aware design optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 70-76, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Zhehui Wang, Jiang Xu 0001, Xiaowen Wu, Yaoyao Ye, Wei Zhang 0012, Mahdi Nikdast, Xuan Wang 0001, Zhe Wang 0003 |
Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 63(6), pp. 1446-1459, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Jackey Z. Yan, Natarajan Viswanathan, Chris Chu |
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 19(3), pp. 29:1-29:25, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Chao Lu, Shaoli Liu, Lei Wang 0015, Longbing Zhang, Meng Wen |
Archipelago: A Floorplan Optimized for Concurrent Multiple Applications on Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: 9th IEEE International Conference on Networking, Architecture, and Storage, NAS 2014, Tianjin, China, August 6-8, 2014, pp. 252-258, 2014, IEEE Computer Society, 978-1-4799-4087-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Ricardo Cabral, Yasutaka Furukawa |
Piecewise Planar and Compact Floorplan Reconstruction from Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: 2014 IEEE Conference on Computer Vision and Pattern Recognition, CVPR 2014, Columbus, OH, USA, June 23-28, 2014, pp. 628-635, 2014, IEEE Computer Society, 978-1-4799-5118-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Kotaro Terada, Masao Yanagisawa, Nozomu Togawa |
A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki, Japan, November 17-20, 2014, pp. 248-251, 2014, IEEE, 978-1-4799-5230-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa |
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki, Japan, November 17-20, 2014, pp. 244-247, 2014, IEEE, 978-1-4799-5230-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Vivek S. Nandakumar, Malgorzata Marek-Sadowska |
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014, pp. 137:1-137:6, 2014, ACM, 978-1-4503-2730-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa |
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12), pp. 2597-2611, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Kai Feng, Yaoyao Ye, Jiang Xu 0001 |
A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(8-B), pp. 941-952, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Yifei Jiang, Xiang Yun, Xin Pan, Kun Li, Qin Lv, Robert P. Dick, Li Shang, Michael Hannigan |
Hallway based automatic indoor floorplan construction using room fingerprints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UbiComp ![In: The 2013 ACM International Joint Conference on Pervasive and Ubiquitous Computing, UbiComp '13, Zurich, Switzerland, September 8-12, 2013, pp. 315-324, 2013, ACM, 978-1-4503-1770-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Ahmad Movahedian Attar, M. Hamed Izadi, Maedeh Movahedian, Shantia Yarahmadian |
Coverage Estimation in Floorplan Visual Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BWCCA ![In: 2013 Eighth International Conference on Broadband and Wireless Computing, Communication and Applications, Compiegne, France, October 28-30, 2013, pp. 146-150, 2013, IEEE, 978-0-7695-5093-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Debora Matos, Cezar Reinbrecht, Márcio Eduardo Kreutz, Gianluca Palermo, Luigi Carro, Altamiro Amadeu Susin |
Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings, pp. 179-184, 2013, Springer, 978-3-642-36811-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Minoru Iizuka, Hiroshi Saito |
A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, France, June 16-19, 2013, pp. 1-4, 2013, IEEE, 978-1-4799-0618-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Guoming Lai 0002, Xiaola Lin |
Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 61(3), pp. 418-437, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Dhiraj, Seema Verma, Rajesh Kumar 0002, Himanshu Choudhary |
A enhanced algorithm for floorplan design using evolutionary technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Intell. Res. ![In: Artif. Intell. Res. 1(2), pp. 38-55, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Hiroshi Tezuka, Kunihiro Fujiyoshi |
An efficient solution space for floorplan of 3D-LSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 460-463, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Debora Matos, Cezar Reinbrecht, Gianluca Palermo, Jonathan Martinelli, Altamiro Amadeu Susin, Cristina Silvano, Luigi Carro |
Floorplan-aware hierarchical NoC topology with GALS interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 652-655, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Ignacio Arnaldo, Alessandro Vincenzi, José Luis Ayala, José Luis Risco-Martín, José Ignacio Hidalgo, Martino Ruggiero, David Atienza |
Fast and scalable temperature-driven floorplan design in 3D MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 13th Latin American Test Workshop, LATW 2012, Quito, Ecuador, April 10-13, 2012, pp. 1-6, 2012, IEEE Computer Society, 978-1-4673-2355-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Antoni Roca 0001, Carles Hernández 0001, José Flich, Federico Silla, José Duato |
Enabling High-Performance Crossbars through a Floorplan-Aware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 41st International Conference on Parallel Processing, ICPP 2012, Pittsburgh, PA, USA, September 10-13, 2012, pp. 269-278, 2012, IEEE Computer Society, 978-1-4673-2508-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Dong Oh Son, Young Jin Park, Jin Woo Ahn, Jaehyung Park, Jong-Myon Kim, Cheol Hong Kim |
Thermal-Aware Floorplan Schemes for Reliable 3D Multi-core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (2) ![In: Computational Science and Its Applications - ICCSA 2011 - International Conference, Santander, Spain, June 20-23, 2011. Proceedings, Part II, pp. 463-474, 2011, Springer, 978-3-642-21886-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin |
Thermal signature: a simple yet accurate thermal index for floorplan optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011, pp. 108-113, 2011, ACM, 978-1-4503-0636-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 4(1), pp. 3:1-3:23, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Qiang Ma 0002, Evangeline F. Y. Young |
Multivoltage Floorplan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4), pp. 607-617, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Li Li, Yuchun Ma, Ning Xu 0006, Yu Wang 0002, Xianlong Hong |
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 769-774, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Paul Falkenstern, Yuan Xie 0001, Yao-Wen Chang, Yu Wang 0002 |
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 169-174, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 921-924, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya |
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 925-928, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Xianwu Xing, Ching-Chuen Jong |
Floorplan-Driven Multivoltage High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009, pp. 156751:1-156751:10, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
Handling routability in floorplan design with twin binary trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 42(4), pp. 449-456, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi |
Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(8), pp. 1034-1047, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12), pp. 3169-3179, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Pritha Banerjee 0001, Susmita Sur-Kolay, Arijit Bishnu |
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5), pp. 651-661, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Hariharan Sankaran, Srinivas Katkoori |
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA, pp. 274-279, 2009, IEEE Computer Society, 978-0-7695-3684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Chia-Pin R. Liu |
Floorplan Optimization for Hierarchical VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAINE ![In: Proceedings of the ISCA 22nd International Conference on Computer Applications in Industry and Engineering, CAINE 2009, November 4-6, 2009, Hilton San Francisco Fisherman's Wharf, San Francisco, California, USA, pp. 114-119, 2009, ISCA, 978-1-880843-73-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
18 | Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic |
Floorplan-based FPGA interconnect power estimation in DSP circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 53-60, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, low power, interconnects, power estimation |
18 | Hidenori Ohta, Kunihiro Fujiyoshi |
Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 1731-1734, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini |
A floorplan-aware interactive tool flow for NoC design and synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings, pp. 379-382, 2009, IEEE, 978-1-4244-4940-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Evangeline F. Y. Young |
Floorplan Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Algorithms for Physical Design Automation ![In: Handbook of Algorithms for Physical Design Automation., 2008, Auerbach Publications, 978-0-8493-7242-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Tung-Chieh Chen, Yao-Wen Chang |
Packing Floorplan Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Algorithms for Physical Design Automation ![In: Handbook of Algorithms for Physical Design Automation., 2008, Auerbach Publications, 978-0-8493-7242-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Evangeline F. Y. Young |
Slicing Floorplan Orientation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Algorithms ![In: Encyclopedia of Algorithms - 2008 Edition, 2008, Springer, 978-0-387-30770-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yoji Kajitani |
Floorplan and Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Algorithms ![In: Encyclopedia of Algorithms - 2008 Edition, 2008, Springer, 978-0-387-30770-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 1, pp. 78-90, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong |
Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12), pp. 3443-3450, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Toshihiko Takahashi, Ryo Fujimaki |
Fujimaki-Takahashi Squeeze: Linear Time Construction of Constraint Graphs of Floorplan for a Given Permutation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4), pp. 1071-1076, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | G. E. Livesey, H. A. Donegan |
Using classical graph theory to generate non-isomorphic floorplan distributions in the measurement of egress complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Comput. Model. ![In: Math. Comput. Model. 48(1-2), pp. 1-10, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Abheek Saha |
A fast and efficient two-dimensional frame composer for OFDMA WiMAX base-stations using floorplan slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EW ![In: European Wireless 2008 - 14th European Wireless Conference 2008, Electronic Proceedings, 22-25 June 2008, Praque, Czech Republic., 2008, VDE-Verlag, 978-3-8007-3102-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
18 | Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu |
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 792-797, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Maolin Tang, Raymond Y. K. Lau |
A Parallel Genetic Algorithm for Floorplan Area Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA ![In: Seventh International Conference on Intelligent Systems Design and Applications, ISDA 2007, Rio de Janeiro, Brazil, October 20-24, 2007, pp. 801-806, 2007, IEEE Computer Society, 978-0-7695-2976-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu |
Using power gating techniques in area-array SoC floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2007 IEEE International SOC Conference, Tampere, Finland, November 19-21, 2007, pp. 233-236, 2007, IEEE, 978-1-4244-1592-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Lin Yu Tseng, Tuan-Yung Han |
A Genetic Local Search Algorithm for the Floorplan Problem with Boundary Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GEM ![In: Proceedings of the 2007 International Conference on Genetic and Evolutionary Methods, GEM 2007, June 25-28, 2007, Las Vegas, Nevada, USA, pp. 70-74, 2007, CSREA Press, 1-60132-038-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
18 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
Accurate estimation of global buffer delay within a floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 1140-1145, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Lei Cheng 0001, Martin D. F. Wong |
Floorplan Design for Multimillion Gate FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2795-2805, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Yosuke Kimura, Kenichi Ida |
Improved genetic algorithm for VLSI floorplan design with non-slicing structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Ind. Eng. ![In: Comput. Ind. Eng. 50(4), pp. 528-540, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Reliability-Aware SOC Voltage Islands Partition and Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 343-348, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai |
Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: IEEE International Conference on Evolutionary Computation, CEC 2006, part of WCCI 2006, Vancouver, BC, Canada, 16-21 July 2006, pp. 718-724, 2006, IEEE, 0-7803-9487-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu |
Area-Driven White Space Distribution for Detailed Floorplan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 1364-1367, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang |
Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006, pp. 211-214, 2006, IEEE, 0-7803-9781-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Song Chen 0001, Takeshi Yoshimura |
On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1867-1870, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Chikaaki Kodama, Kunihiro Fujiyoshi |
Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 88-D(7), pp. 1389-1396, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi |
A Graph Based Soft Module Handling in Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12), pp. 3390-3397, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong |
Simultaneous power supply planning and noise avoidance in floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), pp. 578-587, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Renshen Wang, Sheqin Dong, Xianlong Hong |
An improved P-admissible floorplan representation based on Corner Block List. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1115-1118, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo |
LB-packing-based floorplan design on DBL representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 12th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2005, Gammarth, Tunisia, December 11-14, 2005, pp. 1-4, 2005, IEEE, 978-9972-61-100-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Jin-Tai Yan, Chia-Fang Lee, Tzu-Ya Wang |
Floorplan-aware Steiner tree reconstruction for optimal buffer insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 12th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2005, Gammarth, Tunisia, December 11-14, 2005, pp. 1-4, 2005, IEEE, 978-9972-61-100-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Mario R. Casu, Luca Macchiarulo |
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 121-128, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
through-put, systems-on-chip, floorplanning, wire pipelining |
18 | Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran |
Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 463-468, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane |
Floorplan-aware automated synthesis of bus-based communication architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 565-570, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
systems-on-chip, communication synthesis |
18 | Zhou Feng, Bo Yao, Chung-Kuan Cheng |
Floorplan Representation in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Data Structures and Applications ![In: Handbook of Data Structures and Applications., 2004, Chapman and Hall/CRC, 978-1-58488-435-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Subhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya |
On Finding A Staircase Channel With Minimum Crossing Nets In A VLSI Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 13(5), pp. 1019-1038, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Yosuke Kimura, Kenichi Ida |
Floorplan design problem using improved genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Life Robotics ![In: Artif. Life Robotics 8(2), pp. 123-126, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Yosuke Kimura, Kenichi Ida |
Floorplan design problem using improved genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Life Robotics ![In: Artif. Life Robotics 8(2), pp. 123-126, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Corner block list representation and its application to floorplan optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 51-II(5), pp. 228-233, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Yi-Lin Hsieh, Tsai-Ming Hsieh |
A New Effective Congestion Model in Floorplan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1204-1209, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
Accurate estimation of global buffer delay within a floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 706-711, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Lei Cheng 0001, Martin D. F. Wong |
Floorplan design for multi-million gate FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 292-299, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai |
S-sequence: a new floorplan representation method preserving room abutment relationships. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 505-508, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
18 | Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou 0001, Yici Cai, Yongqiang Lu 0001 |
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 81-84, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
18 | Dongku Kang, Mark C. Johnson, Kaushik Roy 0001 |
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 98-103, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin 0001 |
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 679-686, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Teng-Sheng Moh, Tsu-Shuan Chang |
Comments on "Handling soft modules in general nonslicing floorplan using Lagrangian relaxation". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12), pp. 1684-1686, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Vladimir G. Deineko, Gerhard J. Woeginger |
Complexity and approximability results for slicing floorplan designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eur. J. Oper. Res. ![In: Eur. J. Oper. Res. 149(3), pp. 533-539, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ana Maria de Almeida 0002, Rosália Rodrigues |
Trees, slices, and wheels: On the floorplan area minimization problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks ![In: Networks 41(4), pp. 235-244, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Keishi Sakanushi, Zhonglin Wu, Yoji Kajitani |
Recognition of Floorplan by Parametric BSG for Reuse of Layout Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4), pp. 872-879, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
18 | Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh |
A New Formulation for SOC Floorplan Area Minimization Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1100, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Chris C. N. Chu, Evangeline F. Y. Young |
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1101, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Minghorng Lai, D. F. Wong 0001 |
Slicing tree is a complete floorplan representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 228-232, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang |
Slicing floorplan design with boundary-constrained modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 124-129, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu |
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, pp. 277-282, 2000, ACM, 0-7803-5974-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong |
Floorplan area minimization using Lagrangian relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 174-179, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Ralph H. J. M. Otten |
What is a floorplan?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 201-206, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura |
An enhanced perturbing algorithm for floorplan design using the O-tree representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 168-173, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, pp. 8-12, 2000, IEEE Computer Society, 0-7803-6448-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | En-Cheng Liu, Tu-Hsing Lin, Ting-Chi Wang |
On accelerating slicing floorplan design with boundary constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 399-402, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Priyalal Kulasinghe, Saïd Bettayeb |
An optimal algorithm for layered wheel floorplan designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks ![In: Networks 34(1), pp. 67-72, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura |
An O-Tree Representation of Non-Slicing Floorplan and Its Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 268-273, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung |
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 766-771, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Tomonori Izumi, Atsushi Takahashi 0001, Yoji Kajitani |
Air-Pressure-Model-Based Fast Algorithms for General Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, pp. 563-570, 1998, IEEE, 0-7803-4425-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|