Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Ting Yu 0008, Manfred Lenzen, Chris Dey, Jeremy Badcock |
Automatically Estimating and Updating Input-Output Tables. |
KES (2) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel |
A Compact and Accurate Gaussian Variate Generator. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Huapeng Wu |
Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew |
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ioannis D. Schizas, Georgios B. Giannakis, Stergios I. Roumeliotis, Alejandro Ribeiro |
Consensus in Ad Hoc WSNs With Noisy Links - Part II: Distributed Estimation and Smoothing of Random Signals. |
IEEE Trans. Signal Process. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ralf Laue 0002, Sorin A. Huss |
Parallel Memory Architecture for Elliptic Curve Cryptography over GF(p) Aimed at Efficient FPGA Implementation. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
FPGA, parallelization, elliptic curve cryptography, memory architecture |
15 | Arash Hariri, Arash Reyhani-Masoleh |
Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields. |
WAIFI |
2008 |
DBLP DOI BibTeX RDF |
Shifted polynomial basis, binary extension fields, digit-serial, multiplication |
15 | Xiaoying Wang 0001, Lars Hedrich |
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Guang Gong |
Sequences, DFT and Resistance against Fast Algebraic Attacks. |
SETA |
2008 |
DBLP DOI BibTeX RDF |
fast algebraic attack, bases, trace representations, stream ciphers, Discrete Fourier transform, polynomials, LFSR, m-sequences |
15 | Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng |
Direct sigma-delta modulated signal processing in FPGA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Fan Mo, Robert K. Brayton |
Placement based multiplier rewiring for cell-based designs. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado |
Applying speculation techniques to implement functional units. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Tzu-Yuan Kuo, Jinn-Shyan Wang |
A low-voltage latch-adder based tree multiplier. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Minhyeok Shin, Hanho Lee |
A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo |
Floating point multiplication rounding schemes for interval arithmetic. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Kayo Sakamoto, Masanori Nakagawa |
A Computational Model of Risk-Context-Dependent Inductive Reasoning Based on a Support Vector Machine. |
LKR |
2008 |
DBLP DOI BibTeX RDF |
corpus-based conceptual clustering, Support Vector Machines, context, natural language processing, risk, inductive reasoning |
15 | Samuel I. Daitch, Daniel A. Spielman |
Faster approximate lossy generalized flow via interior point algorithms. |
STOC |
2008 |
DBLP DOI BibTeX RDF |
approximation algorithms, linear programming, network flows, interior-point algorithms |
15 | Turki F. Al-Somani, Alaaeldin Amin |
High performance elliptic curve point operations with pipelined GF(2m) field multiplier. |
AICCSA |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Wei Xu 0001, Chunming Zhao, Peng Zhou, Yijin Yang |
Efficient Adaptive Resource Allocation for Multiuser OFDM Systems with Minimum Rate Constraints. |
ICC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Pierre L'Ecuyer |
Efficient and portable 32-bit random variate generators (1986). |
WSC |
2007 |
DBLP BibTeX RDF |
|
15 | Yoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke, Tsutomu Maruyama |
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Ming Z. Zhang, Vijayan K. Asari |
A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
2D convolution, log-domain computation, multiplier-less architecture, quadrant symmetric kernels, modularized optimization, FPGA based architecture |
15 | Liansheng Tan, Xiangjun Wang |
On IP Traffic Matrix Estimation. |
ICCCN |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Rahul Jain 0004, Preeti Ranjan Panda |
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Natalia A. Fernandez-Garcia, Víctor M. Brea 0001, Diego Cabello |
Area and Time Efficient Cellular Non-linear Networks. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Andrea Fantini, Alessandro Cabrini, Guido Torelli |
Impact of Control Signal Non-Idealties on Two-Phase Charge Pumps. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Kavallur Gopi Smitha, A. Prasad Vinod 0001 |
A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo |
A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Dong-Ho Lee, Jong-Soo Oh |
Multi-segment GF(2m) multiplication and its application to elliptic curve cryptography. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
elliptic curve scalar multiplication, FPGA, elliptic curve cryptography (ECC), coprocessor, finite field multiplication |
15 | Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede |
Efficient pipelining for modular multiplication architectures in prime fields. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
public key coprocessor, FPGA, cryptography, montgomery multiplication |
15 | A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
Low power and high-speed implementation of fir filters for software defined radio receivers. |
IEEE Trans. Wirel. Commun. |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Pramod Kumar Meher |
Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation. |
IEEE Trans. Circuits Syst. Video Technol. |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Jarmo Takala, Konsta Punkka |
Scalable FFT Processors and Pipelined Butterfly Units. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
parallel processing, application-specific integrated circuit, CORDIC, distributed arithmetic, radix-2 |
15 | Martin Novotný, Jan Schmidt |
Two Architectures of a General Digit-Serial Normal Basis Multiplier. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz |
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Chuan He, Guan Qin, Mi Lu, Wei Zhao 0001 |
An Optimized Finite Difference Computing Engine on FPGAs. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
|
15 | R. Mahesh 0001, A. Prasad Vinod 0001 |
A new common subexpression elimination algorithm for implementing low complexity FIR filters in software defined radio receivers. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | A. Prasad Vinod 0001, Ankita Singla, Chip-Hong Chang |
Improved differential coefficients-based low power FIR filters. Part I. Fundamentals. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Nima Honarmand, M. Reza Javaheri, Naser Sedaghati-Mokhtari, Ali Afzali-Kusha |
Power efficient sequential multiplication using pre-computation. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Fault tolerant design of signed digit based FIR filters. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | C. F. Moyano, Roberto S. Salgado, Luciano V. Barboza |
On the determination of adjusted OPF solutions. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Thomas J. Wollinger, Guido Bertoni, Luca Breveglieri, Christof Paar |
Performance of HECC Coprocessors Using Inversion-Free Formulae. |
ICCSA (3) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Vijay K. Jain, Glenn H. Chapman |
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance |
15 | Andrea Boni, Alessandro Zorat |
FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation. |
IJCNN |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Ming Z. Zhang, Vijayan K. Asari |
A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Saurabh Singh, K. Radhakrishna Rao |
Low Voltage Analogue Multiplier. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung |
Customizable elliptic curve cryptosystems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Haining Fan, Yiqi Dai |
Fast Bit-Parallel GF(2^n) Multiplier for All Trinomials. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
Finite field, multiplication, polynomial basis, irreducible trinomial |
15 | Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen |
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
B-spline factorization, discrete wavelet transform, VLSI architecture |
15 | Pradeep Kumar Mishra |
Efficient Simultaneous Inversion in Parallel and Application to Point Multiplication in ECC. |
CISC |
2005 |
DBLP DOI BibTeX RDF |
Montgomery ladder, simultaneous inversion, parallel algorithm, Elliptic Curve Cryptosystems, Scalar Multiplication |
15 | Bo Yang 0010, Nikhil Joshi, Ramesh Karri |
A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
Design of a radix-2m hybrid array multiplier using carry save adder format. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
hybrid multiplier, low power, carry save adder |
15 | Qingsheng Hu, Zhigong Wang, Jun Zhang, Jie Xiao |
Low complexity parallel Chien search architecture for RS decoder. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
Design of low complexity high-speed pulse-shaping IIR filters for mobile communication receivers. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong |
Compact Linear Systolic Arrays for Multiplication Using a Trinomial Basis in GF(2m) for High Speed Cryptographic Processors. |
ICCSA (1) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, finite field, systolic array, irreducible trinomial |
15 | Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon |
Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty |
SOC test planning using virtual test access architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Dominik Stoffel, Wolfgang Kunz |
Equivalence checking of arithmetic circuits on the arithmetic bit level. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Steven S. W. Lee, Maria C. Yuang, Po L. Tien, Shih-Hsun Lin |
A Lagrangean relaxation-based approach for routing and wavelength assignment in multigranularity optical WDM networks. |
IEEE J. Sel. Areas Commun. |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Arash Reyhani-Masoleh, M. Anwar Hasan |
Towards fault-tolerant cryptographic computations over finite fields. |
ACM Trans. Embed. Comput. Syst. |
2004 |
DBLP DOI BibTeX RDF |
polynomial basis multiplier, security, fault-tolerant computing, finite fields, Error correction |
15 | Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang |
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. |
J. VLSI Signal Process. |
2004 |
DBLP DOI BibTeX RDF |
low-power multiplier, coefficient optimization, power weight factor, power modeling |
15 | BaiJie Kuang, Yuefei Zhu, YaJuan Zhang |
An Improved Algorithm for uP + vQ Using JSF13. |
ACNS |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro 0001, Sergio Bampi |
An improved synthesis method for low power hardwired FIR filters. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
FPGA synthesis, parallel FIR filter, power-of-two, common subexpression elimination |
15 | Raymond Hoare, Shen Chih Tung, Katrina Werger |
An 88-Way Multiprocessor within an FPGA with Customizable Instructions. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Architecture, Parallelism, DSP, SIMD |
15 | Yong-Hyuk Kim, Byung Ro Moon |
Lagrange Multiplier Method for Multi-campaign Assignment Problem. |
GECCO (2) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Guido Bertoni, Luca Breveglieri, Thomas J. Wollinger, Christof Paar |
Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems. |
ITCC (2) |
2004 |
DBLP DOI BibTeX RDF |
genus 2, parallelism, embedded processor, hardware architecture, hyperelliptic curve, co-processor |
15 | Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi 0001 |
Evolutionary Synthesis of Arithmetic Circuit Structures. |
Artif. Intell. Rev. |
2003 |
DBLP DOI BibTeX RDF |
genetic algorithms, genetic programming, evolutionary computation, multiple-valued logic, arithmetic circuits, evolutionary design, circuit design |
15 | Seokjin Lee, Martin D. F. Wong |
Timing-driven routing for FPGAs based on Lagrangian relaxation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
15 | James E. Stine, Oliver M. Duverne |
Variations on Truncated Multiplication. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Mustapha Bouhtou, Madiagne Diallo, Laura Wynter |
Capacitated Network Revenue Management through Shadow Pricing. |
Networked Group Communication |
2003 |
DBLP DOI BibTeX RDF |
Internet Pricing, Network Equilibrium, congestion control, Proportional Fairness, Bilevel Program, Revenue Maximization |
15 | Soonhak Kwon |
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II. |
IEEE Symposium on Computer Arithmetic |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Anders Lindström, Michael Nordseth, Lars Bengtsson, Amos Omondi |
Arithmetic Circuits Combining Residue and Signed-Digit Representations. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Masayuki Ito, David G. Chinnery, Kurt Keutzer |
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Seon Ok Lee, Seok Won Jung, Chang Han Kim, Janghong Yoon, Jae-Young Koh, Daeho Kim |
Design of Bit Parallel Multiplier with Lower Time Complexity. |
ICISC |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Ya Jun Yu, Tapio Saramäki, Yong Ching Lim |
An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong |
A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Mark A. Erle, Michael J. Schulte |
Decimal Multiplication Via Carry-Save Addition. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Yeshwant Kolla, Yong-Bin Kim, John Carter |
A novel 32-bit scalable multiplier architecture. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
CMOS VLSI, architecture, multiplier |
15 | Adnan Abdul-Aziz Gutub, Mohammad K. Ibrahim |
Power-time flexible architecture for GF(2k) elliptic curve cryptosystem computation. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
crypto-systems power-time tradeoff, projective coordinate arithmetic, parallel architecture, elliptic curve cryptography |
15 | Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhong Gao |
Finite Field Multiplier Using Redundant Representation. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
cyclotomic ring, redundant set, multiplier, Finite field arithmetic, normal basis, squaring |
15 | Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001 |
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. |
PPSN |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Ernest Jamro, Kazimierz Wiatr |
Constant Coefficient Convolution Implemented in FPGAs. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
15 | George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis |
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Richard H. Turner, Roger F. Woods, Tim Courtney |
Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Seokjin Lee, D. F. Wong 0001 |
Timing-driven routing for FPGAs based on Lagrangian relaxation. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
timing-driven routing, FPGA, Lagrangian relaxation |
15 | Hak-soo Yu, Jacob A. Abraham |
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
3-bit-scan, power-delay-area tradeoffs, synchronous sequential, multiplier, partial product |
15 | Dilip V. Sarwate, Naresh R. Shanbhag |
High-speed architectures for Reed-Solomon decoders. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Omar Nibouche, Ahmed Bouridane, Mokhtar Nibouche |
New architectures for serial-serial multiplication. |
ISCAS (2) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Lijun Gao, Keshab K. Parhi |
Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Tapio Saramäki, Håkan Johansson |
Optimization of FIR filters using the frequency-response masking approach. |
ISCAS (2) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Henrik Eriksson, Per Larsson-Edefors, William P. Marnane |
A regular parallel multiplier which utilizes multiple carry-propagate adders. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Yong Lian 0001 |
A new frequency-response masking structure with reduced complexity for FIR filter design. |
ISCAS (2) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Jagdish Chandra |
Hybrid Dynamical Systems - Minitrack Introduction. |
HICSS |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Ian A. Hiskens |
Stability of Limit Cycles in Hybrid Systems. |
HICSS |
2001 |
DBLP DOI BibTeX RDF |
trajectory sensitivities, hybrid systems, Limit cycles |
15 | Matthias P. Nowak, Werner Römisch |
Stochastic Lagrangian Relaxation Applied to Power Scheduling in a Hydro-Thermal System under Uncertainty. |
Ann. Oper. Res. |
2000 |
DBLP DOI BibTeX RDF |
multistage stochastic programming, stochastic unit commitment, power management, Lagrangian relaxation, mixed-integer |
15 | Rong Lin |
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
low-power CMOS circuits, parallel counter-multiplier circuits, reconfigurable architecture, Matrix multiplication |
15 | Benjamin W. Wah, Zhe Wu 0002 |
Discrete Lagrangian Methods for Designing Multiplierless Two-Channel PR-LP Filter Banks. |
J. VLSI Signal Process. |
1999 |
DBLP DOI BibTeX RDF |
|