Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	F. Matthew Rhodes, Joseph J. Dituri, Glenn H. Chapman, Bruce E. Emerson, Antonio M. Soares, Jack I. Raffel	A Monolithic Hough Transform Processor Based on Restructurable VLSI.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	pixel grouping, WSI technology, monolithic Hough transform processor, restructurable VLSI, wafer-scale-integration technology, PC board, monolithic integrated circuits, image processing, VLSI, transforms, computerised pattern recognition, digital arithmetic, circuit CAD, microprocessor chips, CAD tools, PCB, linear feature extraction
23	ZhiLei Chai, ZhiQiang Tang, LiMing Wang, Shi-liang Tu	An Effective Instruction Optimization Method for Embedded Real-Time Java Processor.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	Embedded Real-time Java Processor, Instruction Optimization, WCET (Worst Case Execution Time), Java Processor
23	Xiaotong Zhuang, Santosh Pande	Balancing register allocation across threads for a multithreaded network processor.	PLDI	2004	DBLP DOI BibTeX RDF	register allocation, network processor, multithreaded processor
23	Emilia Rosti, Evgenia Smirni, Lawrence W. Dowdy, Giuseppe Serazzi, Kenneth C. Sevcik	Processor Saving Scheduling Policies for Multiprocessor Systems.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	processor saving algorithm, work conserving, Markov analysis, performance evaluation, Multiprocessor systems, processor scheduling
23	Hong Liu, Wei-Ming Lin, Yongsheng Song	An efficient processor partitioning and thread mapping strategy for mesh-connected multiprocessor systems.	SAC	1997	DBLP DOI BibTeX RDF	processor partitioning, thread mapping, load balance, parallel processing, processor scheduling
23	Allen B. Downey	A Parallel Workload Model and its Implications for Processor Allocation.	HPDC	1997	DBLP DOI BibTeX RDF	parallel workload model, space-sharing parallel computers, Adaptive Static Partitioning, parallel computers, processor scheduling, processor allocation, ASP
23	Johan Stärner, Joakim Adomat, John Furunäs, Lennart Lindh	Real-Time Scheduling Co-Processor in Hardware for Single and Multiprocessor Systems.	EUROMICRO	1996	DBLP DOI BibTeX RDF	real-time scheduling co-processor, predictable time behaviour, digital chip, Real-Time Unit, global resources, task synchronisation, multiprocessor systems, timing analysis, processor scheduling
23	Santanu Chattopadhyay, S. Mitra 0001, Parimal Pal Chaudhuri	Cellular automata based architecture of a database query processor.	VLSI Design	1996	DBLP DOI BibTeX RDF	cellular automata based architecture, database query processor, programmable query processor chip, fast database access, multiple attractor cellular automata, class-relation storage, true/false classifier, classification, VLSI, query processing, relational databases, relational database, cellular automata, microprocessor chips, database machines
23	Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault	Addendum to "Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hierarchical scalable photonic architectures, high-performance processor interconnection, all-optical wavelength division multiplexed network, time multiplexed access protocol, static slot assignment, cycle synchronization, hypercube networks, wavelength division multiplexing, bandwidth allocation, optical information processing, distributed shared memory system, processor numbering
23	De-Lei Lee	Architecture of an Array Processor Using a Nonlinear Skewing Scheme.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	nonlinear skewing scheme, array processor architecture, interconnection network, parallel architectures, multiprocessor interconnection networks, cellular arrays, array processor, skewing schemes
23	Fred J. Taylor, Rabinder Gill, Jim Joseph, Jeff Radke	A 20 Bit Logarithmic Number System Processor.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	logarithmic number system processor, arithmetic processor, partitioned memory, integrated Schottky logic, 20 bit, satellite computers, performance evaluation, performance evaluation, architecture, computer architecture, digital arithmetic, PLA, microprocessor chips, table lookup, table lookup, ROM, field effect integrated circuits
23	John L. Hennessy	VLSI Processor Architecture.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	instruction issue, processor implementation, VLSI, pipelining, microprocessors, processor architecture, Computer organization, memory mapping, instruction set design
23	David P. Casasent, Peter D. Rapp	System Functions for an Optical/Digital Processor.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	register transfer modules, Hybrid processor, modular optical/digital interface, optical/digital processor, image processing, optical computing, radar signal processing
22	Michal Cernanský	Training Recurrent Neural Network Using Multistream Extended Kalman Filter on Multicore Processor and Cuda Enabled Graphic Processor Unit.	ICANN (1)	2009	DBLP DOI BibTeX RDF
22	Liam Noonan, Colin Flanagan	An effective network processor design framework: using multi-objective evolutionary algorithms and object oriented techniques to optimise the intel IXP1200 network processor.	ANCS	2006	DBLP DOI BibTeX RDF	object oriented, design space exploration, evolutionary approaches
22	Guilin Chen, Guangyu Chen, Ozcan Ozturk 0001, Mahmut T. Kandemir	Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs.	ISVLSI	2005	DBLP DOI BibTeX RDF
22	Seyed H. Hosseini, Nizar Jamal	Efficient distributed processor level fault diagnosis of multiple processor systems.	ICDCS	1991	DBLP DOI BibTeX RDF
22	Takao Nishitani, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Toshiyuki Kanou, Koichi Kikuchi	Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
21	Jason Truman	Radio Frequency Modulated Signaling Interconnect for Memory-to-Processor and Processor-to-Processor Interfaces: An Overview.	CoRR	2016	DBLP BibTeX RDF
21	Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori	A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.	ISSCC	2013	DBLP DOI BibTeX RDF
21	Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres	Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.	DATE	2009	DBLP DOI BibTeX RDF
21	Rama Sangireddy, Jatan P. Shah	Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
21	Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Metrics for Architecture-Level Lifetime Reliability Analysis.	ISPASS	2008	DBLP DOI BibTeX RDF
21	Rod Fatoohi	Performance evaluation of NSF application benchmarks on parallel systems.	IPDPS	2008	DBLP DOI BibTeX RDF
21	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Techniques for Efficient Processing in Runahead Execution Engines.	ISCA	2005	DBLP DOI BibTeX RDF
21	Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami	Circuits for wide-window superscalar processors.	ISCA	2000	DBLP DOI BibTeX RDF
21	Steven K. Reinhardt, Shubhendu S. Mukherjee	Transient fault detection via simultaneous multithreading.	ISCA	2000	DBLP DOI BibTeX RDF
21	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
21	John L. Gustafson	Reevaluating Amdahl's Law.	Commun. ACM	1988	DBLP DOI BibTeX RDF
21	Kiyoshi Shibayama, Masaaki Yamamoto, Hiroaki Hirata, Yasushi Konoh, Takanori Sanetoh, Hiroshi Hagiwara	KPR: A Logic Programming Language-Oriented Parallel Machine.	LP	1987	DBLP DOI BibTeX RDF	Parallel Inference Machine, High-Level Language Machine, Parallel Processing, Logic Programming Language
21	Bing Shi, Yufu Zhang, Ankur Srivastava 0001	Dynamic thermal management for single and multicore processors under soft thermal constraints.	ISLPED	2010	DBLP DOI BibTeX RDF	multi-core processor, dynamic thermal management
21	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
21	Jungseob Lee, Nam Sung Kim	Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.	DAC	2009	DBLP DOI BibTeX RDF	multicore processor, DVFS, power gating
21	Richard Hughey, Andrea Di Blas	Finding the Next Computational Model: Experience with the UCSC Kestrel.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	biological sequence comparison, VLSI system design, application-specific array processor, parallel processing, parallel programming, computer architecture, systolic array, SIMD, sequence analysis, shared registers
21	Sascha Uhrig, Jörg Mische, Theo Ungerer	An IP Core for Embedded Java Systems.	SAMOS	2007	DBLP DOI BibTeX RDF	Implantable Systems, Embedded System-on-a-Chip Implementations, Real-time Embedded Systems, Multithreaded Processors, Java Processor, Embedded Operating Systems
21	Uwe Brinkschulte	Scalable Online Feasibility Tests for Admission Control in a Java Real-Time System.	Real Time Syst.	2006	DBLP DOI BibTeX RDF	guaranteed percentage scheduling, processor demand analysis, real-time scheduling, feasibility tests
21	Juan L. Aragón, José M. González, Antonio González 0001	Control Speculation for Energy-Efficient Next-Generation Superscalar Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	low-power design, processor architecture, energy-aware systems, Control speculation
21	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor performance modeling, speculative execution, runahead execution, Single data stream architectures
21	Dharmesh Parikh, Kevin Skadron, Yan Zhang 0028, Mircea R. Stan	Power-Aware Branch Prediction: Characterization and Design.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	target prediction, highly-biased branches, pipeline gating, speculation control, Low-power design, power, branch prediction, processor architecture, energy-aware systems, banking
21	Sunghyun Jee, Kannappan Palaniappan	Dynamically Scheduling VLIW Instructions with Dependency Information.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	DISVLIW, VLIW, Dynamic Scheduling, Processor Architecture, ILP
21	Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis	Operation-Saving VLSI Architectures for 3D Geometrical Transformations.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Elementary geometrical transformations, vector unit, VLSI architecture, graphics processor
21	Takahiro Koita, Tetsuro Katayama, Keizo Saisho, Akira Fukuda	Memory Conscious Scheduling for Cluster-based NUMA Multiprocessors.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	dynamic space-sharing, page placement, cluster-based NUMA multiprocessors, multiprogrammed environments, processor scheduling
21	Martti Forsell, Martti Penttonen, Ville Leppänen	Efficient Two-Level Mesh based Simulation of PRAMs.	ISPAN	1996	DBLP DOI BibTeX RDF	time-processor optimal, simulation, interconnection network, mesh, PRAM, shared memory machine
21	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
21	Jack L. Rosenfeld	A case study in programming for parallel-processors.	Commun. ACM	1969	DBLP DOI BibTeX RDF	Gauss-Seidel, Jacobi, storage interference, simulation, parallel programming, parallelism, multiprocessor, convergence, tasking, multiprogramming, relaxation, parallel-processor, electrical network
21	M. K. Velamati, Arun Kumar 0004, Naresh Jayam, Ganapathy Senthilkumar, Pallav K. Baruah, Raghunath Sharma, Shakti Kapoor, Ashok Srinivasan	Optimization of Collective Communication in Intra-cell MPI.	HiPC	2007	DBLP DOI BibTeX RDF	heterogeneous multicore processor, MPI, Cell Processor
21	Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer 0001, Li Zhao 0002, W. Cohen	Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.	ISPASS	2007	DBLP DOI BibTeX RDF	memory hierarchy model, full-system simulation acceleration, operating system performance characterization, operating system performance prediction, computer hardware complexity, cycle-accurate processor system simulation overheads, system libraries, OS service performance behavior, processor hierarchy model, Linux, software complexity
21	Prabhat Mishra 0001, Nikil D. Dutt	Modeling and validation of pipeline specifications.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Modeling of processor pipeline, pipeline validation, pipelined processor specification, architecture description language
21	Lesley Shannon, Paul Chow	Using reconfigurability to achieve real-time profiling for hardware/software codesign.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, profiling, performance measurement, embedded processor, hardware/software codesign, soft processor
21	Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leonid Oliker, Katherine A. Yelick, Rupak Biswas	Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines.	IPDPS	2002	DBLP DOI BibTeX RDF	memory intensive benchmarks, data parallelism, vector processor, Processor-in-Memory, embedded DRAM
21	Murat Aydos, Tugrul Yanik, Çetin Kaya Koç	An High-Speed ECC-based Wireless Authentication Protocol on an ARM Microprocessor.	ACSAC	2000	DBLP DOI BibTeX RDF	high-speed ECC-based wireless authentication, ARM microprocessor, elliptic curve digital signature algorithm, ARM7TDMI processor, core processor, 80 MHz, 160 bit, mobile computing, elliptic curve cryptography, public key cryptography, software libraries, software library, authorisation, microprocessor chips, message authentication, portable computers, ECDSA, 32 bit, wireless applications
21	Albert R. McSpadden, Noé Lopez-Benitez	Stochastic Petri nets applied to the performance evaluation of static task allocations in heterogeneous computing environments.	Heterogeneous Computing Workshop	1997	DBLP DOI BibTeX RDF	static task allocations, heterogeneous computing environments, processor suite, subtask execution times, enabling functions, rate functions, SPN model, processor heterogeneity, task priorities, allocation schemes, optimization schemes, non-series-parallel graphs, performance evaluation, Petri nets, heuristics, stochastic Petri net, communication costs, task graph, exponential distribution, completion time
21	Seungkweon Jeong, Young Shin Kim, Wook Hyun Kwon	Scheduling algorithm for programmable logic controllers with remote I/Os.	RTCSA	1997	DBLP DOI BibTeX RDF	remote I/O, remote input output, sequence programs, application processor, bounded response time, scheduling algorithm, network processor, computer simulation, multitasking, data transmission, programmable logic controllers, PLC, programmable controllers
21	Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu	Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors.	ISPAN	1996	DBLP DOI BibTeX RDF	edge-weighted directed acyclic graph, bounded number of processors scheduling, arbitrary processor network, scheduling, scheduling, parallel programming, processor scheduling, data flow graphs, task graphs, parallel processors, dataflow graph
21	Guido Araujo, Sharad Malik	Optimal code generation for embedded memory non-homogeneous register architectures.	ISSS	1995	DBLP DOI BibTeX RDF	TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation
21	Heejo Lee, Kenji Toda, Jong Kim 0001, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi	Performance comparison of real-time architectures using simulation.	RTCSA	1995	DBLP DOI BibTeX RDF	real-time architectures, discrete event-driven, task-based simulator, priority-based communication, simulation, schedulability, performance evaluation, real-time systems, parallel processing, predictability, distributed processing, discrete event simulation, performance prediction, network architectures, processor, distributed real-time systems, performance comparison, scheduling policy, parallel computer systems, dedicated processor, interrupt handling
21	Atsushi Hori, Munenori Maeda, Yutaka Ishikawa, Takashi Tomokiyo, Hiroki Konaka	A scalable time-sharing scheduling for partitionable distributed memory parallel machines.	HICSS (2)	1995	DBLP DOI BibTeX RDF	time-sharing systems, scalable time-sharing scheduling, partitionable distributed memory parallel machines, process scheduling queue system, distributed queue tree, dynamically partitionable parallel machines, dynamically nested partitioning, time-sharing scheduling, process scheduling queues, round-robin scheduling algorithm, task allocation policies, high-load situations, parallel machines, reconfigurable architectures, trees (mathematics), distributed memory systems, processor scheduling, simulation results, interactive environment, time-sharing, nested, batch scheduling, processor utilization
21	Alexandre E. Eichenberger, Santosh G. Abraham	Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	fuzzy barriers, overall execution time, parallel region, nondeterministic load imbalance modelling, random replacement policy, processor caches, cyclic access stream, interprocessor synchronization, 64-processor KSR system, Kendall Square Research system, random first-level caches, performance evaluation, resource allocation, concurrency control, synchronisation, shared memory systems, cache storage, variance, performance improvement, network contention, hit ratio, scalable shared-memory multiprocessors
21	Ian J. Palmer	Modelling the computer animation process for parallel environments.	CA	1995	DBLP DOI BibTeX RDF	computer animation process modelling, processor intensive task, behavioural realism, frame-based animation process, task-processor assignment method, dedicated processing architecture, parallel processing, object-oriented programming, programming environments, computer animation, object-oriented model, parallel environments
21	Jair Jehuda, Gilad Koren, Daniel M. Berry	A time-sharing architecture for complex real-time systems.	ICECCS	1995	DBLP DOI BibTeX RDF	time-sharing systems, time-sharing architecture, dynamic multiple job systems, shared-memory multi-processor platforms, multiple states, near-optimal mode selection, reliable real-time time-sharing, job-oriented strategy, best-effort system values, dynamic critical task sets, complex task characteristics, real-time systems, resource allocation, shared memory systems, processor scheduling, portability, dynamic load-balancing, complex real-time systems, divide-and-conquer approach
21	Shuo-Hsien Hsiao, C. Y. Roger Chen	Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	message size, circuit switched multistage interconnection networks, hold strategy, processor-memory communications, processor processing time, closed queuing network model, performance evaluation, performance evaluation, multiprocessor interconnection networks, queueing theory, multiprocessor systems, switching theory, memory access
21	Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel	Error Recovery in Shared Memory Multiprocessors Using Private Caches.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	processor transient faults, user-transparent checkpointing, checkpointed computation state, recovery stacks, rollback propagation, rapidrecovery, fault tolerance, fault tolerant computing, multiprocessor interconnection networks, multiprocessing systems, shared memory multiprocessors, system recovery, buffer storage, cache coherence protocols, performance degradation, processor utilization, private caches, error latency
21	Viktor K. Prasanna, Dionisios I. Reisis	Image Computations on Meshes with Multiple Broadcast.	IEEE Trans. Pattern Anal. Mach. Intell.	1989	DBLP DOI BibTeX RDF	distributed array processor, parallel algorithms, parallel algorithms, computational complexity, distributed processing, computerised picture processing, computerised picture processing, parallel machines, parallel machines, image computations, data movement, mesh-connected processor array, time performance, multiple broadcast
20	Rasmus Ulslev Pedersen, Martin Schoeberl	Object oriented machine learning with a multicore real-time Java processor: short paper.	JTRES	2010	DBLP DOI BibTeX RDF
20	Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar 0002	Reducing peak power with a table-driven adaptive processor core.	MICRO	2009	DBLP DOI BibTeX RDF	resource resizing, voltage variation, peak power, adaptive architectures, decoupling capacitance
20	Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Characterizing the resource-sharing levels in the UltraSPARC T2 processor.	MICRO	2009	DBLP DOI BibTeX RDF	Sun Nigara T2, CMP, job scheduling, simultaneous multithreading, performance characterization, CMT
20	Sudhir Vinjamuri, Viktor K. Prasanna	Transitive closure on the cell broadband engine: A study on self-scheduling in a multicore processor.	IPDPS	2009	DBLP DOI BibTeX RDF
20	Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir	A case for integrated processor-cache partitioning in chip multiprocessors.	SC	2009	DBLP DOI BibTeX RDF
20	Martin Palkovic, Hans Cappelle, Miguel Glassee, Bruno Bougard, Liesbet Van der Perre	Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform.	DDECS	2008	DBLP DOI BibTeX RDF
20	Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay	Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video.	ICIP	2008	DBLP DOI BibTeX RDF
20	Xi Chen 0068, Robert P. Dick, Alok N. Choudhary	Operating System Controlled Processor-Memory Bus Encryption.	DATE	2008	DBLP DOI BibTeX RDF
20	Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar	Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor.	DATE	2008	DBLP DOI BibTeX RDF
20	Ying Zhang 0032, Qiang Dou, Gen Li 0002, Xuejun Yang, Yongjin Li, Caixia Huang	Mapping and Optimizing 2-D Jacobi Iteration on a Stream Processor.	HPCC	2008	DBLP DOI BibTeX RDF
20	Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park	A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Tsun-Hsien Wang, Wei-Su Wong, Fang-Chu Chen, Ching-Te Chiu	Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video.	ICIP (6)	2007	DBLP DOI BibTeX RDF
20	Sandro Bartolini, Cinzia Castagnini, Enrico Martinelli	Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography.	IAS	2007	DBLP DOI BibTeX RDF	security in embedded systems, special-purpose unit, performance evaluation, Elliptic-curve cryptography, instruction-set extensions
20	P. Yeung, A. Torres, P. Batra	Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor.	DATE	2007	DBLP DOI BibTeX RDF
20	Matthew Marshall, Gordon Russell 0002	A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor.	DSD	2007	DBLP DOI BibTeX RDF
20	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Rethinking custom ISE identification: a new processor-agnostic method.	CASES	2007	DBLP DOI BibTeX RDF	ISE identification, custom processors, maximal cluster
20	Chia-Liang Tsai, Shao-Yi Chien	Flexible and Cost Effective Transport Stream Processor for DTV.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Chichyang Chen, Paul Chow	Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	exponential computation, logarithmic computation, logarithmic number system (LNS) arithmetic, floating-point arithmetic
20	Jianxun Jason Ding, Abdul Waheed	Dual Processor Performance Characterization for XML Application-Oriented Networking.	ICPP	2007	DBLP DOI BibTeX RDF
20	Weidong Shi, Hsien-Hsin S. Lee	Authentication Control Point and Its Implications For Secure Processor Design.	MICRO	2006	DBLP DOI BibTeX RDF
20	Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu 0001, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.	MICRO	2006	DBLP DOI BibTeX RDF
20	Hai-Chen Wang, Chung-Kwong Yuen	Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor.	IPDPS	2006	DBLP DOI BibTeX RDF
20	Sebastian Siegel, Rainer Schaffer, Renate Merker	Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.	PARELEC	2006	DBLP DOI BibTeX RDF
20	Selwyn Leeke, Koushik Maharatna	A low-power geometric mapping co-processor for high-speed graphics application.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa	On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
20	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF
20	Hyunseok Lee, Trevor N. Mudge	A dual-processor solution for the MAC layer of a software defined radio terminal.	CASES	2005	DBLP DOI BibTeX RDF	SDR terminal, wireless platform, protocol processing
20	Xin Li 0020, Jan Lukoschus, Marian Boldt, Michael Harder, Reinhard von Hanxleden	An Esterel processor with full preemption support and its worst case reaction time analysis.	CASES	2005	DBLP DOI BibTeX RDF	reaction time analysis, reactive processing, WCET, synchronous languages, Esterel
20	Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki	Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
20	Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala	256-State Rate 1/2 Viterbi Decoder on TTA Processor.	ASAP	2005	DBLP DOI BibTeX RDF
20	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
20	Markus Levy	Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications.	HiPEAC	2005	DBLP DOI BibTeX RDF
20	Fan Zhang 0097, Samuel T. Chanson	Blocking-aware processor voltage scheduling for real-time tasks.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	non-preemptible sections, real-time systems, Dynamic power management, power-aware scheduling
20	Sung-Hoon Shim, Cheol Hong Kim, Jong Wook Kwak, Chu Shik Jhon	Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor.	EUC	2004	DBLP DOI BibTeX RDF
20	Seung-Min Lee, Stefan Lachowicz, David Lucas, A. M. Rassau, Kamran Eshraghian, Mike Myung-Ok Lee, Kamal E. Alameh	A Novel Design of Beam Steering n-phase OPTO-ULSI Processor for IIPS.	DELTA	2004	DBLP DOI BibTeX RDF
20	Francisco Rodríguez 0003, José Carlos Campelo, Juan José Serrano	A Watchdog Processor Architecture with Minimal Performance Overhead.	SAFECOMP	2002	DBLP DOI BibTeX RDF
20	Jeanine E. Cook, Richard L. Oliver, Eric E. Johnson	Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity.	SIGMETRICS	2002	DBLP DOI BibTeX RDF