Search results for "routability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Ali Jahanian 0001, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi	Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability.	CSICC	2008	DBLP DOI BibTeX RDF
19	Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow	Routability of Network Topologies in FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
19	Yanhua Wang, Qiang Zhou 0001, Jinian Bian, Junhua Qu	VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
19	Jin-Tai Yan, Zhi-Wei Chen, Kuen-Ming Lin	Routability-Driven Track Routing for Coupling Capacitance Reduction.	ICECS	2007	DBLP DOI BibTeX RDF
19	Audip Pandit, Ali Akoglu	Net Length based Routability Driven Packing.	FPT	2007	DBLP DOI BibTeX RDF
19	Yue Zhuo, Hao Li, Qiang Zhou 0001, Yici Cai, Xianlong Hong	New timing and routability driven placement algorithms for FPGA synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	congestion driven placement, physical synthesis, timing driven placement, net weight
19	Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson	Network coding for routability improvement in VLSI.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Zied Marrakchi, Hayder Mrabet, Habib Mehrez	Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation.	ReConFig	2005	DBLP DOI BibTeX RDF
19	Akshay Sharma, Carl Ebeling, Scott Hauck	Architecture-Adaptive Routability-Driven Placement for FPGAs.	FPL	2005	DBLP DOI BibTeX RDF
19	Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh	Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs.	J. Circuits Syst. Comput.	2004	DBLP DOI BibTeX RDF
19	Katherine Compton, Scott Hauck	Track placement: orchestrating routing structures to maximize routability.	FPGA	2003	DBLP DOI BibTeX RDF
19	Jiping Liu, Hongbing Fan, Yu-Liang Wu	On improving FPGA routability applying multi-level switch boxes.	ASP-DAC	2003	DBLP DOI BibTeX RDF
19	Katherine Compton, Scott Hauck	Track Placement: Orchestrating Routing Structures to Maximize Routability.	FPL	2003	DBLP DOI BibTeX RDF
19	Victor N. Kravets, Prabhakar Kudva	Understanding metrics in logic synthesis for routability enhancement.	SLIP	2003	DBLP DOI BibTeX RDF	optimization, VLSI, synthesis, decomposition, layout, congestion, structure, circuits
19	Jun-seob Lee, Heeyoung Jung, Sung-han Kim, Seok Joo Koh, Jae Hong Min	Return Routability Procedure between MAP and MN in HMIPv6.	International Conference on Internet Computing	2003	DBLP BibTeX RDF
19	Yu-Jung Huang, Mei-hui Guo, Shen-Li Fu	Reliability and routability consideration for MCM placement.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
19	William N. N. Hung, Xiaoyu Song, Alan J. Coppola, Andrew A. Kennings	On segmented channel routability.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
19	Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang	Wire space estimation and routability analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai	Efficient routability check algorithms for segmented channel routing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field programmable gate arryas (FPGAs), segmented channel, routing
19	Aman Shaikh, Anujan Varma, Lampros Kalampoukas, Rohit Dube	Routability stability in congested networks: experimentation and analysis.	SIGCOMM	2000	DBLP DOI BibTeX RDF
19	Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh	Routability-driven repeater block planning for interconnect-centric floorplanning.	ISPD	2000	DBLP DOI BibTeX RDF
19	Jin-Tai Yan	Routability Crossing Distribution and Floating Pin Assignment for T-type Junction Region.	VLSI Design	1999	DBLP DOI BibTeX RDF
19	Kusnadi, Jo Dale Carothers	A method of measuring nets routability for MCM's general area routing problems.	ISPD	1999	DBLP DOI BibTeX RDF
19	Majid Sarrafzadeh, Toshihiko Takahashi	A fast algorithm for routability testing.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
19	R. Glenn Wood, Rob A. Rutenbar	FPGA Routing and Routability Estimation via Boolean Satisfiability.	FPGA	1997	DBLP DOI BibTeX RDF
19	Naoyuki Iso, Yasushi Kawaguchi, Tomio Hirata	Efficient routability checking for global wires in planar layouts.	ASP-DAC	1997	DBLP DOI BibTeX RDF
19	Toshiyuki Hama, Hiroaki Etoh	Topological routing path search algorithm with incremental routability test.	ASP-DAC	1997	DBLP DOI BibTeX RDF
19	Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama	Not necessarily more switches more routability [sic.].	ASP-DAC	1997	DBLP DOI BibTeX RDF
19	Stephen Dean Brown, Muhammad M. Khellah, Guy Lemieux	Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays.	VLSI Design	1996	DBLP DOI BibTeX RDF
19	F. Miller Maley	Testing Homotopic Routability Under Polygonal Wiring Rules.	Algorithmica	1996	DBLP DOI BibTeX RDF
19	Joel Darnauer, Wayne Wei-Ming Dai	A Method for Generating Random Circuits and Its Application to Routability Measurement.	FPGA	1996	DBLP DOI BibTeX RDF
19	Yasuhiro Takashima, Atsushi Takahashi 0001, Yoji Kajitani	Detailed-Routability of FPGAs with Extremal Switch-Block Structures.	ED&TC	1996	DBLP DOI BibTeX RDF
19	Kaushik Roy 0001, Sudip Nag	On Routability for FPGAs under Faulty Conditions.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF
19	Yuh-Sheng Lee, Allen C.-H. Wu	A Performance and Routability Driven Router for FPGAs Considering Path Delays.	DAC	1995	DBLP DOI BibTeX RDF
19	Om P. Agrawal	A High Density Complex PLD Family Optimized for Flexibility, Predictability and 100% Routability.	FPL	1994	DBLP DOI BibTeX RDF
19	Kaushik Roy 0001, Sudip Nag	On Channel Architecture and Routability for FPGAs Under Faulty Conditions.	FPL	1994	DBLP DOI BibTeX RDF
19	Jin-Tai Yan, Pei-Yung Hsiao	Routability crossing distribution and floating terminal assignment of T-type junction region.	Great Lakes Symposium on VLSI	1994	DBLP DOI BibTeX RDF
19	Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas	Mathematical model for routability analysis of FPGAs.	Great Lakes Symposium on VLSI	1994	DBLP DOI BibTeX RDF
19	Mahesh Mehendale	Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures.	VLSI Design	1994	DBLP DOI BibTeX RDF
19	Keumog Ahn, Sartaj Sahni	Flipping Modules to Improve Circuit Performance and Routability.	VLSI Design	1994	DBLP DOI BibTeX RDF
19	Kai Zhu 0001, D. F. Wong 0001	Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs.	DAC	1994	DBLP DOI BibTeX RDF
19	Patrick Groeneveld	Necessary and sufficient conditions for the routability of classical channels.	Integr.	1993	DBLP DOI BibTeX RDF
19	Massoud Pedram, Bahman S. Nobandegani, Bryan Preas	Architecture and routability analysis for row-based FPGAs.	ICCAD	1993	DBLP DOI BibTeX RDF
19	Kaushik Roy 0001, Sudip Nag, Santanu Dutta	Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs.	ICCD	1993	DBLP DOI BibTeX RDF
19	Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien	On Routability Prediction for Field-Programmable Gate Arrays.	DAC	1993	DBLP DOI BibTeX RDF	XILINX 3000
19	Hirendu Vaishnav, Massoud Pedram	Routability-Driven Fanout Optimization.	DAC	1993	DBLP DOI BibTeX RDF
19	Martine D. F. Schlag, Jackson Kong, Pak K. Chan	Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs.	ICCD	1992	DBLP DOI BibTeX RDF
19	Wayne Wei-Ming Dai, Raymond Kong, Masao Sato	Routability of a Rubber-Band Sketch.	DAC	1991	DBLP DOI BibTeX RDF
19	Dick W. Harberts, Dré A. J. M. van den Elshout, Harry J. M. Veendrick	Design for routability of a high-density gate array.	ICCD	1990	DBLP DOI BibTeX RDF
19	Ten-Hwang Lai, Alan P. Sprague	On the Routability of a Convex Grid.	J. Algorithms	1987	DBLP DOI BibTeX RDF
19	Charles E. Leiserson, F. Miller Maley	Algorithms for Routing and Testing Routability of Planar VLSI Layouts	STOC	1985	DBLP DOI BibTeX RDF
19	Hing-Cheung So	Pin assignment of circuit cards and the routability of multilayer printed wiring backplanes.	DAC	1973	DBLP BibTeX RDF
11	Lijuan Luo, Tan Yan, Qiang Ma 0002, Martin D. F. Wong, Toshiyuki Shibuya	B-escape: a simultaneous escape routing algorithm based on boundary routing.	ISPD	2010	DBLP DOI BibTeX RDF	PCB routing, dense circuit boards, computer-aided design, escape routing
11	Rupesh S. Shelar, Marek Patyra	Impact of local interconnects on timing and power in a high performance microprocessor.	ISPD	2010	DBLP DOI BibTeX RDF	CAD, delay, interconnects, power, microprocessor
11	Charles J. Alpert, Zhuo Li 0001, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez	What makes a design difficult to route.	ISPD	2010	DBLP DOI BibTeX RDF	congestion driven physical synthesis, routing
11	Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang	An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
11	Muhammet Mustafa Ozdal	Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
11	Lijuan Luo, Martin D. F. Wong	On using SAT to ordered escape problems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
11	Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer	On improving optimization effectiveness in interconnect-driven physical synthesis.	ISPD	2009	DBLP DOI BibTeX RDF	routing, interconnect, physical synthesis, circuit optimization, vlsi
11	Suresh Raman, Mike Lubyanitsky	Cone Resynthesis ECO Methodology for Multi-Million Gate Designs.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao	Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu	MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han	Full-Chip Routing Considering Double-Via Insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Minsik Cho, David Z. Pan	A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Tao Xu 0002, Krishnendu Chakrabarty	Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Physical design automation, microfluidics, biochips, module placement
11	Mingjie Lin	The amorphous FPGA architecture.	FPGA	2008	DBLP DOI BibTeX RDF	amorphous, FPGA, architecture, performance analysis
11	Tilo Meister, Jens Lienig, Gisbert Thomke	Novel Pin Assignment Algorithms for Components with Very High Pin Counts.	DATE	2008	DBLP DOI BibTeX RDF
11	Minsik Cho, David Z. Pan	A high-performance droplet router for digital microfluidic biochips.	ISPD	2008	DBLP DOI BibTeX RDF	routing, synthesis, microfluidics, biochip
11	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A polynomial time approximation scheme for timing constrained minimum cost layer assignment.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang	Multi-layer global routing considering via and wire capacities.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Yanheng Zhang, Yue Xu, Chris Chu	FastRoute3.0: a fast and high quality global router based on virtual capacity.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Jia-Wei Fang, Yao-Wen Chang	Area-I/O flip-chip routing for chip-package co-design.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang	Routing for chip-package-board co-design considering differential pairs.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Jin Hu, Jarrod A. Roy, Igor L. Markov	Sidewinder: a scalable ILP-based router.	SLIP	2008	DBLP DOI BibTeX RDF	integer linear programming, global routing
11	Hidetoshi Kobayashi, Kazumasa Takami	Algorithm for Selecting either an Overlay or Flat Route Based on the Amount of the Delay Measurement Load on the Home Agent in a Hierarchical Mobile IPv6 Network.	NEW2AN	2008	DBLP DOI BibTeX RDF	Packet delay, Route Selection, Hierarchical Mobile IPv6
11	Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan	An integrated nonlinear placement framework with congestion and porosity aware buffer planning.	DAC	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, buffer
11	Tai-Chen Chen, Yao-Wen Chang	Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Chiu-Wing Sham, Evangeline F. Y. Young	Area reduction by deadspace utilization on interconnect optimized floorplan.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	area reduction, Floorplanning
11	Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez	Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances.	NOCS	2007	DBLP DOI BibTeX RDF
11	Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore	Implications of Rent's Rule for NoC Design and Its Fault-Tolerance.	NOCS	2007	DBLP DOI BibTeX RDF
11	Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen	Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu 0002, Lei He 0001, Xianlong Hong	DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Seonggeun Ryu, Youngsong Mun	A Scheme to Enhance TEBU Scheme of Fast Handovers for Mobile IPv6.	ICESS	2007	DBLP DOI BibTeX RDF
11	Philip Chong, Christian Szegedy	A morphing approach to address placement stability.	ISPD	2007	DBLP DOI BibTeX RDF	incremental placement, stability, morphing
11	Eunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang	Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design.	ISQED	2007	DBLP DOI BibTeX RDF
11	Chen Li 0004, Cheng-Kok Koh	Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement.	ISQED	2007	DBLP DOI BibTeX RDF
11	Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang	An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.	DAC	2007	DBLP DOI BibTeX RDF
11	Muhammet Mustafa Ozdal	Escape Routing For Dense Pin Clusters In Integrated Circuits.	DAC	2007	DBLP DOI BibTeX RDF
11	Tao Xu 0002, Krishnendu Chakrabarty	Integrated Droplet Routing in the Synthesis of Microfluidic Biochips.	DAC	2007	DBLP DOI BibTeX RDF
11	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu	MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.	DAC	2007	DBLP DOI BibTeX RDF
11	Yajun Ran, Malgorzata Marek-Sadowska	Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Lihong Zhang, Ulrich Kleine, Yingtao Jiang	An automated design tool for analog layouts.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	PariVallal Kannan, Dinesh Bhatia	Interconnect estimation for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Andrew B. Kahng, Sherief Reda	Wirelength minimization for min-cut placements via placement feedback.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Gang Chen 0020, Jason Cong	Simultaneous placement with clustering and duplication.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	clustering, FPGA, Placement, legalization, duplication, redundancy removal
11	Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake	Multi-SP: A Representation with United Rectangles for Analog Placement and Routing.	ISVLSI	2006	DBLP DOI BibTeX RDF
11	Claudio Menezes, Cristina Meinhardt, Ricardo Reis 0001, Reginaldo Tavares	A Regular Layout Approach for ASICs.	ISVLSI	2006	DBLP DOI BibTeX RDF
11	Zied Marrakchi, Hayder Mrabet, Habib Mehrez	Configuration tools for a new multilevel hierarchical FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
11	Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin	A novel framework for multilevel full-chip gridless routing.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	NTUplace2: a hybrid placer using partitioning and analytical techniques.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, legalization