Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Ali Jahanian 0001, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi |
Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSICC ![In: Advances in Computer Science and Engineering - 13th International CSI Computer Conference, CSICC 2008, Kish Island, Iran, March 9-11, 2008 Revised Selected Papers, pp. 689-696, 2008, 978-3-540-89984-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow |
Routability of Network Topologies in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 948-951, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yanhua Wang, Qiang Zhou 0001, Jinian Bian, Junhua Qu |
VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAD/Graphics ![In: 10th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2007, Beijing, China, 15-18 October, 2007, pp. 349-354, 2007, IEEE, 978-1-4244-1579-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Tai Yan, Zhi-Wei Chen, Kuen-Ming Lin |
Routability-Driven Track Routing for Coupling Capacitance Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 849-852, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Audip Pandit, Ali Akoglu |
Net Length based Routability Driven Packing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007, pp. 225-232, 2007, IEEE, 1-4244-1472-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yue Zhuo, Hao Li, Qiang Zhou 0001, Yici Cai, Xianlong Hong |
New timing and routability driven placement algorithms for FPGA synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 570-575, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
congestion driven placement, physical synthesis, timing driven placement, net weight |
19 | Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson |
Network coding for routability improvement in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 820-823, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005, 2005, IEEE Computer Society, 0-7695-2456-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Akshay Sharma, Carl Ebeling, Scott Hauck |
Architecture-Adaptive Routability-Driven Placement for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 427-432, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh |
Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 13(1), pp. 77-100, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Katherine Compton, Scott Hauck |
Track placement: orchestrating routing structures to maximize routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 241, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Jiping Liu, Hongbing Fan, Yu-Liang Wu |
On improving FPGA routability applying multi-level switch boxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 366-369, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Katherine Compton, Scott Hauck |
Track Placement: Orchestrating Routing Structures to Maximize Routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 121-130, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Victor N. Kravets, Prabhakar Kudva |
Understanding metrics in logic synthesis for routability enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 3-5, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
optimization, VLSI, synthesis, decomposition, layout, congestion, structure, circuits |
19 | Jun-seob Lee, Heeyoung Jung, Sung-han Kim, Seok Joo Koh, Jae Hong Min |
Return Routability Procedure between MAP and MN in HMIPv6. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Internet Computing ![In: Proceedings of the International Conference on Internet Computing, IC '03, Las Vegas, Nevada, USA, June 23-26, 2003, Volume 1, pp. 407-410, 2003, CSREA Press, 1-932415-00-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
19 | Yu-Jung Huang, Mei-hui Guo, Shen-Li Fu |
Reliability and routability consideration for MCM placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 42(1), pp. 83-91, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | William N. N. Hung, Xiaoyu Song, Alan J. Coppola, Andrew A. Kennings |
On segmented channel routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 169-172, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang |
Wire space estimation and routability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5), pp. 624-628, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai |
Efficient routability check algorithms for segmented channel routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 735-747, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
field programmable gate arryas (FPGAs), segmented channel, routing |
19 | Aman Shaikh, Anujan Varma, Lampros Kalampoukas, Rohit Dube |
Routability stability in congested networks: experimentation and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 2000 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, August 28 - September 1, 2000, Stockholm, Sweden, pp. 163-174, 2000, ACM, 1-58113-223-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh |
Routability-driven repeater block planning for interconnect-centric floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 186-191, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Tai Yan |
Routability Crossing Distribution and Floating Pin Assignment for T-type Junction Region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 10(2), pp. 155-167, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Kusnadi, Jo Dale Carothers |
A method of measuring nets routability for MCM's general area routing problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1999 International Symposium on Physical Design, ISPD 1999, Monterey, CA, USA, April 12-14, 1999, pp. 186-192, 1999, ACM, 1-58113-089-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Majid Sarrafzadeh, Toshihiko Takahashi |
A fast algorithm for routability testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 178-181, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | R. Glenn Wood, Rob A. Rutenbar |
FPGA Routing and Routability Estimation via Boolean Satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997, pp. 119-125, 1997, ACM, 0-89791-801-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Naoyuki Iso, Yasushi Kawaguchi, Tomio Hirata |
Efficient routability checking for global wires in planar layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 641-644, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Toshiyuki Hama, Hiroaki Etoh |
Topological routing path search algorithm with incremental routability test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 645-648, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama |
Not necessarily more switches more routability [sic.]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 579-584, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Stephen Dean Brown, Muhammad M. Khellah, Guy Lemieux |
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 4(4), pp. 275-291, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | F. Miller Maley |
Testing Homotopic Routability Under Polygonal Wiring Rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 15(1), pp. 1-16, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Joel Darnauer, Wayne Wei-Ming Dai |
A Method for Generating Random Circuits and Its Application to Routability Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996, pp. 66-72, 1996, ACM, 0-89791-773-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Yasuhiro Takashima, Atsushi Takahashi 0001, Yoji Kajitani |
Detailed-Routability of FPGAs with Extremal Switch-Block Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996, pp. 160-164, 1996, IEEE Computer Society, 0-8186-7423-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Kaushik Roy 0001, Sudip Nag |
On Routability for FPGAs under Faulty Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(11), pp. 1296-1305, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Yuh-Sheng Lee, Allen C.-H. Wu |
A Performance and Routability Driven Router for FPGAs Considering Path Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 557-561, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Om P. Agrawal |
A High Density Complex PLD Family Optimized for Flexibility, Predictability and 100% Routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, pp. 295-297, 1994, Springer, 3-540-58419-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Kaushik Roy 0001, Sudip Nag |
On Channel Architecture and Routability for FPGAs Under Faulty Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, pp. 361-372, 1994, Springer, 3-540-58419-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Tai Yan, Pei-Yung Hsiao |
Routability crossing distribution and floating terminal assignment of T-type junction region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994, pp. 162-165, 1994, IEEE, 0-8186-5610-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas |
Mathematical model for routability analysis of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994, pp. 76-79, 1994, IEEE, 0-8186-5610-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Mahesh Mehendale |
Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 233-236, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Keumog Ahn, Sartaj Sahni |
Flipping Modules to Improve Circuit Performance and Routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 127-132, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Kai Zhu 0001, D. F. Wong 0001 |
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994., pp. 165-170, 1994, ACM Press, 0-7803-1836-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Patrick Groeneveld |
Necessary and sufficient conditions for the routability of classical channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 16(1), pp. 59-74, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Massoud Pedram, Bahman S. Nobandegani, Bryan Preas |
Architecture and routability analysis for row-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, pp. 230-235, 1993, IEEE Computer Society / ACM, 0-8186-4490-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Kaushik Roy 0001, Sudip Nag, Santanu Dutta |
Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, pp. 220-223, 1993, IEEE Computer Society, 0-8186-4230-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien |
On Routability Prediction for Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 326-330, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
XILINX 3000 |
19 | Hirendu Vaishnav, Massoud Pedram |
Routability-Driven Fanout Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 230-235, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Martine D. F. Schlag, Jackson Kong, Pak K. Chan |
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 86-90, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Wayne Wei-Ming Dai, Raymond Kong, Masao Sato |
Routability of a Rubber-Band Sketch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 45-48, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Dick W. Harberts, Dré A. J. M. van den Elshout, Harry J. M. Veendrick |
Design for routability of a high-density gate array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990, pp. 56-59, 1990, IEEE Computer Society, 0-8186-2079-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Ten-Hwang Lai, Alan P. Sprague |
On the Routability of a Convex Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Algorithms ![In: J. Algorithms 8(3), pp. 372-384, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Charles E. Leiserson, F. Miller Maley |
Algorithms for Routing and Testing Routability of Planar VLSI Layouts ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 17th Annual ACM Symposium on Theory of Computing, May 6-8, 1985, Providence, Rhode Island, USA, pp. 69-78, 1985, ACM. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
19 | Hing-Cheung So |
Pin assignment of circuit cards and the routability of multilayer printed wiring backplanes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 10th Design Automation Workshop, DAC '73, Portland, Oregon, USA, June 25-27, 1973, pp. 33-43, 1973, ACM. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP BibTeX RDF |
|
11 | Lijuan Luo, Tan Yan, Qiang Ma 0002, Martin D. F. Wong, Toshiyuki Shibuya |
B-escape: a simultaneous escape routing algorithm based on boundary routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 19-25, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
PCB routing, dense circuit boards, computer-aided design, escape routing |
11 | Rupesh S. Shelar, Marek Patyra |
Impact of local interconnects on timing and power in a high performance microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 145-152, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CAD, delay, interconnects, power, microprocessor |
11 | Charles J. Alpert, Zhuo Li 0001, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez |
What makes a design difficult to route. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 7-12, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
congestion driven physical synthesis, routing |
11 | Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang |
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1), pp. 98-110, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Muhammet Mustafa Ozdal |
Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3), pp. 340-349, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Lijuan Luo, Martin D. F. Wong |
On using SAT to ordered escape problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 594-599, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer |
On improving optimization effectiveness in interconnect-driven physical synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 51-58, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
routing, interconnect, physical synthesis, circuit optimization, vlsi |
11 | Suresh Raman, Mike Lubyanitsky |
Cone Resynthesis ECO Methodology for Multi-Million Gate Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 195-199, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao |
Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 525-530, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu |
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1621-1634, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han |
Full-Chip Routing Considering Double-Via Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 844-857, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Minsik Cho, David Z. Pan |
A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1714-1724, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Tao Xu 0002, Krishnendu Chakrabarty |
Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(3), pp. 11:1-11:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Physical design automation, microfluidics, biochips, module placement |
11 | Mingjie Lin |
The amorphous FPGA architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 191-200, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
amorphous, FPGA, architecture, performance analysis |
11 | Tilo Meister, Jens Lienig, Gisbert Thomke |
Novel Pin Assignment Algorithms for Components with Very High Pin Counts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 837-842, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Minsik Cho, David Z. Pan |
A high-performance droplet router for digital microfluidic biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 200-206, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
routing, synthesis, microfluidics, biochip |
11 | Shiyan Hu, Zhuo Li 0001, Charles J. Alpert |
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 112-115, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang |
Multi-layer global routing considering via and wire capacities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 350-355, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Yanheng Zhang, Yue Xu, Chris Chu |
FastRoute3.0: a fast and high quality global router based on virtual capacity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 344-349, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Jia-Wei Fang, Yao-Wen Chang |
Area-I/O flip-chip routing for chip-package co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 518-522, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang |
Routing for chip-package-board co-design considering differential pairs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 512-517, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Jin Hu, Jarrod A. Roy, Igor L. Markov |
Sidewinder: a scalable ILP-based router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 73-80, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
integer linear programming, global routing |
11 | Hidetoshi Kobayashi, Kazumasa Takami |
Algorithm for Selecting either an Overlay or Flat Route Based on the Amount of the Delay Measurement Load on the Home Agent in a Hierarchical Mobile IPv6 Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEW2AN ![In: Next Generation Teletraffic and Wired/Wireless Advanced Networking, 8th International Conference, NEW2AN and 1st Russian Conference on Smart Spaces, ruSMART 2008, St. Petersburg, Russia, September 3-5, 2008. Proceedings, pp. 234-245, 2008, Springer, 978-3-540-85499-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Packet delay, Route Selection, Hierarchical Mobile IPv6 |
11 | Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan |
An integrated nonlinear placement framework with congestion and porosity aware buffer planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 702-707, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
VLSI, placement, physical design, buffer |
11 | Tai-Chen Chen, Yao-Wen Chang |
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 1041-1053, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Chiu-Wing Sham, Evangeline F. Y. Young |
Area reduction by deadspace utilization on interconnect optimized floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 3:1-3:11, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
area reduction, Floorplanning |
11 | Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez |
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 243-252, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore |
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 283-294, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen |
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 804-809, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu 0002, Lei He 0001, Xianlong Hong |
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 256-261, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Seonggeun Ryu, Youngsong Mun |
A Scheme to Enhance TEBU Scheme of Fast Handovers for Mobile IPv6. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 773-782, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Philip Chong, Christian Szegedy |
A morphing approach to address placement stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 95-102, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
incremental placement, stability, morphing |
11 | Eunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang |
Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 573-579, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Chen Li 0004, Cheng-Kok Koh |
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 829-834, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang |
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 606-611, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Muhammet Mustafa Ozdal |
Escape Routing For Dense Pin Clusters In Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 49-54, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Tao Xu 0002, Krishnendu Chakrabarty |
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 948-953, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu |
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 447-452, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Yajun Ran, Malgorzata Marek-Sadowska |
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(9), pp. 998-1009, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Lihong Zhang, Ulrich Kleine, Yingtao Jiang |
An automated design tool for analog layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 881-894, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | PariVallal Kannan, Dinesh Bhatia |
Interconnect estimation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1523-1534, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Andrew B. Kahng, Sherief Reda |
Wirelength minimization for min-cut placements via placement feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7), pp. 1301-1312, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Gang Chen 0020, Jason Cong |
Simultaneous placement with clustering and duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(3), pp. 740-772, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
clustering, FPGA, Placement, legalization, duplication, redundancy removal |
11 | Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake |
Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 38-43, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Claudio Menezes, Cristina Meinhardt, Ricardo Reis 0001, Reginaldo Tavares |
A Regular Layout Approach for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 424-425, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
Configuration tools for a new multilevel hierarchical FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 229, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin |
A novel framework for multilevel full-chip gridless routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 636-641, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang |
NTUplace2: a hybrid placer using partitioning and analytical techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 215-217, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
placement, physical design, legalization |