Search results for "Clocking"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Zheng Xu 0003, Kenneth L. Shepard	Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking.	CICC	2007	DBLP DOI BibTeX RDF
18	Lin Zhang, Berkehan Ciftcioglu, Hui Wu	A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking.	CICC	2007	DBLP DOI BibTeX RDF
18	Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication.	CICC	2007	DBLP DOI BibTeX RDF
18	Thucydides Xanthopoulos, Atila Alvandpour	Clocking.	ISSCC	2007	DBLP DOI BibTeX RDF
18	Sherif A. Tawfik, Volkan Kursun	Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Ganesh Venkataraman, Jiang Hu	A Placement Methodology for Robust Clocking.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Michael J. Gilsdorf	A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
18	Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown	A 16-bit, low-power microsystem with monolithic MEMS-LC clocking.	ASP-DAC	2006	DBLP DOI BibTeX RDF
18	Chunsheng Liu	Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking.	ATS	2006	DBLP DOI BibTeX RDF
18	Lin Zhang, Berkehan Ciftcioglu, Michael C. Huang 0001, Hui Wu	Injection-Locked Clocking: A New GHz Clock Distribution Scheme.	CICC	2006	DBLP DOI BibTeX RDF
18	Martin Hansson, Behzad Mesgarzadeh, Atila Alvandpour	1.56 GHz On-chip Resonant Clocking in 130nm CMOS.	CICC	2006	DBLP DOI BibTeX RDF
18	Kuan-Ta Chen, Polly Huang, Chun-Ying Huang, Chin-Laung Lei	The Impact of Network Variabilities on TCP Clocking Schemes.	INFOCOM	2006	DBLP DOI BibTeX RDF
18	Zhiyi Yu, Bevan M. Baas	Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.	ICCD	2006	DBLP DOI BibTeX RDF
18	Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown	Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang	Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
18	David R. Rolston, David M. Gross, Gordon W. Roberts, David V. Plant	A Distributed Synchronized Clocking Method.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
18	Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail	Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.	DSN	2005	DBLP DOI BibTeX RDF
18	Phillip J. Restle, Kenneth L. Shepard	New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems.	ASYNC	2005	DBLP DOI BibTeX RDF
18	Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki	A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.	CICC	2005	DBLP DOI BibTeX RDF
18	Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Jim O. Barnes, Robert A. Zimmer, Kari L. Arave, H. Herman M. Pang, Tom E. Cynkar, Aaron M. Volz, Jim R. Pfiester, R. J. Martin, Robert H. Miller, David A. Hood, Gordon W. Motley, Ed J. Rojas, Tom M. Walley, Michael J. Gilsdorf	A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking.	CICC	2005	DBLP DOI BibTeX RDF
18	Jafar Savoj, Ramesh Harjani	Clocking circuits for wireline communications.	CICC	2005	DBLP DOI BibTeX RDF
18	Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale	A 16-bit low-power microcontroller with monolithic MEMS-LC clocking.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown	Resonant clocking using distributed parasitic capacitance.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
18	Farhad H. A. Asgari, Manoj Sachdev	A low-power reduced swing global clocking methodology.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
18	Oswaldo Cadenas, Graham M. Megson	A clocking technique for FPGA pipelined designs.	J. Syst. Archit.	2004	DBLP DOI BibTeX RDF
18	Michael M. Yang, James A. Barby	A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit.	ISCAS (2)	2004	DBLP BibTeX RDF
18	Behzad Mesgarzadeh, Christer Svensson, Atila Alvandpour	A new mesochronous clocking scheme for synchronization in SoC.	ISCAS (2)	2004	DBLP BibTeX RDF
18	Vojin G. Oklobdzija	Clocking and clocked storage elements in a multi-gigahertz environment.	IBM J. Res. Dev.	2003	DBLP DOI BibTeX RDF
18	Takayuki Daimon, Hiroshi Sadamura, Takayuki Shindou, Haruo Kobayashi 0001, Masashi Kono, Takao Myono, Tatsuya Suzuki, Shuhei Kawai, Takashi Iijima	Spread-Spectrum Clocking in Switching Regulators for EMI Reduction.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
18	Johnny Öberg	Clocking Strategies for Networks-on-Chip.	Networks on Chip	2003	DBLP DOI BibTeX RDF
18	Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Bums, Richard B. Brown	Resonant clocking using distributed parasitic capacitance.	CICC	2003	DBLP DOI BibTeX RDF
18	Vojin G. Oklobdzija, Jens Sparsø	Future directions in clocking multi-ghz systems.	ISLPED	2002	DBLP DOI BibTeX RDF
18	Thanh T. Tran, Richard Liu	Gated direct sequence spread spectrum clocking scheme for multimedia systems.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
18	Nasser A. Kurd, Javed S. Barkatullah, Rommel O. Dizon, Thomas D. Fletcher, Paul D. Madland	A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
18	Victor V. Zyuban, David Meltzer	Clocking strategies and scannable latches for low power appliacations.	ISLPED	2001	DBLP DOI BibTeX RDF
18	Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park	An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking.	ICCD	2001	DBLP DOI BibTeX RDF
18	Andrew T. K. Tang	Bandpass spread spectrum clocking for reduced clock spurs in autozeroed amplifiers.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
18	Christl Lauterbach, Werner Weber, Dirk Romer	Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
18	Antonio J. Acosta 0001, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero	Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.	PATMOS	2000	DBLP BibTeX RDF
18	Yuh-Kuang Tseng, Chung-Yu Wu	A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
18	Kenneth Y. Yun, Ayoob E. Dooply	Pausible clocking-based heterogeneous systems.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
18	Sanghyeon Baeg, William A. Rogers	A cost-effective design for testability: clock line control and test generation using selective clocking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
18	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
18	Daniel W. Bailey, Bradley J. Benschneider	Clocking design and analysis for a 600-MHz Alpha microprocessor.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
18	Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar	A linear array processor with dynamic frequency clocking for image processing applications.	IEEE Trans. Circuits Syst. Video Technol.	1998	DBLP DOI BibTeX RDF
18	Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina	A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
18	Mitsuhisa Ohnishi, Akihisa Yamada 0001, Hiroaki Noda, Takashi Kambe	A method of redundant clocking detection and power reduction at RT level design.	ISLPED	1997	DBLP DOI BibTeX RDF
18	Gerard M. Blair	Comments on "A robust single phase clocking for low power, high-speed VLSI applications" [and reply].	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
18	Peter Nilsson 0001, Mats Torkelson	A monolithic digital clock-generator for on-chip clocking of custom DSP's.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
18	M. Afghahi	A robust single phase clocking for low power, high-speed VLSI applications.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
18	M. Afghahi	Author's Reply to Comments on "A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applica.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
18	F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	A 650 MHz pipelined MAC for DSP applications using a new clocking strategy.	EUSIPCO	1996	DBLP BibTeX RDF
18	Ahmed El-Amawy, Maheshwar Umasankar	A Comparative Study of Synchronous Clocking Schemes for VLSI Based Systems.	VLSI Design	1995	DBLP DOI BibTeX RDF
18	F. Fernández, A. Sánchez	Design and Optimization of MuItiphase Clocking Systolic Architectures using Algebraic Retiming Techniques: Extension to Regular Graphs.	PARCO	1995	DBLP BibTeX RDF
18	Rafael Peset Llopis	Path sensitization of combinational circuits and its impact on clocking of sequential systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
18	Christos A. Papachristou, Mark Spining, Mehrdad Nourani	A multiple clocking scheme for low power RTL design.	ISLPD	1995	DBLP DOI BibTeX RDF
18	Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu	Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.	ISCAS	1995	DBLP BibTeX RDF
18	Seokjin Kim, Ramalingam Sridhar	A local clocking approach for self-timed datapath designs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
18	Sanghyeon Baeg, William A. Rogers	A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits.	ICCD	1994	DBLP DOI BibTeX RDF
18	Shangzhi Sun, David Hung-Chang Du, Yaun-Chung Hsu, Hsi-Chuan Chen	On Valid Clocking for Combinational Circuits.	ICCD	1994	DBLP DOI BibTeX RDF
18	Dinesh Somasekhar, V. Visvanathan	A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
18	Dinesh Somasekhar, V. Visvanathan	A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking.	VLSI Design	1993	DBLP DOI BibTeX RDF
18	Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah	Using constraint geometry to determine maximum rate pipeline clocking.	ICCAD	1992	DBLP DOI BibTeX RDF
18	William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Valid clocking in wavepipelined circuits.	ICCAD	1992	DBLP DOI BibTeX RDF
18	C. Safina, Régis Leveugle	Clocking scheme selection for circuits made up of a controller and a datapath.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
18	Masakiyo Miyazawa	The Characterization of the Stationary Distribution of the Supplemented Self-Clocking Jump Process.	Math. Oper. Res.	1991	DBLP DOI BibTeX RDF
18	Zebo Peng	Design of clocking schemes in high-level synthesis.	Microprocessing and Microprogramming	1991	DBLP DOI BibTeX RDF
18	Marios D. Dikaiakos, Kenneth Steiglitz	Comparison of tree and straight-line clocking for long systolic arrays.	ICASSP	1991	DBLP DOI BibTeX RDF
18	Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson	Optimal Clocking of Circular Pipelines.	ICCD	1991	DBLP DOI BibTeX RDF
18	Ahmed El-Amawy	Branch-and-Combine Clocking of Arbitrarily Large Computing Networks.	ICPP (1)	1991	DBLP BibTeX RDF
18	Somanathan C. Menon, Karem A. Sakallah	Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and On-section Clock Derivation.	ICSI	1990	DBLP BibTeX RDF
18	Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun	check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits.	ICCAD	1990	DBLP DOI BibTeX RDF
18	Paul R. Prucnal, Phillppe A. Perrier, Carollynn Brandmaier	A low DC, self-clocking, two-color transmission code for optical communications.	Proc. IEEE	1987	DBLP DOI BibTeX RDF
18	Paul R. Prucnal, Philippe A. Perrier	A rate-transparent, self-clocking line code.	Proc. IEEE	1987	DBLP DOI BibTeX RDF
18	A. J. Field, M. D. Cripps	Self-Clocking Networks.	ICPP	1985	DBLP BibTeX RDF
18	Joep L. W. Kessels	Two Designs of a Fault-Tolerant Clocking System.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF
18	Grzegorz Rozenberg, Sebastiaan H. von Solms	Rewriting systems with a clocking mechanism.	Inf. Sci.	1978	DBLP DOI BibTeX RDF
18	Se June Hong, Daniel L. Ostapko	Codes for Self-Clocking, AC-Coupled Transmission: Aspects of Synthesis and Analysis.	IBM J. Res. Dev.	1975	DBLP DOI BibTeX RDF
18	Andrew Gabor	Adaptive Coding for Self-Clocking Recording.	IEEE Trans. Electron. Comput.	1967	DBLP DOI BibTeX RDF
18	Leonard D. Seader	A Self-Clocking System for Information Transfer.	IBM J. Res. Dev.	1957	DBLP DOI BibTeX RDF
10	Xin-Wei Shih, Yao-Wen Chang	Fast timing-model independent buffered clock-tree synthesis.	DAC	2010	DBLP DOI BibTeX RDF
10	Khaled Z. Ibrahim, Smaïl Niar	Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
10	Robert Meagher, Modukuri Sushmitha, Maher E. Rizkalla, Paul Salama, Mohamed El-Sharkawy 0001	VHDL Design for Real Time Motion Estimation Video Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	simulation, Real time, Motion estimation, Hardware, Video compression
10	Thomas Polzer, Thomas Handl, Andreas Steininger	A Metastability-Free Multi-synchronous Communication Scheme for SoCs.	SSS	2009	DBLP DOI BibTeX RDF
10	Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
10	Takashi Kawamoto, Masaru Kokubo	A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA.	ASP-DAC	2009	DBLP DOI BibTeX RDF
10	Mohaned Kafi, Sylvain Guilley, Sandra Marcello, David Naccache	Deconvolving Protected Signals.	ARES	2009	DBLP DOI BibTeX RDF
10	Muhammad Aqeel Wahlah, Kees Goossens	Modeling reconfiguration in a FPGA with a hardwired network on chip.	IPDPS	2009	DBLP DOI BibTeX RDF
10	Emre Tuncer, Jordi Cortadella, Luciano Lavagno	Enabling adaptability through elastic clocks.	DAC	2009	DBLP DOI BibTeX RDF	low power design, GALS, desynchronization, adaptive voltage scaling
10	Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi	An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Siddharth Garg, Diana Marculescu	System-level throughput analysis for process variation aware multiple voltage-frequency island designs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	manufacturing process variations, maximum cycle mean, voltage-frequency islands, performance analysis, system-level design, Globally asynchronous locally synchronous
10	Chun-Lung Hsu, Yu-Sheng Huang	A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter
10	Simon Ogg, Enrico Valli, Bashir M. Al-Hashimi, Alexandre Yakovlev, Crescenzo D'Alessandro, Luca Benini	Serialized Asynchronous Links for NoC.	DATE	2008	DBLP DOI BibTeX RDF
10	Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary	An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System.	DATE	2008	DBLP DOI BibTeX RDF
10	Somashekar Bangalore Prakash, Pamela Abshire	A fully differential CMOS capacitance sensor design, testing and array architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Chih-Hung Li, Wen-Hsiao Peng, Tihao Chiang	A reconfigurable video embedding transcoder based on H.264/AVC: Design tradeoffs and analysis.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Safar Hatami, Hamed Abrishami, Massoud Pedram	Statistical timing analysis of flip-flops considering codependent setup and hold times.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time
10	Jeff Mueller, Resve A. Saleh	A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks.	ISQED	2008	DBLP DOI BibTeX RDF
10	Charbel J. Akl, Magdy A. Bayoumi	Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.	ISQED	2008	DBLP DOI BibTeX RDF	circuit family, low-power, high-speed
10	Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang	Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF