Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Zheng Xu 0003, Kenneth L. Shepard |
Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 9-12, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Lin Zhang, Berkehan Ciftcioglu, Hui Wu |
A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 309-312, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 451-454, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Thucydides Xanthopoulos, Atila Alvandpour |
Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007, pp. 170-171, 2007, IEEE, 1-4244-0853-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Sherif A. Tawfik, Volkan Kursun |
Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 645-648, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Ganesh Venkataraman, Jiang Hu |
A Placement Methodology for Robust Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 881-886, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Michael J. Gilsdorf |
A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(8), pp. 1894-1907, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown |
A 16-bit, low-power microsystem with monolithic MEMS-LC clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 94-95, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Chunsheng Liu |
Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 431-436, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Lin Zhang, Berkehan Ciftcioglu, Michael C. Huang 0001, Hui Wu |
Injection-Locked Clocking: A New GHz Clock Distribution Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006, pp. 785-788, 2006, IEEE, 1-4244-0075-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Martin Hansson, Behzad Mesgarzadeh, Atila Alvandpour |
1.56 GHz On-chip Resonant Clocking in 130nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006, pp. 241-244, 2006, IEEE, 1-4244-0075-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Kuan-Ta Chen, Polly Huang, Chun-Ying Huang, Chin-Laung Lei |
The Impact of Network Variabilities on TCP Clocking Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2006. 25th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 23-29 April 2006, Barcelona, Catalunya, Spain, 2006, IEEE, 1-4244-0221-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Zhiyi Yu, Bevan M. Baas |
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, pp. 174-179, 2006, IEEE, 978-0-7803-9707-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown |
Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang |
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | David R. Rolston, David M. Gross, Gordon W. Roberts, David V. Plant |
A Distributed Synchronized Clocking Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8), pp. 1597-1607, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail |
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings, pp. 770-779, 2005, IEEE Computer Society, 0-7695-2282-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Phillip J. Restle, Kenneth L. Shepard |
New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki |
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005, pp. 527-530, 2005, IEEE, 0-7803-9023-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Jim O. Barnes, Robert A. Zimmer, Kari L. Arave, H. Herman M. Pang, Tom E. Cynkar, Aaron M. Volz, Jim R. Pfiester, R. J. Martin, Robert H. Miller, David A. Hood, Gordon W. Motley, Ed J. Rojas, Tom M. Walley, Michael J. Gilsdorf |
A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005, pp. 553-556, 2005, IEEE, 0-7803-9023-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Jafar Savoj, Ramesh Harjani |
Clocking circuits for wireline communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005, pp. 526-527, 2005, IEEE, 0-7803-9023-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale |
A 16-bit low-power microcontroller with monolithic MEMS-LC clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 624-627, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown |
Resonant clocking using distributed parasitic capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(9), pp. 1520-1528, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Farhad H. A. Asgari, Manoj Sachdev |
A low-power reduced swing global clocking methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(5), pp. 538-545, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Oswaldo Cadenas, Graham M. Megson |
A clocking technique for FPGA pipelined designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 50(11), pp. 687-696, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Michael M. Yang, James A. Barby |
A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 289-292, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
18 | Behzad Mesgarzadeh, Christer Svensson, Atila Alvandpour |
A new mesochronous clocking scheme for synchronization in SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 605-608, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
18 | Vojin G. Oklobdzija |
Clocking and clocked storage elements in a multi-gigahertz environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 47(5-6), pp. 567-584, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Takayuki Daimon, Hiroshi Sadamura, Takayuki Shindou, Haruo Kobayashi 0001, Masashi Kono, Takao Myono, Tatsuya Suzuki, Shuhei Kawai, Takashi Iijima |
Spread-Spectrum Clocking in Switching Regulators for EMI Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2), pp. 381-386, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
18 | Johnny Öberg |
Clocking Strategies for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 153-172, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Bums, Richard B. Brown |
Resonant clocking using distributed parasitic capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 647-650, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Vojin G. Oklobdzija, Jens Sparsø |
Future directions in clocking multi-ghz systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 219, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Thanh T. Tran, Richard Liu |
Gated direct sequence spread spectrum clocking scheme for multimedia systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 173-176, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Nasser A. Kurd, Javed S. Barkatullah, Rommel O. Dizon, Thomas D. Fletcher, Paul D. Madland |
A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(11), pp. 1647-1653, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Victor V. Zyuban, David Meltzer |
Clocking strategies and scannable latches for low power appliacations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 346-351, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park |
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 511-512, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Andrew T. K. Tang |
Bandpass spread spectrum clocking for reduced clock spurs in autozeroed amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 663-666, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Christl Lauterbach, Werner Weber, Dirk Romer |
Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 35(5), pp. 719-723, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Antonio J. Acosta 0001, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero |
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 316-326, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
18 | Yuh-Kuang Tseng, Chung-Yu Wu |
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(1), pp. 68-79, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Kenneth Y. Yun, Ayoob E. Dooply |
Pausible clocking-based heterogeneous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 482-488, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Sanghyeon Baeg, William A. Rogers |
A cost-effective design for testability: clock line control and test generation using selective clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), pp. 850-861, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Ayoob E. Dooply, Kenneth Y. Yun |
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 200-214, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault |
18 | Daniel W. Bailey, Bradley J. Benschneider |
Clocking design and analysis for a 600-MHz Alpha microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 33(11), pp. 1627-1633, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar |
A linear array processor with dynamic frequency clocking for image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 8(4), pp. 435-445, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina |
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(11), pp. 1807-1816, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Mitsuhisa Ohnishi, Akihisa Yamada 0001, Hiroaki Noda, Takashi Kambe |
A method of redundant clocking detection and power reduction at RT level design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997, Monterey, California, USA, August 18-20, 1997, pp. 131-136, 1997, ACM, 0-89791-903-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Gerard M. Blair |
Comments on "A robust single phase clocking for low power, high-speed VLSI applications" [and reply]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(12), pp. 2060-2061, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Peter Nilsson 0001, Mats Torkelson |
A monolithic digital clock-generator for on-chip clocking of custom DSP's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(5), pp. 700-706, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | M. Afghahi |
A robust single phase clocking for low power, high-speed VLSI applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(2), pp. 247-254, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | M. Afghahi |
Author's Reply to Comments on "A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applica. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(12), pp. 2061, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni |
A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 8th European Signal Processing Conference, EUSIPCO 1996, Trieste, Italy, 10-13 September, 1996, pp. 1-4, 1996, IEEE, 978-888-6179-83-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP BibTeX RDF |
|
18 | Ahmed El-Amawy, Maheshwar Umasankar |
A Comparative Study of Synchronous Clocking Schemes for VLSI Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 3(1), pp. 81-92, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | F. Fernández, A. Sánchez |
Design and Optimization of MuItiphase Clocking Systolic Architectures using Algebraic Retiming Techniques: Extension to Regular Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARCO ![In: Parallel Computing: State-of-the-Art and Perspectives, Proceedings of the conference ParCo 1995, Gent, Belgium, September 1995, pp. 605-608, 1995, Elsevier, 0-444-82490-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
18 | Rafael Peset Llopis |
Path sensitization of combinational circuits and its impact on clocking of sequential systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 210-215, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Christos A. Papachristou, Mark Spining, Mehrdad Nourani |
A multiple clocking scheme for low power RTL design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPD ![In: Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995, pp. 27-32, 1995, ACM, 0-89791-744-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu |
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 1572-1575, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
18 | Seokjin Kim, Ramalingam Sridhar |
A local clocking approach for self-timed datapath designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 152-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits |
18 | Sanghyeon Baeg, William A. Rogers |
A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 354-358, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Shangzhi Sun, David Hung-Chang Du, Yaun-Chung Hsu, Hsi-Chuan Chen |
On Valid Clocking for Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 381-384, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Dinesh Somasekhar, V. Visvanathan |
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 415-422, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Dinesh Somasekhar, V. Visvanathan |
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 347-350, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah |
Using constraint geometry to determine maximum rate pipeline clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers, pp. 142-148, 1992, IEEE Computer Society / ACM, 0-8186-3010-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Valid clocking in wavepipelined circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers, pp. 518-525, 1992, IEEE Computer Society / ACM, 0-8186-3010-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | C. Safina, Régis Leveugle |
Clocking scheme selection for circuits made up of a controller and a datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Synthesis for Control Dominated Circuits ![In: Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992, pp. 293-308, 1992, North-Holland, 0-444-81479-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
18 | Masakiyo Miyazawa |
The Characterization of the Stationary Distribution of the Supplemented Self-Clocking Jump Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Oper. Res. ![In: Math. Oper. Res. 16(3), pp. 547-565, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
18 | Zebo Peng |
Design of clocking schemes in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocessing and Microprogramming ![In: Microprocessing and Microprogramming 31(1-5), pp. 71-74, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
18 | Marios D. Dikaiakos, Kenneth Steiglitz |
Comparison of tree and straight-line clocking for long systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1991 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '91, Toronto, Ontario, Canada, May 14-17, 1991, pp. 1177-1180, 1991, IEEE Computer Society, 0-7803-0003-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
18 | Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson |
Optimal Clocking of Circular Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 642-650, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
18 | Ahmed El-Amawy |
Branch-and-Combine Clocking of Arbitrarily Large Computing Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the International Conference on Parallel Processing, ICPP '91, Austin, Texas, USA, August 1991. Volume I: Architecture/Hardware., pp. 409-417, 1991, CRC Press. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
18 | Somanathan C. Menon, Karem A. Sakallah |
Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and On-section Clock Derivation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSI ![In: Proceedings of the First International Conference on Systems Integration, Morristown, NJ, USA, April 1990, pp. 550-558, 1990, IEEE Computer Society, 0-8186-9027-5. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
18 | Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun |
check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 552-555, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
18 | Paul R. Prucnal, Phillppe A. Perrier, Carollynn Brandmaier |
A low DC, self-clocking, two-color transmission code for optical communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 75(6), pp. 856-858, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
18 | Paul R. Prucnal, Philippe A. Perrier |
A rate-transparent, self-clocking line code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 75(8), pp. 1123-1125, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
18 | A. J. Field, M. D. Cripps |
Self-Clocking Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: International Conference on Parallel Processing, ICPP'85, University Park, PA, USA, August 1985., pp. 384-387, 1985, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP BibTeX RDF |
|
18 | Joep L. W. Kessels |
Two Designs of a Fault-Tolerant Clocking System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(10), pp. 912-919, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
18 | Grzegorz Rozenberg, Sebastiaan H. von Solms |
Rewriting systems with a clocking mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Sci. ![In: Inf. Sci. 14(3), pp. 221-280, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
|
18 | Se June Hong, Daniel L. Ostapko |
Codes for Self-Clocking, AC-Coupled Transmission: Aspects of Synthesis and Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 19(4), pp. 358-365, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
|
18 | Andrew Gabor |
Adaptive Coding for Self-Clocking Recording. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Electron. Comput. ![In: IEEE Trans. Electron. Comput. 16(6), pp. 866-868, 1967. The full citation details ...](Pics/full.jpeg) |
1967 |
DBLP DOI BibTeX RDF |
|
18 | Leonard D. Seader |
A Self-Clocking System for Information Transfer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 1(2), pp. 181-184, 1957. The full citation details ...](Pics/full.jpeg) |
1957 |
DBLP DOI BibTeX RDF |
|
10 | Xin-Wei Shih, Yao-Wen Chang |
Fast timing-model independent buffered clock-tree synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 80-85, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
10 | Khaled Z. Ibrahim, Smaïl Niar |
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers II, pp. 286-306, 2009, Springer, 978-3-642-00903-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Robert Meagher, Modukuri Sushmitha, Maher E. Rizkalla, Paul Salama, Mohamed El-Sharkawy 0001 |
VHDL Design for Real Time Motion Estimation Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(3), pp. 339-348, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulation, Real time, Motion estimation, Hardware, Video compression |
10 | Thomas Polzer, Thomas Handl, Andreas Steininger |
A Metastability-Free Multi-synchronous Communication Scheme for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSS ![In: Stabilization, Safety, and Security of Distributed Systems, 11th International Symposium, SSS 2009, Lyon, France, November 3-6, 2009. Proceedings, pp. 578-592, 2009, Springer, 978-3-642-05117-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi |
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 469-480, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Takashi Kawamoto, Masaru Kokubo |
A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 696-701, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Mohaned Kafi, Sylvain Guilley, Sandra Marcello, David Naccache |
Deconvolving Protected Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Forth International Conference on Availability, Reliability and Security, ARES 2009, March 16-19, 2009, Fukuoka, Japan, pp. 687-694, 2009, IEEE Computer Society, 978-1-4244-3572-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Muhammad Aqeel Wahlah, Kees Goossens |
Modeling reconfiguration in a FPGA with a hardwired network on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Emre Tuncer, Jordi Cortadella, Luciano Lavagno |
Enabling adaptability through elastic clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 8-10, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power design, GALS, desynchronization, adaptive voltage scaling |
10 | Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi |
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1187-1198, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Siddharth Garg, Diana Marculescu |
System-level throughput analysis for process variation aware multiple voltage-frequency island designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 59:1-59:25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
manufacturing process variations, maximum cycle mean, voltage-frequency islands, performance analysis, system-level design, Globally asynchronous locally synchronous |
10 | Chun-Lung Hsu, Yu-Sheng Huang |
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 211-229, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter |
10 | Simon Ogg, Enrico Valli, Bashir M. Al-Hashimi, Alexandre Yakovlev, Crescenzo D'Alessandro, Luca Benini |
Serialized Asynchronous Links for NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1003-1008, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary |
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1160-1165, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Somashekar Bangalore Prakash, Pamela Abshire |
A fully differential CMOS capacitance sensor design, testing and array architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 165-168, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Chih-Hung Li, Wen-Hsiao Peng, Tihao Chiang |
A reconfigurable video embedding transcoder based on H.264/AVC: Design tradeoffs and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 852-855, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Safar Hatami, Hamed Abrishami, Massoud Pedram |
Statistical timing analysis of flip-flops considering codependent setup and hold times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 101-106, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time |
10 | Jeff Mueller, Resve A. Saleh |
A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 572-577, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Charbel J. Akl, Magdy A. Bayoumi |
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 385-390, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
circuit family, low-power, high-speed |
10 | Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang |
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 881-894, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|