Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Shih-Hsu Huang, Chun-Hua Cheng |
Timing driven power gating in high-level synthesis. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Mohammed Abid Hussain, Madhu Mutyam |
Block remap with turnoff: A variation-tolerant cache design technique. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Andrew B. Kahng |
How to get real mad. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability |
30 | Benedikt Gierlichs, Lejla Batina, Pim Tuyls, Bart Preneel |
Mutual Information Analysis. |
CHES |
2008 |
DBLP DOI BibTeX RDF |
Differential Side-Channel Analysis (DSCA), DPA-resistant logic, Information Theory, Mutual Information |
30 | Zhiyu Liu, Volkan Kursun |
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis |
High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Kimiyoshi Usami |
Overview on Low Power SoC Design Technology. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Samuel Rodríguez, Bruce L. Jacob |
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
nanometer design, pipelined caches, cache design |
30 | Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi |
A Case for Asymmetric-Cell Cache Memories. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Jaume Abella 0001, Antonio González 0001, Xavier Vera, Michael F. P. O'Boyle |
IATAC: a smart predictor to turn-off L2 cache lines. |
ACM Trans. Archit. Code Optim. |
2005 |
DBLP DOI BibTeX RDF |
turning off cache lines, low power, Cache memories, L2 cache |
30 | Weiping Liao, Lei He 0001 |
Coupled Power and Thermal Simulation with Active Cooling. |
PACS |
2003 |
DBLP DOI BibTeX RDF |
|
30 | S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay |
Customizing pattern set for test power reduction via improved X-identification and reordering. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
don't care bits, runtime leakage power, vector reordering, x-fill, dynamic power |
30 | Sreeharsha Tavva, Dhireesha Kudithipudi |
Variation tolerant 9T SRAM cell design. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
bitline leakage, static random access memory (SRAM), process variations, static noise margin, embedded sram |
30 | Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee |
Compilation for compact power-gating controls. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction |
30 | Ravishankar Rao, Sarma B. K. Vrudhula |
Performance optimal processor throttling under thermal constraints. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
leakage dependence on temperature, power, thermal management, thermal model, throttling |
30 | Christoph Kutter |
Design challenges for mobile communication devices. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
design for low power, SoC, leakage |
30 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail |
Power density minimization for highly-associative caches in embedded processors. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
cache, embedded processor, leakage power, temperature |
30 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao 0001 |
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
Karhunen-Loeve, intra-die, correlations, process variations, statistical, leakage |
30 | Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet |
The "Backend Duplication" Method. |
CHES |
2005 |
DBLP DOI BibTeX RDF |
secured backend, differential signals, Information leakage |
30 | Karthik Sankaranarayanan, Kevin Skadron |
Profile-based adaptation for cache decay. |
ACM Trans. Archit. Code Optim. |
2004 |
DBLP DOI BibTeX RDF |
Adaptation, leakage power, interval, cache decay |
30 | Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong |
An MTCMOS design methodology and its application to mobile computing. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
CPFF, low power, leakage current, CCS, MTCMOS |
30 | Amit Agarwal 0001, Hai Li, Kaushik Roy 0001 |
DRG-cache: a data retention gated-ground cache for low power. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
gated-ground, low leakage cache, SRAM |
30 | Adam L. Young, Moti Yung |
Bandwidth-Optimal Kleptographic Attacks. |
CHES |
2001 |
DBLP DOI BibTeX RDF |
Leakage attacks, the Newton channel, design methodologies for asymmetric ciphers, kleptographic attacks, attack bandwidth, discrete logarithm based systems, tamper-proof hardware designs, public scrutiny, hardware technologies: EEPROM, ferroelectric, trust, DSA, ElGamal, subliminal channels, non-volatile memory |
30 | Liqiong Wei, Kaushik Roy 0001, Vivek De |
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
low voltage low power, multiple threshold voltages, multiple supply voltages and leakage control |
30 | David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards |
Emerging power management tools for processor design. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
low power CAD, standby leakage, power distribution |
30 | Zhiyu Liu, Volkan Kursun |
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage |
27 | Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano |
Cache Controller Design on Ultra Low Leakage Embedded Processors. |
ARCS |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong |
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Xin He, Syed Al-Kadry, Afshin Abdollahi |
Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Yongwen Pan, Man Lin |
Dynamic leakage aware power management with procrastination method. |
CCECE |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry |
A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Andreas Frotzscher, Gerhard P. Fettweis |
A Stochastic Gradient LMS Algorithm for Digital Compensation of Tx Leakage in Zero-IF-Receivers. |
VTC Spring |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Tadayoshi Enomoto, Yuki Higuchi |
A low-leakage current power 180-nm CMOS SRAM. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Leilei Li, Jonathon A. Chambers |
A novel adaptive leakage factor scheme for enhancement of a variable tap-length learning algorithm. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Pasquale Malacaria, Han Chen |
Lagrange multipliers and maximum information leakage in different observational models. |
PLAS |
2008 |
DBLP DOI BibTeX RDF |
security, information theory, lagrange multipliers |
27 | Hushrav Mogal, Kia Bazargan |
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Ieng-Fat Lam, Kuan-Ta Chen, Ling-Jyh Chen |
Involuntary Information Leakage in Social Network Services. |
IWSEC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Weixiang Shen, Yici Cai, Xianlong Hong |
Leakage power optimization for clock network using dual-Vth technology. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Saraju P. Mohanty |
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Tao Li, Zhiping Yu |
Full-Chip Leakage Verification for Manufacturing Considering Process Variations. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Sherif A. Tawfik, Volkan Kursun |
Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Akhilesh Kumar, Mohab Anis |
Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Juan M. Cebrian, Juan L. Aragón, José M. García 0001 |
Leakage Energy Reduction in Value Predictors through Static Decay. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Kiyofumi Tanaka, Takenori Fujita |
Leakage Energy Reduction in Cache Memory by Software Self-invalidation. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Mrinmoy Ghosh, Hsien-Hsin S. Lee |
Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems. |
ICPADS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Kazuhisa Suzuki, Koichi Mouri, Eiji Okubo |
Salvia : A Privacy-Aware Operating System for Prevention of Data Leakage. |
IWSEC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Zhiyu Liu, Volkan Kursun |
High Read Stability and Low Leakage Cache Memory Cell. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Lin Yuan, Gang Qu 0001 |
ALT-DVS: Dynamic Voltage Scaling with Awareness of Leakage and Temperature for Real-Time Systems. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif |
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark |
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jie Gu 0003, Sachin S. Sapatnekar, Chris H. Kim |
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Sagar S. Sabade, D. M. H. Walker |
Estimation of fault-free leakage current using wafer-level spatial information. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001 |
Modeling and Analysis of Leakage Currents in Double-Gate Technologies. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Hui Xiong 0001, Michael S. Steinbach, Vipin Kumar 0001 |
Privacy leakage in multi-relational databases: a semi-supervised learning perspective. |
VLDB J. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Houman Homayoun, Amirali Baniasadi |
Reducing Execution Unit Leakage Power in Embedded Processors. |
SAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim |
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Pepijn J. de Langen, Ben H. H. Juurlink |
Leakage-aware multiprocessor scheduling for low power. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Lian Li 0002, Jingling Xue |
Trace-Based Data Cache Leakage Reduction at Link Time. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy 0001 |
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
Leakage energy reduction techniques in deep submicron cache memories: a comparative study. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | G. Razavipour, A. Motamedi, Ali Afzali-Kusha |
WL-VC SRAM: a low leakage memory circuit for deep sub-micron design. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Behnam Amelifard, Massoud Pedram, Farzan Fallah |
Low-leakage SRAM Design with Dual V_t Transistors. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Saraju P. Mohanty, Elias Kougianos |
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Chuen M. Tan, Masud H. Chowdhury |
Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Po-Kuan Huang, Soheil Ghiasi |
Leakage-aware intraprogram voltage scaling for embedded processors. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava 0001 |
Simultaneous Vt selection and assignment for leakage optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Man Lung Mui, Kaustav Banerjee, Amit Mehrotra |
Supply and power optimization in leakage-dominant technologies. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Hanane Fathi, SeongHan Shin, Kazukuni Kobara, Shyam S. Chakraborty, Hideki Imai, Ramjee Prasad |
Leakage-resilient security architecture for mobile IPv6 in wireless overlay networks. |
IEEE J. Sel. Areas Commun. |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das |
Hierarchical LUT structures for leakage power reduction (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin |
Leakage-Aware Interconnect for On-Chip Network. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge |
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan |
Leakage control in FPGA routing fabric. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Zhangliang Xiong, Xiangquan Shi |
Adaptive Leakage Suppression Based on Recurrent Wavelet Neural Network. |
ICNC (2) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De |
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yongzhi Liu, Qiyue Zou, Zhiping Lin 0001 |
Generalized sidelobe cancellers with leakage constraints. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy 0001 |
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Frank Sill, Frank Grassert, Dirk Timmermann |
Reducing Leakage with Mixed-V_th (MVT). |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yu-Shiang Lin, Dennis Sylvester |
A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
A novel synthesis approach for active leakage power reduction using dynamic supply gating. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Carlo Dallavalle |
Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Yingmin Li, Dharmesh Parikh, Yan Zhang 0028, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron |
State-Preserving vs. Non-State-Preserving Leakage Control in Caches. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, Ibrahim Kolcu |
Banked scratch-pad memory management for reducing leakage energy consumption. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Vishal Khandelwal, Ankur Srivastava 0001 |
Leakage control through fine-grained placement and sizing of sleep transistors. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Michael Liu, Wei-Shen Wang, Michael Orshansky |
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
variability, yield, power minimization |
27 | Saumil Shah, Kanak Agarwal, Dennis Sylvester |
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Feng Gao 0017, John P. Hayes |
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
27 | M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan |
Designing Leakage Aware Multipliers. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Modeling and Estimation of Leakage in Sub-90nm Devices. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Jader A. De Lima |
An active leakage-injection scheme applied to low-voltage SRAMs. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Dongwoo Lee, David T. Blaauw |
Static leakage reduction through simultaneous threshold voltage and state assignment. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Lin Li 0002, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam |
Leakage Energy Management in Cache Hierarchies. |
IEEE PACT |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Chris H. Kim, Kaushik Roy 0001 |
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Weiping Liao, Joseph M. Basile, Lei He 0001 |
Leakage power modeling and reduction with data retention. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi |
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
27 | David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin |
Evaluating Run-Time Techniques for Leakage Power Reduction. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David T. Blaauw, Trevor N. Mudge |
Drowsy Caches: Simple Techniques for Reducing Leakage Power. |
ISCA |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi |
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins |
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|