Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Wolfgang Ecker, Johannes Schreiner |
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yi Zhao 0001, S. Saqib Khursheed, Bashir M. Al-Hashimi, Zhiwen Zhao |
Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | |
2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![IEEE, 978-1-5090-3561-8 The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
1 | Sukarn Agarwal, Hemangee K. Kapoor |
Restricting writes for energy-efficient hybrid cache in multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Niklas Krafczyk, Heinz Riener, Görschwin Fey |
WCET overapproximation for software in the context of a Cyber-Physical System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello |
Speeding up safety verification by fault abstraction and simulation to transaction level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto |
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione |
Conclusively verifying clock-domain crossings in very large hardware designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu |
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-7, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mini Jayakrishnan, Alan Chang, Tae-Hyoung Kim |
Power and area efficient clock stretching and critical path reshaping for error resilience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Lei Wu, Ching-Chuen Jong |
A VLSI architecture for real-time gradient guided image filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi |
Optimistic clock adjustment for preventing Better-than-worst-case violations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio |
XbarGen: A memristor based boolean logic synthesis tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Peer Adelt, Bastian Koppelmann, Wolfgang Müller 0003, Markus Becker 0001, Bernd Kleinjohann, Christoph Scheytt |
Fast dynamic fault injection for virtual microcontroller platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker |
Automatically comparing analog behavior using Earth Mover's Distance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-8, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Boyang Du, Luca Sterpone |
An FPGA-based testing platform for the validation of automotive powertrain ECU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-7, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Shounak Chakraborty 0001, Hemangee K. Kapoor |
Static energy reduction by performance linked dynamic cache resizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Seyed Saber Nabavi Larimi, Mehdi Kamal, Ali Afzali-Kusha, Hamid Mahmoodi |
Power and energy reduction of racetrack-based caches by exploiting shared shift operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Debjyoti Bhattacharjee, Farhad Merchant, Anupam Chattopadhyay |
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Van-Phuc Hoang, Thi-Thanh-Dung Phan, Van-Lan Dao, Cong-Kha Pham |
A compact, ultra-low power AES-CCM IP core for wireless body area networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi |
A novel soft error tolerant FPGA architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier |
A Hybrid Power Estimation Technique to improve IP power models quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Elad Amrani, Avishay Drori, Shahar Kvatinsky |
Logic design with unipolar memristors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-5, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Luca Piccolboni, Graziano Pravadelli |
Stimuli generation through invariant mining for black-box verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mengying Zhao, Keni Qiu, Yuan Xie 0001, Jingtong Hu, Chun Jason Xue |
Redesigning software and systems for non-volatile processors on self-powered devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Abhiram Reddy Gundla, Tom Chen 0001 |
An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-5, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Anna Bernasconi 0001, Valentina Ciriani, Luca Frontini, Gabriella Trucco |
Synthesis on switching lattices of Dimension-reducible Boolean functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Erol Koser, Sebastian Krosche, Walter Stechele |
Integrated Soft Error Resilience and Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yanzhe Li, Kai Huang 0002, Luc Claesen |
SoC oriented real-time high-quality stereo vision system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Maede Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Minghao Lin, Heming Sun, Shinji Kimura |
Power-efficient and slew-aware three dimensional gated clock tree synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Moritoshi Yasunaga, Naoki Yokoshima, Ikuo Yoshihara |
A passive equalizer and its design methodology for global interconnects in VLSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yuan He 0002, Masaaki Kondo |
Opportunistic circuit-switching for energy efficient on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini |
Faster-than-at-speed execution of functional programs: An experimental analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Syed Mohsin Abbas, Chi-Ying Tsui |
Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-5, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jotham Vaddaboina Manoranjan, Solomon Surya Tej Mano Sajjan, Vivek B. Gujari, Kenneth S. Stevens |
Design of a multi-style and multi-frequency FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mahshid Nasserian, Ali Peiravi, Farshad Moradi |
A 1.62 µW 8-channel ultra-high input impedance EEG amplifier for dry and non-contact biopotential recording applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Tohidi, Jens Kargaard Madsen, Martijn J. R. Heck, Farshad Moradi |
A low-power analog front-end neural acquisition design for seizure detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yukai Chen, Enrico Macii, Massimo Poncino |
Frequency domain characterization of batteries for the design of energy storage subsystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Xueqing Li, Kaisheng Ma, Sumitha George, John Sampson, Vijaykrishnan Narayanan |
Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya |
Power-aware test optimization for core-based 3D-SOCs under TSV-constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann |
Efficient handling of the fault space in functional safety analysis utilizing formal methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-7, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Asim Khan, Muhammad Umar Karim Khan, Muhammad Bilal 0001, Chong-Min Kyung |
Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 142-148, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Qiong Wei Low, Liter Siek, Mi Zhou |
A high efficiency rectifier for inductively power transfer application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 270-273, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jaehyun Park 0005, Donghwa Shin, Hyung Gyu Lee |
Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 104-109, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Seongbo Shim, Youngsoo Shin |
Physical design and mask optimization for directed self-assembly lithography (DSAL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 80-85, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Kerem Seyid, Sebastien Blanc, Yusuf Leblebici |
Hardware implementation of real-time multiple frame super-resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 219-224, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee |
A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 241-245, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Matthew M. Kim, Karl M. Fant, Paul Beckett |
Design of asynchronous RISC CPU register-file Write-Back queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 31-36, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Bartosz Boguslawski, Hossam Sarhan, Frédéric Heitzmann, Fabrice Seguin, Sébastien Thuries, Olivier Billoint, Fabien Clermidy |
Compact interconnect approach for networks of neural cliques using 3D technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 116-121, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Seongmo Park, Kyungjin Byun, Nak-Woong Eum |
A hybrid embedded compression codec engine for ultra HD video application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 292-296, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis |
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 1-6, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jia Wei Tang, Yuan Wen Hau, Muhammad N. Marsono |
Hardware/software partitioning of embedded System-on-Chip applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 331-336, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Danese, Francesca Filini, Graziano Pravadelli |
A time-window based approach for dynamic assertions mining on control signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 246-251, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sudipta Paul 0001, Pritha Banerjee 0001, Susmita Sur-Kolay |
Flare reduction in EUV Lithography by perturbation of wire segments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 7-12, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Artur Quiring, Markus Olbrich, Erich Barke |
Fast global interconnnect driven 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 313-318, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | |
2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![IEEE, 978-1-4673-9140-5 The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
1 | Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta |
Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 25-30, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ying-Jung Chen, Shanq-Jang Ruan |
A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 349-354, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jae-Jin Lee, Chan Kim, Kyungjin Byun, Nak-Woong Eum |
Virtual prototype based on Aldebarn CPU core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 303-306, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra 0001 |
Trace Buffer Attack: Security versus observability study in post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 355-360, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay |
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 337-342, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Manikantan Srinivasan, C. Siva Ram Murthy, Anusuya Balasubramanian |
Modular performance analysis of Multicore SoC-based small cell LTE base station. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 37-42, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chun-Jen Tsai, Tsung-Han Wu, Hung-Cheng Su |
JAIP-MP: A four-core Java application processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 189-194, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Lilian Bossuet, Viktor Fischer, Pierre Bayon |
Contactless transmission of intellectual property data to protect FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 19-24, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Pierre Nicolas-Nicolaz, Kiyoung Choi |
Dynamic error tracking and supply voltage adjustment for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 74-79, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Naehyuck Chang, Kiyoung Choi |
Message from the general chairs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. VIII, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Amir Masoud Gharehbaghi, Masahiro Fujita |
Efficient signature-based sub-circuit matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 280-285, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu |
Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cycles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 92-97, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hyunsun Park, Junwhan Ahn, Eunhyeok Park, Sungjoo Yoo |
Locality-aware vertex scheduling for GPU-based graph computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 195-200, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Surajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman 0001 |
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 122-127, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Andres F. Gomez, Víctor H. Champac |
A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 297-302, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Dominik Macko, Katarína Jelemenská, Pavel Cicák |
Power-management high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 63-68, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet |
A generic clock controller for low power systems: Experimentation on an AXI bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 307-312, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita |
Trace signal selection methods for post silicon debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 258-263, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury |
A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 231-236, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chengmo Yang, Maria Ruiz Varela |
Qualifying non-volatile register files for embedded systems through compiler-directed write minimization and balancing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 86-91, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shahzad Muzaffar, Ibrahim M. Elfadel |
Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 225-230, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang 0001, Hai Li 0001 |
An overview on memristor crossabr based neuromorphic circuit and architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 52-56, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim |
Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 159-164, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik |
Scalable algorithm for structural fault collapsing in digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 171-176, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler |
Reversible circuit rewriting with simulated annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 286-291, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, Harry H. Chen |
Cost reduction of system-level tests with stressed structural tests and SVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 177-182, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii, Enrico Macii, Massimo Poncino |
An equation-based battery cycle life model for various battery chemistries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 57-62, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jae-sun Seo, Mingoo Seok |
Digital CMOS neuromorphic processor design featuring unsupervised online learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 49-51, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Manish Kumar Jaiswal, Hayden Kwok-Hay So |
Dual-mode double precision / two-parallel single precision floating point multiplier architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 213-218, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Manikandan Pandiyan, Geetha Mani, Jovitha Jerome, Natarajan S. |
Integrating wearable low power CMOS ECG acquisition SoC with decision making system for WSBN applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 154-158, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Motoki Amagasaki, Yuto Takeuchi, Qian Zhao 0001, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
Architecture exploration of 3D FPGA to minimize internal layer connection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 110-115, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Tara Ghasempouri, Graziano Pravadelli |
On the estimation of assertion interestingness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 325-330, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Manikandan Pandiyan, Geetha Mani |
Embedded low power analog CMOS Fuzzy Logic Controller chip for industrial applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 43-48, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jun Guo, Peng Liu 0016, Weidong Wang |
Physical-based modeling and fast simulation of wireline links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 252-257, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu |
Timing attack on NEMS relay based design of AES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 264-269, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Gain Kim, Raffaele Capoccia, Yusuf Leblebici |
Design optimization of polyphase digital down converters for extremely high frequency wireless communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 207-212, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ananthanarayanan Parthasarathy |
Design and analysis of search algorithms for lower power consumption and faster convergence of DAC input of SAR-ADC in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 274-279, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez |
Circuit performance optimization for local intra-die process variations using a gate selection metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 165-170, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jaemin Lee, Seungwon Kim, Youngmin Kim, Seokhyeong Kang |
An optimal operating point by using error monitoring circuits with an error-resilient technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 69-73, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xabier Iturbe, Didier Keymeulen, Emre Ozer 0001, Patrick Yiu, Daniel Berisford, Kevin P. Hand, Robert Carlson |
An integrated SoC for science data processing in next-generation space flight instruments avionics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 134-141, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | John Jose, Joe Augustine, Sijin Sebastian |
Dynamic migratory selection strategy for adaptive routing in mesh NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 343-348, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jaehyun Park 0005, Donghwa Shin, Hyung Gyu Lee |
Prefetch-based dynamic row buffer management for LPDDR2-NVM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 98-103, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|