Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino	Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Wolfgang Ecker, Johannes Schreiner	Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Yi Zhao 0001, S. Saqib Khursheed, Bashir M. Al-Hashimi, Zhiwen Zhao	Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1		2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016	VLSI-SoC	2016	DBLP BibTeX RDF
1	Sukarn Agarwal, Hemangee K. Kapoor	Restricting writes for energy-efficient hybrid cache in multi-core architectures.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Niklas Krafczyk, Heinz Riener, Görschwin Fey	WCET overapproximation for software in the context of a Cyber-Physical System.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello	Speeding up safety verification by fault abstraction and simulation to transaction level.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto	Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione	Conclusively verifying clock-domain crossings in very large hardware designs.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu	An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Mini Jayakrishnan, Alan Chang, Tae-Hyoung Kim	Power and area efficient clock stretching and critical path reshaping for error resilience.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Lei Wu, Ching-Chuen Jong	A VLSI architecture for real-time gradient guided image filtering.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi	Optimistic clock adjustment for preventing Better-than-worst-case violations.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio	XbarGen: A memristor based boolean logic synthesis tool.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Peer Adelt, Bastian Koppelmann, Wolfgang Müller 0003, Markus Becker 0001, Bernd Kleinjohann, Christoph Scheytt	Fast dynamic fault injection for virtual microcontroller platforms.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker	Automatically comparing analog behavior using Earth Mover's Distance.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Boyang Du, Luca Sterpone	An FPGA-based testing platform for the validation of automotive powertrain ECU.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Shounak Chakraborty 0001, Hemangee K. Kapoor	Static energy reduction by performance linked dynamic cache resizing.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Seyed Saber Nabavi Larimi, Mehdi Kamal, Ali Afzali-Kusha, Hamid Mahmoodi	Power and energy reduction of racetrack-based caches by exploiting shared shift operations.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Debjyoti Bhattacharjee, Farhad Merchant, Anupam Chattopadhyay	Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Van-Phuc Hoang, Thi-Thanh-Dung Phan, Van-Lan Dao, Cong-Kha Pham	A compact, ultra-low power AES-CCM IP core for wireless body area networks.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi	A novel soft error tolerant FPGA architecture.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier	A Hybrid Power Estimation Technique to improve IP power models quality.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Elad Amrani, Avishay Drori, Shahar Kvatinsky	Logic design with unipolar memristors.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Luca Piccolboni, Graziano Pravadelli	Stimuli generation through invariant mining for black-box verification.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Mengying Zhao, Keni Qiu, Yuan Xie 0001, Jingtong Hu, Chun Jason Xue	Redesigning software and systems for non-volatile processors on self-powered devices.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Abhiram Reddy Gundla, Tom Chen 0001	An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani, Luca Frontini, Gabriella Trucco	Synthesis on switching lattices of Dimension-reducible Boolean functions.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Erol Koser, Sebastian Krosche, Walter Stechele	Integrated Soft Error Resilience and Self-Test.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Yanzhe Li, Kai Huang 0002, Luc Claesen	SoC oriented real-time high-quality stereo vision system.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Maede Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Minghao Lin, Heming Sun, Shinji Kimura	Power-efficient and slew-aware three dimensional gated clock tree synthesis.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Moritoshi Yasunaga, Naoki Yokoshima, Ikuo Yoshihara	A passive equalizer and its design methodology for global interconnects in VLSIs.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Yuan He 0002, Masaaki Kondo	Opportunistic circuit-switching for energy efficient on-chip networks.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini	Faster-than-at-speed execution of functional programs: An experimental analysis.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Syed Mohsin Abbas, Chi-Ying Tsui	Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Jotham Vaddaboina Manoranjan, Solomon Surya Tej Mano Sajjan, Vivek B. Gujari, Kenneth S. Stevens	Design of a multi-style and multi-frequency FPGA.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Mahshid Nasserian, Ali Peiravi, Farshad Moradi	A 1.62 µW 8-channel ultra-high input impedance EEG amplifier for dry and non-contact biopotential recording applications.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Mohammad Tohidi, Jens Kargaard Madsen, Martijn J. R. Heck, Farshad Moradi	A low-power analog front-end neural acquisition design for seizure detection.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Yukai Chen, Enrico Macii, Massimo Poncino	Frequency domain characterization of batteries for the design of energy storage subsystems.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Xueqing Li, Kaisheng Ma, Sumitha George, John Sampson, Vijaykrishnan Narayanan	Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya	Power-aware test optimization for core-based 3D-SOCs under TSV-constraints.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann	Efficient handling of the fault space in functional safety analysis utilizing formal methods.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Asim Khan, Muhammad Umar Karim Khan, Muhammad Bilal 0001, Chong-Min Kyung	Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Qiong Wei Low, Liter Siek, Mi Zhou	A high efficiency rectifier for inductively power transfer application.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jaehyun Park 0005, Donghwa Shin, Hyung Gyu Lee	Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Seongbo Shim, Youngsoo Shin	Physical design and mask optimization for directed self-assembly lithography (DSAL).	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Kerem Seyid, Sebastien Blanc, Yusuf Leblebici	Hardware implementation of real-time multiple frame super-resolution.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee	A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Matthew M. Kim, Karl M. Fant, Paul Beckett	Design of asynchronous RISC CPU register-file Write-Back queue.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Bartosz Boguslawski, Hossam Sarhan, Frédéric Heitzmann, Fabrice Seguin, Sébastien Thuries, Olivier Billoint, Fabien Clermidy	Compact interconnect approach for networks of neural cliques using 3D technology.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Seongmo Park, Kyungjin Byun, Nak-Woong Eum	A hybrid embedded compression codec engine for ultra HD video application.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis	An Incremental Timing-Driven flow using quadratic formulation for detailed placement.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jia Wei Tang, Yuan Wen Hau, Muhammad N. Marsono	Hardware/software partitioning of embedded System-on-Chip applications.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Alessandro Danese, Francesca Filini, Graziano Pravadelli	A time-window based approach for dynamic assertions mining on control signals.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Sudipta Paul 0001, Pritha Banerjee 0001, Susmita Sur-Kolay	Flare reduction in EUV Lithography by perturbation of wire segments.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Artur Quiring, Markus Olbrich, Erich Barke	Fast global interconnnect driven 3D floorplanning.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1		2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015	VLSI-SoC	2015	DBLP BibTeX RDF
1	Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta	Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Ying-Jung Chen, Shanq-Jang Ruan	A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVs.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jae-Jin Lee, Chan Kim, Kyungjin Byun, Nak-Woong Eum	Virtual prototype based on Aldebarn CPU core.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Yuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra 0001	Trace Buffer Attack: Security versus observability study in post-silicon debug.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Zoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay	Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Manikantan Srinivasan, C. Siva Ram Murthy, Anusuya Balasubramanian	Modular performance analysis of Multicore SoC-based small cell LTE base station.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Chun-Jen Tsai, Tsung-Han Wu, Hung-Cheng Su	JAIP-MP: A four-core Java application processor.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Lilian Bossuet, Viktor Fischer, Pierre Bayon	Contactless transmission of intellectual property data to protect FPGA designs.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Pierre Nicolas-Nicolaz, Kiyoung Choi	Dynamic error tracking and supply voltage adjustment for low power.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Naehyuck Chang, Kiyoung Choi	Message from the general chairs.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Masahiro Fujita	Efficient signature-based sub-circuit matching.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Yuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu	Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cycles.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Hyunsun Park, Junwhan Ahn, Eunhyeok Park, Sungjoo Yoo	Locality-aware vertex scheduling for GPU-based graph computation.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Surajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman 0001	A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Andres F. Gomez, Víctor H. Champac	A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Dominik Macko, Katarína Jelemenská, Pavel Cicák	Power-management high-level synthesis.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet	A generic clock controller for low power systems: Experimentation on an AXI bus.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita	Trace signal selection methods for post silicon debugging.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury	A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Chengmo Yang, Maria Ruiz Varela	Qualifying non-volatile register files for embedded systems through compiler-directed write minimization and balancing.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Shahzad Muzaffar, Ibrahim M. Elfadel	Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communications.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang 0001, Hai Li 0001	An overview on memristor crossabr based neuromorphic circuit and architecture.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim	Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik	Scalable algorithm for structural fault collapsing in digital circuits.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler	Reversible circuit rewriting with simulated annealing.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, Harry H. Chen	Cost reduction of system-level tests with stressed structural tests and SVM.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii, Enrico Macii, Massimo Poncino	An equation-based battery cycle life model for various battery chemistries.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jae-sun Seo, Mingoo Seok	Digital CMOS neuromorphic processor design featuring unsupervised online learning.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Manish Kumar Jaiswal, Hayden Kwok-Hay So	Dual-mode double precision / two-parallel single precision floating point multiplier architecture.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Manikandan Pandiyan, Geetha Mani, Jovitha Jerome, Natarajan S.	Integrating wearable low power CMOS ECG acquisition SoC with decision making system for WSBN applications.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Motoki Amagasaki, Yuto Takeuchi, Qian Zhao 0001, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	Architecture exploration of 3D FPGA to minimize internal layer connection.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Tara Ghasempouri, Graziano Pravadelli	On the estimation of assertion interestingness.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Manikandan Pandiyan, Geetha Mani	Embedded low power analog CMOS Fuzzy Logic Controller chip for industrial applications.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jun Guo, Peng Liu 0016, Weidong Wang	Physical-based modeling and fast simulation of wireline links.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu	Timing attack on NEMS relay based design of AES.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Gain Kim, Raffaele Capoccia, Yusuf Leblebici	Design optimization of polyphase digital down converters for extremely high frequency wireless communications.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Ananthanarayanan Parthasarathy	Design and analysis of search algorithms for lower power consumption and faster convergence of DAC input of SAR-ADC in 65nm CMOS.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez	Circuit performance optimization for local intra-die process variations using a gate selection metric.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jaemin Lee, Seungwon Kim, Youngmin Kim, Seokhyeong Kang	An optimal operating point by using error monitoring circuits with an error-resilient technique.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Xabier Iturbe, Didier Keymeulen, Emre Ozer 0001, Patrick Yiu, Daniel Berisford, Kevin P. Hand, Robert Carlson	An integrated SoC for science data processing in next-generation space flight instruments avionics.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	John Jose, Joe Augustine, Sijin Sebastian	Dynamic migratory selection strategy for adaptive routing in mesh NoCs.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Jaehyun Park 0005, Donghwa Shin, Hyung Gyu Lee	Prefetch-based dynamic row buffer management for LPDDR2-NVM devices.	VLSI-SoC	2015	DBLP DOI BibTeX RDF

Publications at "VLSI-SoC"( http://dblp.L3S.de/Venues/VLSI-SoC )