Search results for "flip-flops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Lin-rong Xiao, Xie-xiong Chen, Shi-yan Ying	Design of dual-edge triggered flip-flops based on quantum-dot cellular automata.	J. Zhejiang Univ. Sci. C	2012	DBLP DOI BibTeX RDF
30	Faiz-ul Hassan, Wim Vanderbauwhede, Fernando Rodríguez Salazar	Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
30	Elio Consoli, Gaetano Palumbo, Melita Pennisi	Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
30	Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie	Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
30	Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida	A Selective Replacement Method for Timing-Error-Predicting flip-Flops.	J. Circuits Syst. Comput.	2012	DBLP DOI BibTeX RDF
30	Xiayu Li, Song Jia, Limin Liu, Yuan Wang 0001, Ganggang Zhang	Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application.	Sci. China Inf. Sci.	2012	DBLP DOI BibTeX RDF
30	Geoffrey L. Herman, Craig B. Zilles, Michael C. Loui	Flip-Flops in Students' Conceptions of State.	IEEE Trans. Educ.	2012	DBLP DOI BibTeX RDF
30	Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello	Comparative analysis of yield optimized pulsed flip-flops.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
30	Abdoul Rjoub, Muna M. Al-Durrah	The performance and behaviour of dual edge triggered flip-flops in nanotechnology.	Int. J. Comput. Aided Eng. Technol.	2012	DBLP DOI BibTeX RDF
30	Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu	A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
30	David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong	Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
30	Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin	Crosstalk-aware power optimization with multi-bit flip-flops.	ASP-DAC	2012	DBLP DOI BibTeX RDF
30	Yoshihiro Ohkawa, Yukiya Miura	Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
30	Zhi-Wei Chen, Jin-Tai Yan	Utilization of multi-bit flip-flops for clock power reduction.	ICECS	2012	DBLP DOI BibTeX RDF
30	Yiqun Wang, Yongpan Liu, Shuangchen Li, Daming Zhang, Bo Zhao 0003, Mei-Fang Chiang, Yanxin Yan, Baiko Sai, Huazhong Yang	A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops.	ESSCIRC	2012	DBLP DOI BibTeX RDF
30	Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller, Hraziia, Costin Anghel, Amara Amara	Bipolar ReRAM Based non-volatile flip-flops for low-power architectures.	NEWCAS	2012	DBLP DOI BibTeX RDF
30	Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger	Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules.	CICC	2012	DBLP DOI BibTeX RDF
30	Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao	A novel low gate-count serializer topology with Multiplexer-Flip-Flops.	ISCAS	2012	DBLP DOI BibTeX RDF
30	Tamer Ragheb, Andrew Marshall	Calibration of propagation delay of flip-flops.	SoCC	2012	DBLP DOI BibTeX RDF
30	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
30	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
30	Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo	Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
30	Changnoh Yoon, Youngmin Cho, Jinsang Kim	DFV-Aware Flip-Flops Using C-Elements.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
30	Weiqiang Zhang, Li Su, Yu Zhang, Linfeng Li, Jianping Hu	Low-Leakage Flip-Flops Based on Dual-Threshold and Multiple Leakage Reduction Techniques.	J. Circuits Syst. Comput.	2011	DBLP DOI BibTeX RDF
30	Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang	Post-Placement Power Optimization With Multi-Bit Flip-Flops.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
30	Dangui Yan, Ruijun Tong, Chengchang Zhang, Changyong Li	A Modified Technique for Analysis of Synchronous Counters Constructed with Flip-flops.	J. Comput.	2011	DBLP DOI BibTeX RDF
30	Takumi Okuhira, Tohru Ishihara	Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits.	PATMOS	2011	DBLP DOI BibTeX RDF
30	Renato P. Ribas, André Inácio Reis, André Ivanov	Performance and functional test of flip-flops using ring oscillator structure.	IDT	2011	DBLP DOI BibTeX RDF
30	Yukiya Miura	Dual Edge Triggered Flip-Flops for Noise Aware Design.	ETS	2011	DBLP DOI BibTeX RDF	data signal, dependable design, edge triggered flip-flop, noise, synchronous circuits
30	Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov	Ring oscillators for functional and delay test of latches and flip-flops.	SBCCI	2011	DBLP DOI BibTeX RDF
30	David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong	Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
30	David Li, Pierce Chuang, David Nairn, Manoj Sachdev	Design and analysis of metastable-hardened flip-flops in sub-threshold region.	ISLPED	2011	DBLP BibTeX RDF
30	Vikram G. Rao, Hamid Mahmoodi	Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology.	ICCD	2011	DBLP DOI BibTeX RDF
30	Sagi Fisher, Raz Dagan, Sagi Blonder, Alexander Fish	An improved model for delay/energy estimation in near-threshold flip-flops.	ISCAS	2011	DBLP DOI BibTeX RDF
30	Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov	Self-checking test circuits for latches and flip-flops.	IOLTS	2011	DBLP DOI BibTeX RDF
30	A. Perumal, T. K. Bhattacharyya	Design of 1 V CMOS VCO followed by proposed source degeneration based CML flip-flops for 2.4 GHz short range wireless applications.	ICWET	2011	DBLP DOI BibTeX RDF
30	David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev	Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.	ISQED	2011	DBLP DOI BibTeX RDF
30	Ajay N. Bhoj, Niraj K. Jha	Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology.	ISQED	2011	DBLP DOI BibTeX RDF
30	Teruki Nakasato, Toru Nakura, Kunihiro Asada	Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy.	ISOCC	2011	DBLP DOI BibTeX RDF
30	Chun Zhao, W. Zhang, C. Z. Zhao, Ka Lok Man, Taikyeong T. Jeong, J. K. Seon, Y. Lee	Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process.	ISOCC	2011	DBLP DOI BibTeX RDF
30	Nader Alawadhi, Ozgur Sinanoglu	Revival of partial scan: Test cube analysis driven conversion of flip-flops.	VTS	2011	DBLP DOI BibTeX RDF
30	Omid Sarbishei, Mohammad Maymandi-Nejad	A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
30	Kazuteru Namba, Takashi Ikeda, Hideo Ito	Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
30	Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume	Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops.	IEICE Trans. Inf. Syst.	2010	DBLP DOI BibTeX RDF
30	Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara	Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
30	Massimo Alioto, Elio Consoli, Gaetano Palumbo	General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
30	Vincent van der Leest, Geert Jan Schrijen, Helena Handschuh, Pim Tuyls	Hardware intrinsic security from D flip-flops.	STC@CCS	2010	DBLP BibTeX RDF
30	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.	PATMOS	2010	DBLP DOI BibTeX RDF
30	Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello	Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis.	PATMOS	2010	DBLP DOI BibTeX RDF
30	Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello	Impact of Process Variations on Flip-Flops Energy and Timing Characteristics.	ISVLSI	2010	DBLP DOI BibTeX RDF
30	Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume	Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
30	Yngvar Berg	Novel high speed and ultra low voltage CMOS flip-flops.	ICECS	2010	DBLP DOI BibTeX RDF
30	Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen	Post-placement power optimization with multi-bit flip-flops.	ICCAD	2010	DBLP DOI BibTeX RDF
30	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.	ISCAS	2010	DBLP DOI BibTeX RDF
30	Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry	Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops.	ISCAS	2010	DBLP DOI BibTeX RDF
30	Hailong Jiao, Volkan Kursun	Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops.	ISCAS	2010	DBLP DOI BibTeX RDF
30	David Li, Pierce Chuang, Manoj Sachdev	Comparative analysis and study of metastability on high-performance flip-flops.	ISQED	2010	DBLP DOI BibTeX RDF
30	Eun Ju Hwang, Wook Kim, Young Hwan Kim	Improving the process variation tolerability of flip-flops for UDSM circuit design.	ISQED	2010	DBLP DOI BibTeX RDF
30	Yuji Kunitake, Toshinori Sato, Hiroto Yasuura	A Replacement Strategy for Canary Flip-Flops.	PRDC	2010	DBLP DOI BibTeX RDF
30	Chengtian Ouyang, Jianhui Jiang, Jie Xiao	Reliability Evaluation of Flip-Flops Based on Probabilistic Transfer Matrices.	PRDC	2010	DBLP DOI BibTeX RDF
30	Changnoh Yoon, Youngmin Cho, Jinsang Kim, Won-Kyung Cho	Efficient DFV-aware flip-flops.	APCCAS	2010	DBLP DOI BibTeX RDF
30	Rita Lovassy	Multilayer Perceptrons Based on Fuzzy Flip-Flops		2010	RDF
30	Lih-Yih Chiou, Shien-Chun Luo	Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
30	Yingbo Hu, Runde Zhou	Low Clock-Swing TSPC Flip-Flops for Low-Power Applications.	J. Circuits Syst. Comput.	2009	DBLP DOI BibTeX RDF
30	Jaehyun Kim, Chungki Oh, Youngsoo Shin	Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF
30	Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry	Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits.	ISVLSI	2009	DBLP DOI BibTeX RDF
30	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design.	ECCTD	2009	DBLP DOI BibTeX RDF
30	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Optimum clock slope for flip-flops within a clock domain: Analysis and a case study.	ICECS	2009	DBLP DOI BibTeX RDF
30	Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang	Level Converting Scan Flip-flops.	ISCAS	2009	DBLP DOI BibTeX RDF
30	Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba	Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.	DFT	2009	DBLP DOI BibTeX RDF
30	Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba	Test point insertion using functional flip-flops to drive control points.	ITC	2009	DBLP DOI BibTeX RDF
30	Kentaroh Katoh, Kazuteru Namba, Hideo Ito	Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.	IPSJ Trans. Syst. LSI Des. Methodol.	2008	DBLP DOI BibTeX RDF
30	Joo-Seong Kim, Bai-Sun Kong	Self-Resetting Level-Conversion Flip-Flops with Direct Output Feedback for Dual-Supply SoCs.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
30	Amir Moradi 0001, Thomas Eisenbarth 0001, Axel Poschmann, Carsten Rolfes, Christof Paar, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh	Information Leakage of Flip-Flops in DPA-Resistant Logic Styles.	IACR Cryptol. ePrint Arch.	2008	DBLP BibTeX RDF
30	Rita Lovassy, László T. Kóczy, László Gál	Multilayer Pereeptron implemented by fuzzy flip-flops.	FUZZ-IEEE	2008	DBLP DOI BibTeX RDF
30	Mohammad Ghasemazar, Behnam Amelifard, Massoud Pedram	A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops.	ISLPED	2008	DBLP DOI BibTeX RDF
30	Kaijian Shi	Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities.	ICCD	2008	DBLP DOI BibTeX RDF
30	Tino Heijmen	Soft-Error Vulnerability of Sub-100-nm Flip-Flops.	IOLTS	2008	DBLP DOI BibTeX RDF
30	Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty	A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Hong Li, Lifang Ye, Jinghong Fu, Jianping Hu	Single-phase power-gating adiabatic flip-flops.	APCCAS	2008	DBLP DOI BibTeX RDF
30	Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara	Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling.	DAC	2008	DBLP DOI BibTeX RDF	CTS, error-detection flip-flop, DVS, STA
30	Shunsuke Okura, Tetsuro Okura, Indika U. K. Bogoda Appuhamylage, Kenji Taniguchi 0001	A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
30	René Kothe, Heinrich Theodor Vierhaus	Flip-Flops and Scan-Path Elements for Nanoelectronics.	DDECS	2007	DBLP DOI BibTeX RDF
30	Zhiyu Liu, Volkan Kursun	New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability.	ICECS	2007	DBLP DOI BibTeX RDF
30	Toru Nakura, Koichi Nose, Masayuki Mizuno	Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops.	ISSCC	2007	DBLP DOI BibTeX RDF
30	Eric L. Hill, Mikko H. Lipasti	Transparent mode flip-flops for collapsible pipelines.	ICCD	2007	DBLP DOI BibTeX RDF
30	Amith Singhee, Rob A. Rutenbar	From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis.	ISQED	2007	DBLP DOI BibTeX RDF
30	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty	A TMR Scheme for SEU Mitigation in Scan Flip-Flops.	ISQED	2007	DBLP DOI BibTeX RDF
30	Hyoun Soo Park, Bong Hyun Lee, Young Hwan Kim	Level Converting Flip-Flops for High-Speed and Low-Power Applications.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
30	Józef Kalisz, Zbigniew Jachna	Metastability tests of flip-flops in programmable digital circuits.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
30	Ahmed Sayed, Hussain Al-Asaad	Survey and Evaluation of Low-Power Flip-Flops.	CDES	2006	DBLP BibTeX RDF
30	Martin Hansson, Atila Alvandpour	A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOS.	SoCC	2006	DBLP DOI BibTeX RDF
30	Fatemeh Aezinia, S. Najafzadeh, Ali Afzali-Kusha	Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops.	APCCAS	2006	DBLP DOI BibTeX RDF
30	Thomas E. Collins, Vikas Manan, Stephen I. Long	Design analysis and circuit enhancements for high-speed bipolar flip-flops.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
30	Bong Hyun Lee, Young Hwan Kim, Kwang-Ok Jeong	Clock-Free MTCMOS Flip-Flops with High Speed and Low Power.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
30	Shin-ichi Yoshida, Kaoru Hirota	Lattice Structure of D, T, and SR Fuzzy Flip-Flops Under Max-Min Logic.	J. Adv. Comput. Intell. Intell. Informatics	2005	DBLP DOI BibTeX RDF
30	A. P. Dhande, V. T. Ingole	Design of 3-Valued R-S & D Flip-Flops Based on Simple Ternary Gates.	Int. J. Softw. Eng. Knowl. Eng.	2005	DBLP DOI BibTeX RDF
30	Víctor H. Champac, Antonio Zenteno, José L. Garcia	Testing of resistive opens in CMOS latches and flip-flops.	ETS	2005	DBLP DOI BibTeX RDF
30	A. P. Dhande, V. T. Ingole	Design Of 3-Valued R-S & D Flip - Flops Based on Simple Ternary Gates.	WEC (2)	2005	DBLP BibTeX RDF
30	David Levacq, Vincent Dessard, Denis Flandre	Ultra-low power flip-flops for MTCMOS circuits.	ISCAS (5)	2005	DBLP DOI BibTeX RDF