Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita |
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 418-425, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Parthasarathi Dasgupta, Susmita Sur-Kolay |
Slicibility of rectangular graphs and floorplan optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997, pp. 150-155, 1997, ACM, 0-89791-927-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
graph dualization, nonslicible floorplans, slicible floorplans, very large scale integration, heuristic search, planar graphs, floorplanning |
18 | Isao Tazawa, Seiichi Koakutsu, Hironori Hirata |
An Immunity Based Genetic Algorithm and Its Application to the VLSI Floorplan Design Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Evolutionary Computation ![In: Proceedings of 1996 IEEE International Conference on Evolutionary Computation, Nayoya University, Japan, May 20-22, 1996, pp. 417-421, 1996, IEEE, 0-7803-2902-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Maurizio Rebaudengo, Matteo Sonza Reorda |
A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, International Conference and Exhibition, HPCN Europe 1996, Brussels, Belgium, April 15-19, 1996, Proceedings, pp. 987-988, 1996, Springer, 3-540-61142-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Danny Z. Chen, Xiaobo Hu 0001 |
Efficient Approximation Algorithms for Floorplan Area Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 483-486, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Kai Wang, Wai-Kai Chen |
Floorplan Area Optimization Using Network Analogous Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 167-170, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Matteo Sonza Reorda, Maurizio Rebaudengo |
A Genetic Algorithm for Floorplan Area Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Evolutionary Computation ![In: Proceedings of the First IEEE Conference on Evolutionary Computation, IEEE World Congress on Computational Intelligence, Orlando, Florida, USA, June 27-29, 1994, pp. 93-96, 1994, IEEE, 0-7803-1899-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Cheng-Hsi Chen, Ioannis G. Tollis |
A New Approach to Floorplan Area Optimization: To Slice or not to Slice? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 161-164, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Maurizio Rebaudengo, Matteo Sonza Reorda |
Floorplan area optimization using genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994, pp. 22-25, 1994, IEEE, 0-8186-5610-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Ting-Chi Wang, D. F. Wong 0001 |
Graph-based techniques to speed up floorplan area optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 15(2), pp. 179-199, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Michael Kolonko |
Optimal compactification of a floorplan and its relation to other optimization problems-a dynamic programming approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ZOR Methods Model. Oper. Res. ![In: ZOR Methods Model. Oper. Res. 37(1), pp. 75-95, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa |
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 321-335, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Ting-Chi Wang, D. F. Wong 0001 |
A note on the Complexity of Stockmeyer's floorplan Optimization Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 309-320, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Seiichi Koakutsu, Hironori Hirata |
Genetic simulated annealing for floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
System Modelling and Optimization ![In: System Modelling and Optimization: Proceedings of the 16th IFIP-TC7 Conference, Compiègne, France, July 5-9, 1993, pp. 268-277, 1993, Springer, 978-3-540-19893-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Majid Sarrafzadeh |
Transforming an arbitrary floorplan into a sliceable one. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, pp. 386-389, 1993, IEEE Computer Society / ACM, 0-8186-4490-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Sharat Prasad, Paul Kollaritsch, P. Anirudhan, D. K. Hwang, Steve Lusky, R. Farrow |
Efficient Floorplan Enumeration Using Dynamic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 1766-1769, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
18 | Kai Wang, Wai-Kai Chen |
A Class of Zero Wasted Area Floorplan for VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 1762-1765, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
18 | Mitsuho Seki, Shun'ichi Kobayashi, Munehiro Takubo, Kazuyoshi Kurosawa |
A New Floorplan Simultaneously Placing Blocks over Two Logic Layers for Sea-of-gate Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 1758-1761, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
18 | Zahava Koren, Israel Koren |
Does the Floorplan of a Chip Affect Its Yield? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings, pp. 159-166, 1993, IEEE Computer Society, 0-8186-3502-9. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
18 | Tsu-Chang Lee |
A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 525-530, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Ting-Chi Wang, D. F. Wong 0001 |
A Graph Theoretic Technique to Speed up Floorplan Area Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992., pp. 62-68, 1992, IEEE Computer Society Press, 0-8186-2822-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
18 | A. J. W. M. ten Berg |
Floorplan Optimized Topological Partitioning of Programmed Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Synthesis for Control Dominated Circuits ![In: Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992, pp. 399-411, 1992, North-Holland, 0-444-81479-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
18 | Youngtak Kim, Youngjo Jang, Myunghwan Kim 0001 |
Stepwise-overlapped parallel annealing and its application to floorplan designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Aided Des. ![In: Comput. Aided Des. 23(2), pp. 133-144, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
18 | Ting-Chi Wang, D. F. Wong 0001 |
Efficient shape curve construction in floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991, pp. 356-360, 1991, EEE Computer Society, 0-8186-2130-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
18 | Cheng-Hsi Chen, Ioannis G. Tollis |
An Optimal Algorithm for Spiral Floorplan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 516-519, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
18 | Masako Murofushi, Masaaki Yamada, Takashi Mitsuhashi |
FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 140-143, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
18 | Chidchanok Lursinsap, Daniel Gajski |
Power routing in channelless floorplan layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 8(3), pp. 249-268, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Thomas R. Mueller, D. F. Wong 0001, C. L. Liu 0001 |
An enhanced bottom-up algorithm for floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 7(2), pp. 189-201, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
18 | D. F. Wong 0001, C. L. Liu 0001 |
Floorplan Design of VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 4(2), pp. 263-291, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
18 | D. F. Wong 0001, Khe-Sing The |
An algorithm for hierarchical floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers, pp. 484-487, 1989, IEEE Computer Society, 0-8186-1986-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Sai-keung Dong, Jason Cong, C. L. Liu 0001 |
Constrained floorplan design for flexible blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers, pp. 488-491, 1989, IEEE Computer Society, 0-8186-1986-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Sunil Arvindam, Vipin Kumar 0001, V. Nageshwara Rao |
Floorplan optimization on multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989, pp. 109-114, 1989, IEEE, 0-8186-1971-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Y. C. Hsu, William J. Kubitz |
ALSO: A system for chip floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 6(2), pp. 127-146, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
18 | James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana Richards |
Floorplan design using distributed genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers, pp. 452-455, 1988, IEEE Computer Society, 0-8186-0869-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
18 | Philippe Chaisemartin |
Contribution à la génération automatique de plans de masse. (Contribution to automatic floorplan design). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1986 |
RDF |
|
18 | Larry J. Stockmeyer |
Optimal Orientations of Cells in Slicing Floorplan Designs ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Control. ![In: Inf. Control. 57(2/3), pp. 91-101, May/June 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
|
18 | Ralph H. J. M. Otten |
Automatic floorplan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982, pp. 261-267, 1982, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
11 | Jason Cong, Guojie Luo |
An analytical placer for mixed-size 3D placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 61-66, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
placement, 3D integration, analytical method |
11 | Lane Schwartz, Luan Nguyen, Andrew Exley, William Schuler |
Positive effects of redundant descriptions in an interactive semantic speech interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IUI ![In: Proceedings of the 14th International Conference on Intelligent User Interfaces, IUI 2009, Sanibel Island, Florida, USA, February 8-11, 2009, pp. 217-226, 2009, ACM, 978-1-60558-168-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interactive semantics, semantics, speech recognition, spoken language interfaces |
11 | Xin Li, Yuchun Ma, Xianlong Hong |
A novel thermal optimization flow using incremental floorplanning for 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 347-352, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang |
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 5-12, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multiple-supply voltage designs, physical design, floorplanning, vlsi |
11 | Domenik Helms, Kai Hylla, Wolfgang Nebel |
Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 33-38, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
electro-thermal coupling, system level estimation, reliability, thermal modelling, IR-drop |
11 | Jyh-Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han |
A Parallel Simulated Annealing Approach for Floorplanning in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP ![In: Algorithms and Architectures for Parallel Processing, 9th International Conference, ICA3PP 2009, Taipei, Taiwan, June 8-11, 2009. Proceedings, pp. 291-302, 2009, Springer, 978-3-642-03094-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FFA, Parallel Computing, Simulated Annealing, OpenMP, Floorplanning |
11 | Renshen Wang, Chung-Kuan Cheng |
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 257-262, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3-D integrated circuits, cuboidal dual, computational complexity |
11 | Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang |
Buffer/flip-flop block planning for power-integrity-driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 488-493, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Pritha Banerjee 0001, Megha Sangtani, Susmita Sur-Kolay |
Floorplanning for Partial Reconfiguration in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 125-130, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Vyas Krishnan, Srinivas Katkoori |
Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 419-424, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Jackey Z. Yan, Natarajan Viswanathan, Chris Chu |
Handling complexities in modern large-scale mixed-size placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 436-441, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
incremental placement, mixed-size design, floorplanning |
11 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(6), pp. 733-744, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Minsik Cho, David Z. Pan |
Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(12), pp. 1713-1717, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 286-294, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Song Chen 0001, Takeshi Yoshimura |
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 858-871, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Chaomin Luo, Miguel F. Anjos, Anthony Vannelli |
Large-scale fixed-outline floorplanning design using convex optimization techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 198-203, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Hasliza A. Rahim, Ab Al-Hadi Ab Rahman, R. Badlishah Ahmad, Wan Nur Suryani Firuz Wan Ariffin, Muhammad Imran Ahmad |
The Performance Study of Two Genetic Algorithm Approaches for VLSI Macro-Cell Layout Area Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Second Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, Malaysia, May 13-15, 2008, pp. 207-212, 2008, IEEE Computer Society, 978-0-7695-3136-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Steady-State Algorithm, Genetic Algorithm, VLSI, Area Optimization, Simple Genetic Algorithm |
11 | Santhosh Coimbatore Vaidyanathan, Amit Mangesh Brahme, Sukumar Jairam |
Techniques for Early Package Closure in System-in-Packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 608-613, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
spacer, landing, SoC, SIP, CSP, MCM, POP |
11 | Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser |
Utilizing shared data in chip multiprocessors with the nahalal architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June 14-16, 2008, pp. 1-10, 2008, ACM, 978-1-59593-973-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
chip multiprocessors, cache memories |
11 | Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser |
Nahalal: Cache Organization for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 6(1), pp. 21-24, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo |
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 869-880, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001 |
Microarchitecture Configurations and Floorplanning Co-Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 830-841, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Zhenyu (Peter) Gu, Jia Wang 0003, Robert P. Dick, Hai Zhou 0001 |
Unified Incremental Physical-Level and High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1576-1588, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng |
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4), pp. 645-658, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das |
Hierarchical partitioning of VLSI floorplans by staircases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 7:1-7:19, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
balanced bipartitioning, NP-completeness, Floorplanning, network flow, global routing |
11 | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
Temporal floorplanning using the three-dimensional transitive closure subGraph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 37, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration |
11 | David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida |
HW-SW emulation framework for temperature-aware design in MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 26:1-26:26, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Thermal-aware design, FPGA, emulation, MPSoC, temperature |
11 | Hushrav Mogal, Kia Bazargan |
Microarchitecture floorplanning for sub-threshold leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1238-1243, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Heyong Wang, Kang Hu, Jing Liu 0006, Licheng Jiao |
Multiagent evolutionary algorithm for floorplanning using moving block sequence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 4372-4377, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 184-190, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 274-279, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs |
11 | Love Singhal, Elaheh Bozorgzadeh |
Novel Multi-Layer floorplanning for Heterogeneous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 613-616, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail |
Modeling and Characterizing Power Variability in Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 146-157, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mal-fabricated chip, VariPower, project power variability, microarchitectural block, power variability characterization, statistical analysis, multicore processor, multicore architecture, technology scaling, parameter variation, SPICE simulation |
11 | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 650-655, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou 0001, Xianlong Hong, Qiang Zhou 0001 |
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 590-597, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Qiang Ma 0002, Evangeline F. Y. Young |
Voltage island-driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 644-649, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel |
Voltage- and ABB-island optimization in high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 153-158, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, process variation, leakage, voltage islands |
11 | Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou 0001, Xianlong Hong |
Power Delivery Aware Floorplanning for Voltage Island Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 350-355, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong |
OPC-Friendly Bus Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 847-852, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry |
A Low-Power Multi-Pin Maze Routing Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 153-158, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Harlan Hile, Gaetano Borriello |
Information Overlay for Camera Phones in Indoor Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LoCA ![In: Location- and Context-Awareness, Third International Symposium, LoCA 2007, Oberpfaffenhofen, Germany, September 20-21, 2007, Proceedings, pp. 68-84, 2007, Springer, 978-3-540-75159-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Sankar P. Debnath, Ganesh P. Kumar 0002, Sukumar Jairam |
Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 887-892, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
Linear-programming-based techniques for synthesis of network-on-chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(4), pp. 407-420, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Ruiming Chen, Hai Zhou 0001 |
An Efficient Data Structure for Maxplus Merge in Dynamic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 3004-3009, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong |
Minimizing wire length in floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1744-1753, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak |
Latency-Guided On-Chip Bus-Network Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2663-2673, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak |
A statistical methodology for wire-length prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7), pp. 1327-1336, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Tung-Chieh Chen, Yao-Wen Chang |
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4), pp. 637-650, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar |
A design methodology for application-specific networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 263-280, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
regular topology, architecture, methodology, networks-on-chip, Application-specific |
11 | Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin |
Floorplanning Based on Particle Swarm Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 7-11, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb |
Die Stacking (3D) Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 469-479, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Minsik Cho, Hongjoong Shin, David Z. Pan |
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 765-770, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang |
Simultaneous block and I/O buffer floorplanning for flip-chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 213-218, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Love Singhal, Elaheh Bozorgzadeh |
Physically-aware exploitation of component reuse in a partially reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Krishnan Srinivasan, Karam S. Chatha |
Layout aware design of mesh based NoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 136-141, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
network-on-chip, automated design, mesh topology |
11 | Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu |
Analog placement with symmetry and other placement constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 349-354, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
symmetry constraints, placement, analog circuits, sequence-pair |
11 | Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh |
A congestion-driven buffer planner with space reservation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani |
How does partitioning matter for 3D floorplanning? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 73-78, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
partitioning, floorplanning, 3D IC, wire length |
11 | Wei-Lun Hung, Greg M. Link, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin |
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 98-104, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Jia Wang 0003, Hai Zhou 0001, Ping-Chih Wu |
Processing Rate Optimization by Sequential System Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 340-345, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma |
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 792-795, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh |
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(1), pp. 75-85, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Jai-Ming Lin, Yao-Wen Chang |
TCG: A transitive closure graph-based representation for general floorplans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(2), pp. 288-292, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|