Search results for "floorplan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita	The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.	ICCAD	1998	DBLP DOI BibTeX RDF
18	Parthasarathi Dasgupta, Susmita Sur-Kolay	Slicibility of rectangular graphs and floorplan optimization.	ISPD	1997	DBLP DOI BibTeX RDF	graph dualization, nonslicible floorplans, slicible floorplans, very large scale integration, heuristic search, planar graphs, floorplanning
18	Isao Tazawa, Seiichi Koakutsu, Hironori Hirata	An Immunity Based Genetic Algorithm and Its Application to the VLSI Floorplan Design Problem.	International Conference on Evolutionary Computation	1996	DBLP DOI BibTeX RDF
18	Maurizio Rebaudengo, Matteo Sonza Reorda	A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture.	HPCN	1996	DBLP DOI BibTeX RDF
18	Danny Z. Chen, Xiaobo Hu 0001	Efficient Approximation Algorithms for Floorplan Area Minimization.	DAC	1996	DBLP DOI BibTeX RDF
18	Kai Wang, Wai-Kai Chen	Floorplan Area Optimization Using Network Analogous Approach.	ISCAS	1995	DBLP DOI BibTeX RDF
18	Matteo Sonza Reorda, Maurizio Rebaudengo	A Genetic Algorithm for Floorplan Area Optimization.	International Conference on Evolutionary Computation	1994	DBLP DOI BibTeX RDF
18	Cheng-Hsi Chen, Ioannis G. Tollis	A New Approach to Floorplan Area Optimization: To Slice or not to Slice?	ISCAS	1994	DBLP DOI BibTeX RDF
18	Maurizio Rebaudengo, Matteo Sonza Reorda	Floorplan area optimization using genetic algorithms.	Great Lakes Symposium on VLSI	1994	DBLP DOI BibTeX RDF
18	Ting-Chi Wang, D. F. Wong 0001	Graph-based techniques to speed up floorplan area optimization.	Integr.	1993	DBLP DOI BibTeX RDF
18	Michael Kolonko	Optimal compactification of a floorplan and its relation to other optimization problems-a dynamic programming approach.	ZOR Methods Model. Oper. Res.	1993	DBLP DOI BibTeX RDF
18	Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa	An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
18	Ting-Chi Wang, D. F. Wong 0001	A note on the Complexity of Stockmeyer's floorplan Optimization Technique.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
18	Seiichi Koakutsu, Hironori Hirata	Genetic simulated annealing for floorplan design.	System Modelling and Optimization	1993	DBLP DOI BibTeX RDF
18	Majid Sarrafzadeh	Transforming an arbitrary floorplan into a sliceable one.	ICCAD	1993	DBLP DOI BibTeX RDF
18	Sharat Prasad, Paul Kollaritsch, P. Anirudhan, D. K. Hwang, Steve Lusky, R. Farrow	Efficient Floorplan Enumeration Using Dynamic Programming.	ISCAS	1993	DBLP BibTeX RDF
18	Kai Wang, Wai-Kai Chen	A Class of Zero Wasted Area Floorplan for VLSI Design.	ISCAS	1993	DBLP BibTeX RDF
18	Mitsuho Seki, Shun'ichi Kobayashi, Munehiro Takubo, Kazuyoshi Kurosawa	A New Floorplan Simultaneously Placing Blocks over Two Logic Layers for Sea-of-gate Gate Arrays.	ISCAS	1993	DBLP BibTeX RDF
18	Zahava Koren, Israel Koren	Does the Floorplan of a Chip Affect Its Yield?	DFT	1993	DBLP BibTeX RDF
18	Tsu-Chang Lee	A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules.	DAC	1993	DBLP DOI BibTeX RDF
18	Ting-Chi Wang, D. F. Wong 0001	A Graph Theoretic Technique to Speed up Floorplan Area Optimization.	DAC	1992	DBLP BibTeX RDF
18	A. J. W. M. ten Berg	Floorplan Optimized Topological Partitioning of Programmed Logic Arrays.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
18	Youngtak Kim, Youngjo Jang, Myunghwan Kim 0001	Stepwise-overlapped parallel annealing and its application to floorplan designs.	Comput. Aided Des.	1991	DBLP DOI BibTeX RDF
18	Ting-Chi Wang, D. F. Wong 0001	Efficient shape curve construction in floorplan design.	EURO-DAC	1991	DBLP BibTeX RDF
18	Cheng-Hsi Chen, Ioannis G. Tollis	An Optimal Algorithm for Spiral Floorplan Designs.	ICCD	1991	DBLP DOI BibTeX RDF
18	Masako Murofushi, Masaaki Yamada, Takashi Mitsuhashi	FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays.	ICCAD	1990	DBLP DOI BibTeX RDF
18	Chidchanok Lursinsap, Daniel Gajski	Power routing in channelless floorplan layouts.	Integr.	1989	DBLP DOI BibTeX RDF
18	Thomas R. Mueller, D. F. Wong 0001, C. L. Liu 0001	An enhanced bottom-up algorithm for floorplan design.	Integr.	1989	DBLP DOI BibTeX RDF
18	D. F. Wong 0001, C. L. Liu 0001	Floorplan Design of VLSI Circuits.	Algorithmica	1989	DBLP DOI BibTeX RDF
18	D. F. Wong 0001, Khe-Sing The	An algorithm for hierarchical floorplan design.	ICCAD	1989	DBLP DOI BibTeX RDF
18	Sai-keung Dong, Jason Cong, C. L. Liu 0001	Constrained floorplan design for flexible blocks.	ICCAD	1989	DBLP DOI BibTeX RDF
18	Sunil Arvindam, Vipin Kumar 0001, V. Nageshwara Rao	Floorplan optimization on multiprocessors.	ICCD	1989	DBLP DOI BibTeX RDF
18	Y. C. Hsu, William J. Kubitz	ALSO: A system for chip floorplan design.	Integr.	1988	DBLP DOI BibTeX RDF
18	James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana Richards	Floorplan design using distributed genetic algorithms.	ICCAD	1988	DBLP DOI BibTeX RDF
18	Philippe Chaisemartin	Contribution à la génération automatique de plans de masse. (Contribution to automatic floorplan design).		1986	RDF
18	Larry J. Stockmeyer	Optimal Orientations of Cells in Slicing Floorplan Designs	Inf. Control.	1983	DBLP DOI BibTeX RDF
18	Ralph H. J. M. Otten	Automatic floorplan design.	DAC	1982	DBLP DOI BibTeX RDF
11	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
11	Lane Schwartz, Luan Nguyen, Andrew Exley, William Schuler	Positive effects of redundant descriptions in an interactive semantic speech interface.	IUI	2009	DBLP DOI BibTeX RDF	interactive semantics, semantics, speech recognition, spoken language interfaces
11	Xin Li, Yuchun Ma, Xianlong Hong	A novel thermal optimization flow using incremental floorplanning for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
11	Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs.	ISPD	2009	DBLP DOI BibTeX RDF	multiple-supply voltage designs, physical design, floorplanning, vlsi
11	Domenik Helms, Kai Hylla, Wolfgang Nebel	Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction.	ISLPED	2009	DBLP DOI BibTeX RDF	electro-thermal coupling, system level estimation, reliability, thermal modelling, IR-drop
11	Jyh-Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han	A Parallel Simulated Annealing Approach for Floorplanning in VLSI.	ICA3PP	2009	DBLP DOI BibTeX RDF	FFA, Parallel Computing, Simulated Annealing, OpenMP, Floorplanning
11	Renshen Wang, Chung-Kuan Cheng	On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	3-D integrated circuits, cuboidal dual, computational complexity
11	Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang	Buffer/flip-flop block planning for power-integrity-driven floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
11	Pritha Banerjee 0001, Megha Sangtani, Susmita Sur-Kolay	Floorplanning for Partial Reconfiguration in FPGAs.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Vyas Krishnan, Srinivas Katkoori	Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Jackey Z. Yan, Natarajan Viswanathan, Chris Chu	Handling complexities in modern large-scale mixed-size placement.	DAC	2009	DBLP DOI BibTeX RDF	incremental placement, mixed-size design, floorplanning
11	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Minsik Cho, David Z. Pan	Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin	A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Song Chen 0001, Takeshi Yoshimura	Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	Large-scale fixed-outline floorplanning design using convex optimization techniques.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Hasliza A. Rahim, Ab Al-Hadi Ab Rahman, R. Badlishah Ahmad, Wan Nur Suryani Firuz Wan Ariffin, Muhammad Imran Ahmad	The Performance Study of Two Genetic Algorithm Approaches for VLSI Macro-Cell Layout Area Optimization.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Steady-State Algorithm, Genetic Algorithm, VLSI, Area Optimization, Simple Genetic Algorithm
11	Santhosh Coimbatore Vaidyanathan, Amit Mangesh Brahme, Sukumar Jairam	Techniques for Early Package Closure in System-in-Packages.	ISQED	2008	DBLP DOI BibTeX RDF	spacer, landing, SoC, SIP, CSP, MCM, POP
11	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
11	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Nahalal: Cache Organization for Chip Multiprocessors.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF
11	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001	Microarchitecture Configurations and Floorplanning Co-Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Zhenyu (Peter) Gu, Jia Wang 0003, Robert P. Dick, Hai Zhou 0001	Unified Incremental Physical-Level and High-Level Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das	Hierarchical partitioning of VLSI floorplans by staircases.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	balanced bipartitioning, NP-completeness, Floorplanning, network flow, global routing
11	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Temporal floorplanning using the three-dimensional transitive closure subGraph.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
11	David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida	HW-SW emulation framework for temperature-aware design in MPSoCs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Thermal-aware design, FPGA, emulation, MPSoC, temperature
11	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
11	Heyong Wang, Kang Hu, Jing Liu 0006, Licheng Jiao	Multiagent evolutionary algorithm for floorplanning using moving block sequence.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
11	Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod	Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
11	Love Singhal, Elaheh Bozorgzadeh	Novel Multi-Layer floorplanning for Heterogeneous FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
11	Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail	Modeling and Characterizing Power Variability in Multicore Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	mal-fabricated chip, VariPower, project power variability, microarchitectural block, power variability characterization, statistical analysis, multicore processor, multicore architecture, technology scaling, parameter variation, SPICE simulation
11	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou 0001, Xianlong Hong, Qiang Zhou 0001	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Qiang Ma 0002, Evangeline F. Y. Young	Voltage island-driven floorplanning.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel	Voltage- and ABB-island optimization in high level synthesis.	ISLPED	2007	DBLP DOI BibTeX RDF	adaptive body biasing, process variation, leakage, voltage islands
11	Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou 0001, Xianlong Hong	Power Delivery Aware Floorplanning for Voltage Island Designs.	ISQED	2007	DBLP DOI BibTeX RDF
11	Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong	OPC-Friendly Bus Driven Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
11	Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry	A Low-Power Multi-Pin Maze Routing Methodology.	ISQED	2007	DBLP DOI BibTeX RDF
11	Harlan Hile, Gaetano Borriello	Information Overlay for Camera Phones in Indoor Environments.	LoCA	2007	DBLP DOI BibTeX RDF
11	Sankar P. Debnath, Ganesh P. Kumar 0002, Sukumar Jairam	Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc.	VLSI Design	2007	DBLP DOI BibTeX RDF
11	Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod	Linear-programming-based techniques for synthesis of network-on-chip architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Ruiming Chen, Hai Zhou 0001	An Efficient Data Structure for Maxplus Merge in Dynamic Programming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong	Minimizing wire length in floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak	Latency-Guided On-Chip Bus-Network Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak	A statistical methodology for wire-length prediction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Tung-Chieh Chen, Yao-Wen Chang	Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	A design methodology for application-specific networks-on-chip.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	regular topology, architecture, methodology, networks-on-chip, Application-specific
11	Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin	Floorplanning Based on Particle Swarm Optimization.	ISVLSI	2006	DBLP DOI BibTeX RDF
11	Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb	Die Stacking (3D) Microarchitecture.	MICRO	2006	DBLP DOI BibTeX RDF
11	Minsik Cho, Hongjoong Shin, David Z. Pan	Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang	Simultaneous block and I/O buffer floorplanning for flip-chip design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Love Singhal, Elaheh Bozorgzadeh	Physically-aware exploitation of component reuse in a partially reconfigurable architecture.	IPDPS	2006	DBLP DOI BibTeX RDF
11	Krishnan Srinivasan, Karam S. Chatha	Layout aware design of mesh based NoC architectures.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	network-on-chip, automated design, mesh topology
11	Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu	Analog placement with symmetry and other placement constraints.	ICCAD	2006	DBLP DOI BibTeX RDF	symmetry constraints, placement, analog circuits, sequence-pair
11	Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh	A congestion-driven buffer planner with space reservation.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani	How does partitioning matter for 3D floorplanning?	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	partitioning, floorplanning, 3D IC, wire length
11	Wei-Lun Hung, Greg M. Link, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin	Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.	ISQED	2006	DBLP DOI BibTeX RDF
11	Jia Wang 0003, Hai Zhou 0001, Ping-Chih Wu	Processing Rate Optimization by Sequential System Floorplanning.	ISQED	2006	DBLP DOI BibTeX RDF
11	Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma	A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Jai-Ming Lin, Yao-Wen Chang	TCG: A transitive closure graph-based representation for general floorplans.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF