Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | N. Lakhdar, Fayçal Djeffal |
New optimized Dual-Material (DM) gate design to improve the submicron GaN-MESFETs reliability in subthreshold regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 52(6), pp. 958-963, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | S.-L. Siu, Wing-Shan Tam, Hei Wong, Chi-Wah Kok, K. Kakusima, Hiroshi Iwai |
Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 52(8), pp. 1606-1609, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Mukund Kalyanaraman, Michael Orshansky |
Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2012, pp. 413, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
15 | Benjamin Torben-Nielsen, Idan Segev, Yosef Yarom |
The Generation of Phase Differences and Frequency Changes in a Network Model of Inferior Olive Subthreshold Oscillations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLoS Comput. Biol. ![In: PLoS Comput. Biol. 8(7), 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang |
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(12), pp. 863-867, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Fabio Frustaci, Pasquale Corsonello, Stefania Perri |
Analytical Delay Model Considering Variability Effects in Subthreshold Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(3), pp. 168-172, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Woojin Rim, Woong Choi, Jongsun Park 0001 |
Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(9), pp. 587-591, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Ming-Hung Chang, Yi-Te Chiu, Wei Hwang |
Design and Iso-Area Vmin Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(7), pp. 429-433, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Chenchang Zhan, Wing-Hung Ki |
An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(5), pp. 1119-1131, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang |
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(12), pp. 878-882, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Peter Grossmann, Miriam Leeser, Marvin Onabajo |
Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(12), pp. 942-946, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Yingchieh Ho, Chiachi Chang, Chauchin Su |
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(1), pp. 55-59, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Armin Tajalli, Yusuf Leblebici |
Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(12), pp. 903-907, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Morteza Nabavi, Maitham Shams |
A gate sizing and transistor fingering strategy for subthreshold CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 9(19), pp. 1550-1555, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Michael J. Roy, Michelle E. Costanzo, Suzanne Leaman |
Psychophysiologic Identification of Subthreshold PTSD in Combat Veterans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Review of Cybertherapy and Telemedicine ![In: Annual Review of Cybertherapy and Telemedicine 2012 - Advanced Technologies in the Behavioral, Social and Neurosciences, pp. 149-155, 2012, IOS Press, 978-1-61499-120-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Shilpa Pendyala, Srinivas Katkoori |
Interval arithmetic based input vector control for RTL subthreshold leakage minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, pp. 141-146, 2012, IEEE, 978-1-4673-2657-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Viviane S. Ghaderi, Shane M. Roach, Dong Song, Vasilis Z. Marmarelis, John Choma Jr., Theodore W. Berger |
Analog low-power hardware implementation of a Laguerre-Volterra model of intracellular subthreshold neuronal activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMBC ![In: Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2012, San Diego, CA, USA, August 28 - September 1, 2012, pp. 767-770, 2012, IEEE, 978-1-4244-4119-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Weiwei Shi 0001, Oliver Chiu-sing Choy |
A process-compatible passive RFID tag's digital design for subthreshold operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 528-531, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Kiyohiko Sakakibara, Toshio Kumamoto, K. Arimoto |
Impact of subthreshold hump on bulk-bias dependence of offset voltage variability in weak and moderate inversion regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-1555-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Sven Lütkemeier, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001 |
A 200mV 32b subthreshold processor with adaptive supply voltage control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, pp. 484-486, 2012, IEEE, 978-1-4673-0376-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Kyle Craig, Yousef Shakhsheer, Benton H. Calhoun |
Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012, pp. 221-224, 2012, ACM, 978-1-4503-1249-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | A. R. Aravinth Kumar, Ashudeb Dutta, Shiv Govind Singh |
A 1.5-7.5GHz low power low noise amplifier (LNA) design using subthreshold technique for Wireless Sensor Network (WSN) application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 1943-1946, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou |
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 2553-2556, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Erkka Laulainen, Matthew J. Turnquist, Jani Mäkipää, Lauri Koskinen |
Adaptive subthreshold timing-error detection 8 bit microcontroller in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 2953-2956, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | A. R. Aravinth Kumar, Ashudeb Dutta, Shiv Govind Singh |
Noise-cancelled subthreshold UWB LNA for Wireless Sensor Network application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUWB ![In: IEEE International Conference on Ultra-Wideband, ICUWB 2012, Syracuse, NY, USA, September 17-20, 2012, pp. 383-386, 2012, IEEE, 978-1-4577-2031-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Ming Liu 0015, Xu Zhang 0010, Hong Chen 0002, Chun Zhang, Zhihua Wang 0001 |
A fast computable delay model for subthreshold circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 25th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2012, Montreal, QC, Canada, April 29 - May 2, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-1431-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Wei-Bin Yang, Chi-Hsiung Wang, I-Ting Chuo, Huang-Hsuan Hsu |
A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2012, Tamsui, New Taipei City, Taiwan, November 4-7, 2012, pp. 604-608, 2012, IEEE, 978-1-4673-5083-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama |
Power-saving analysis of adiabatic logic in subthreshold region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2012, Tamsui, New Taipei City, Taiwan, November 4-7, 2012, pp. 590-594, 2012, IEEE, 978-1-4673-5083-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Jun Zhang, Yunling Luo, Qiaobo Wang, Jingjing Li, Zhuqian Gong, Hong-Zhou Tan, Yunliang Long |
A low-voltage, low-power subthreshold CMOS voltage reference without resistors and high threshold voltage devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012, pp. 384-387, 2012, IEEE, 978-1-4577-1728-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Tsung-Sum Lee, Wen-Zhe Lu, Yi-Cheng Huang |
A 0.6-V subthreshold-leakage supressed CMOS fully differential switched-capacitor amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012, pp. 152-155, 2012, IEEE, 978-1-4577-1728-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Bo Liu, Maryam Ashouei, Jos Huisken, José Pineda de Gyvez |
Standard cell sizing for subthreshold operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, pp. 962-967, 2012, ACM, 978-1-4503-1199-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Luca Magnelli |
Subthreshold design of ultra low-power analog modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
RDF |
|
15 | Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, Wei-Cheng Wu |
A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 46(2), pp. 520-529, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Cheng-Hung Lo, Shi-Yu Huang |
P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 46(3), pp. 695-704, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Luca Magnelli, Felice Crupi, Pasquale Corsonello, Calogero Pace, Giuseppe Iannaccone |
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 46(2), pp. 465-474, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Michael B. Henry, Leyla Nazhandali |
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers IV, pp. 175-194, 2011, Springer, 978-3-642-24567-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Michiel W. H. Remme, John Rinzel |
Role of active dendritic conductances in subthreshold input integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Neurosci. ![In: J. Comput. Neurosci. 31(1), pp. 13-30, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Woochang Lim, Sang-Yoon Kim |
Statistical-mechanical measure of stochastic spiking coherence in a population of inhibitory subthreshold neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Neurosci. ![In: J. Comput. Neurosci. 31(3), pp. 667-677, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa |
Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 94-C(1), pp. 80-88, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa |
Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 94-C(6), pp. 1042-1048, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Saurav Chakraborty, Abhijit Mallik, Chandan Kumar Sarkar |
Subthreshold performance of pocket-implanted silicon-on-insulator CMOS devices and circuits for ultra-low-power analogue/mixed-signal applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 5(4), pp. 343-350, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Amir Hasanbegovic, Snorre Aunet |
Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 35(1), pp. 1-9, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Osamu Hoshino |
Neuronal Responses Below Firing Threshold for Subthreshold Cross-Modal Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. ![In: Neural Comput. 23(4), pp. 958-983, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Osamu Hoshino |
Subthreshold Membrane Depolarization as Memory Trace for Perceptual Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. ![In: Neural Comput. 23(12), pp. 3205-3231, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9), pp. 1349-1358, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Zhihao Ding, Guangxi Hu, Jinglun Gu, Ran Liu 0001, Lingli Wang, Tingao Tang |
An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 42(3), pp. 515-519, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | S. D. Pable, Mohd. Hasan |
High speed interconnect through device optimization for subthreshold FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 42(3), pp. 545-552, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Fayçal Djeffal, Toufik Bendib, Mohamed Amir Abdi |
A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 42(12), pp. 1391-1395, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | J. Kevin Hicks, Dhireesha Kudithipudi |
Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 7(2), pp. 172-184, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Abhijit Sil, Magdy A. Bayoumi |
A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 7(1), pp. 96-109, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3), pp. 335-342, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo |
Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2), pp. 183-192, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Hak-Kee Jung |
Analysis of Subthreshold Characteristics for Device Parameter of DGMOSFET Using Gaussian Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inform. and Commun. Convergence Engineering ![In: J. Inform. and Commun. Convergence Engineering 9(6), pp. 733-737, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Ji-Hyeong Han, Hak-Kee Jung, Choon-Shik Park |
Structure-Dependent Subthreshold Swings for Double-gate MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inform. and Commun. Convergence Engineering ![In: J. Inform. and Commun. Convergence Engineering 9(5), pp. 583-586, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye |
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 58-II(5), pp. 299-303, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Chutham Sawigun, Wouter A. Serdijn |
Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(7), pp. 1615-1626, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Manmit Muker, Maitham Shams |
Preference of designing CMOS subthreshold logic circuits using uniform-size transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 8(23), pp. 1983-1988, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Indika U. K. Bogoda Appuhamylage, Daisuke Kanemoto, Kenji Taniguchi 0001 |
A Novel 100ppm/°C current reference for ultra-low-power subthreshold applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 8(3), pp. 168-174, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Bipul C. Paul, Arijit Raychowdhury |
Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 185-207, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Antonio Cerdeira, Magali Estrada, Benjamín Iñíguez, S. Soto |
Modeling the subthreshold region of OTFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCE ![In: 8th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2011, Merida City, Mexico, October 26-28, 2011, pp. 1-4, 2011, IEEE. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Joseph Sankman, Dongsheng Ma 0001 |
A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011, pp. 363-367, 2011, IEEE, 978-1-4577-0171-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Peter Grossmann, Miriam Leeser |
A prototype FPGA for subthreshold-optimized CMOS (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011, pp. 279, 2011, ACM, 978-1-4503-0554-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa |
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011, pp. 113-114, 2011, IEEE, 978-1-4244-7516-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Matthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Lauri Koskinen |
Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, pp. 1-4, 2011, IEEE, 978-1-4577-0514-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang |
A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 291-296, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
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15 | Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi |
A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 61-64, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Hao Zhang 0087, Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara |
CMOS low-power subthreshold reference voltage utilizing self-biased body effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 516-519, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Yilei Li, Yu Wang 0046, Na Yan, Xi Tan, Hao Min |
A subthreshold MOSFET bandgap reference with ultra-low power supply voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 862-865, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Kyungseok Kim, Vishwani D. Agrawal |
Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011, pp. 689-694, 2011, IEEE, 978-1-61284-914-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Adnan Abdul-Aziz Gutub |
Subthreshold SRAM Designs for Cryptography Security Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSECS (1) ![In: Software Engineering and Computer Systems - Second International Conference, ICSECS 2011, Kuantan, Pahang, Malaysia, June 27-29, 2011, Proceedings, Part I, pp. 104-110, 2011, Springer, 978-3-642-22169-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Chen Hu, Jun Yang, Meng Zhang, Xiulong Wu |
A 12T Subthreshold SRAM Bit-Cell for Medical Device Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CyberC ![In: 2011 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC 2011, Beijing, China, October 10-12, 2011, pp. 540-543, 2011, IEEE Computer Society, 978-1-4577-1827-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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15 | Ik Joon Chang, Sang Phill Park, Kaushik Roy 0001 |
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 45(2), pp. 401-410, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe 0001, Marios C. Papaefthymiou |
187 MHz Subthreshold-Supply Charge-Recovery FIR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 45(4), pp. 793-803, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Benton H. Calhoun, David M. Brooks |
Can Subthreshold and Near-Threshold Circuits Go Mainstream? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(4), pp. 80-85, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(7), pp. 1118-1129, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai |
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 93-C(3), pp. 332-339, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya |
High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 93-C(6), pp. 741-746, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal |
Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 4(6), pp. 548-560, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Pramod Kumar Tiwari, Chinmay R. Panda, Anupam Agarwal, Pratik Sharma, Satyabrata Jit |
Modelling of doping-dependent subthreshold swing of symmetric double-gate MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 4(4), pp. 337-345, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Lars Wolff, Benjamin Lindner |
Mean, Variance, and Autocorrelation of Subthreshold Potential Fluctuations Driven by Filtered Conductance Shot Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. ![In: Neural Comput. 22(1), pp. 94-120, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal |
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 41(4), pp. 195-211, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | David Bol, Denis Flandre, Jean-Didier Legat |
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 16(1), pp. 2:1-2:26, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | David Coleman, Jia Di |
Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 6(2), pp. 320-324, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal |
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 6(1), pp. 103-114, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Armin Tajalli, Yusuf Leblebici |
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 6(1), pp. 211-217, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Hak-Kee Jung, Ji-Hyeong Han |
Design of DGMOSFET for Optimum Subthreshold Characteristics using MicroTec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inform. and Commun. Convergence Engineering ![In: J. Inform. and Commun. Convergence Engineering 8(4), pp. 449-452, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Udit Monga, H. Børli, Tor A. Fjeldly |
Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Comput. Model. ![In: Math. Comput. Model. 51(7-8), pp. 901-907, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Steven A. Vitale, Peter W. Wyatt, Nisha Checka, Jakub Kedzierski, Craig L. Keast |
FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 98(2), pp. 333-342, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Sumeet Kumar Gupta, Arijit Raychowdhury, Kaushik Roy 0001 |
Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 98(2), pp. 160-190, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Ryan D. Jorgenson, Lief Sorensen, Dan Leet, Michael S. Hagedorn, David R. Lamb, Thomas Hal Friddell, Warren P. Snapp |
Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 98(2), pp. 299-314, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock |
An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 57-II(4), pp. 290-294, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Massimo Alioto |
Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7), pp. 1597-1607, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Ling Su, Dongsheng Ma 0001, A. Paul Brokaw |
Design and Analysis of Monolithic Step-Down SC Power Converter With Subthreshold DPWM Control for Self-Powered Wireless Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1), pp. 280-290, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 57-II(9), pp. 681-685, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Sven Lütkemeier, Ulrich Rückert 0001 |
A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 57-II(9), pp. 721-724, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang |
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12), pp. 3039-3047, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Kapil K. Rajput, Anil K. Saini, Subash Chandra Bose |
DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 247-252, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Armin Tajalli, Yusuf Leblebici |
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 711-716, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 361-362, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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15 | Armin Tajalli, Yusuf Leblebici |
Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010, pp. 174-177, 2010, IEEE, 978-1-4244-6662-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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