Search results for "BIST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Elham K. Moghaddam, Shaahin Hessabi	An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits.	DSD	2007	DBLP DOI BibTeX RDF
22	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Digital Generation of Signals for Low Cost RF BIST.	ETS	2007	DBLP DOI BibTeX RDF
22	Xiaoding Chen, Michael S. Hsiao	Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	built-in-self-test, System-on-a-chip, spectral analysis
22	Jiun-Lang Huang, Jui-Jer Huang, Yuan-Shuang Liu	A Low-Cost Jitter Measurement Technique for BIST Applications.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	random jitter, jitter measurement, built-in self-test
22	Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi	An Optimized BIST Architecture for FPGA Look-Up Table Testing.	ISVLSI	2006	DBLP DOI BibTeX RDF
22	Malav Shah, Dipankar Nagchoudhuri	BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
22	Livier Lizarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur	Study of a BIST Technique for CMOS Active Pixel Sensors.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
22	Slimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa	A Transparent based Programmable Memory BIST.	ETS	2006	DBLP DOI BibTeX RDF
22	Vincent Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, Jean-Marie Janik, B. Agnus, Philippe Cauvet, Ph. Gandy	A Low Cost Alternative Method for Harmonics Estimation in a BIST Context.	ETS	2006	DBLP DOI BibTeX RDF
22	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
22	Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.	IOLTS	2006	DBLP DOI BibTeX RDF
22	Yuejian Wu, André Ivanov	Low Power SoC Memory BIST.	DFT	2006	DBLP DOI BibTeX RDF
22	Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro	A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters.	VTS	2006	DBLP DOI BibTeX RDF
22	Chunsheng Liu, Krishnendu Chakrabarty	Design and analysis of compact dictionaries for diagnosis in scan-BIST.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
22	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Noise Figure Evaluation Using Low Cost BIST.	DATE	2005	DBLP DOI BibTeX RDF
22	B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu	At-Speed Logic BIST for IP Cores.	DATE	2005	DBLP DOI BibTeX RDF
22	Zhiyuan He 0002, Gert Jervan, Zebo Peng, Petru Eles	Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.	DSD	2005	DBLP DOI BibTeX RDF
22	Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang	A BIST Scheme Based on Selecting State Generation of Folding Counters.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
22	Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo	At-Speed Logic BIST Architecture for Multi-Clock Designs.	ICCD	2005	DBLP DOI BibTeX RDF
22	Anand Gopalan, Tejasvi Das, Clyde Washburn, Ponnathpur R. Mukund	Use of source degeneration for non-intrusive BIST of RF front-end circuits.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
22	Jinkyu Lee 0005, Nur A. Touba	Low Power BIST Based on Scan Partitioning.	DFT	2005	DBLP DOI BibTeX RDF
22	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
22	Yun-Che Wen	A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses.	VTS	2005	DBLP DOI BibTeX RDF
22	Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew	Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.	VTS	2005	DBLP DOI BibTeX RDF
22	Chunsheng Liu, Krishnendu Chakrabarty	Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
22	Michael Gössel, Krishnendu Chakrabarty, Vitalij Ocheretnij, Andreas Leininger	A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	algebraic analysis, intervals of test vectors, fault diagnosis, linearity, MISR
22	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	IEEE P1500, diagnosis, Hough transform, embedded memories
22	Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton	Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.	ISVLSI	2004	DBLP DOI BibTeX RDF
22	Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos	Scan Cell Ordering for Low Power BIST.	ISVLSI	2004	DBLP DOI BibTeX RDF
22	Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study.	DATE	2004	DBLP DOI BibTeX RDF
22	Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki	Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
22	Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu	Low Power BIST with Smoother and Scan-Chain Reorder .	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
22	Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu	Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
22	Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
22	Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko	BIST Based Interconnect Fault Location for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
22	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001	A Technique to Reduce Power and Test Application Time in BIST.	IOLTS	2004	DBLP DOI BibTeX RDF
22	Shalini Ghosh, Eric W. MacDonald, Sugato Basu, Nur A. Touba	Low-power weighted pseudo-random BIST using special scan cells.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	weighted pseudo-random testing, low power, built-in self-test
22	Jerzy J. Dabrowski, Javier Gonzalez Bayon	Mixed Loopback BiST for RF Digital Transceivers.	DFT	2004	DBLP DOI BibTeX RDF
22	Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy	Scan BIST Targeting Transition Faults Using a Markov Source.	ISQED	2004	DBLP DOI BibTeX RDF
22	Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius 0001, Rosa Rodríguez-Montañés, Joan Figueras	BIST Technique by Equally Spaced Test Vector Sequences.	VTS	2004	DBLP DOI BibTeX RDF
22	Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan	Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.	ITC	2004	DBLP DOI BibTeX RDF
22	C. J. Clark, Mike Ricchetti	A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and Systems.	ITC	2004	DBLP DOI BibTeX RDF
22	Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng	Logic BIST with Scan Chain Segmentation.	ITC	2004	DBLP DOI BibTeX RDF
22	Raimund Ubar, Maksim Jenihhin	Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting.	DELTA	2004	DBLP DOI BibTeX RDF
22	Peter Wohl, John A. Waicukauski, Sanjay Patel	Scalable selector architecture for x-tolerant deterministic BIST.	DAC	2004	DBLP DOI BibTeX RDF	test-generation (ATPG), test-data compression
22	Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell	On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF
22	Doris Lupea, Udo Pursche, Hans-Joachim Jentschel	RF-BIST: Loopback Spectral Signature Analysis.	DATE	2003	DBLP DOI BibTeX RDF
22	Chunsheng Liu, Krishnendu Chakrabarty	A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis.	DATE	2003	DBLP DOI BibTeX RDF
22	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin	Test Time Minimization for Hybrid BIST of Core-Based Systems.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
22	Huaguo Liang, Cuiyun Jiang	Sharing BIST with Multiple Cores for System-on-a-Chip.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
22	He Hu 0002, Yihe Sun	Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
22	Chaowen Yu, Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz	An Improved Markov Source Design for Scan BIST.	IOLTS	2003	DBLP DOI BibTeX RDF
22	Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou	An Efficient BIST scheme for High-Speed Adders.	IOLTS	2003	DBLP DOI BibTeX RDF
22	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos	A highly regular multi-phase reseeding technique for scan-based BIST.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	scan-based schemes, built-in self-test, linear feedback shift registers, reseeding
22	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin	Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture.	DFT	2003	DBLP DOI BibTeX RDF
22	John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani	A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits.	DFT	2003	DBLP DOI BibTeX RDF
22	Ahmad A. Al-Yamani, Edward J. McCluskey	Built-In Reseeding for Serial Bist.	VTS	2003	DBLP DOI BibTeX RDF
22	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Ultra Low Cost Analog BIST Using Spectral Analysis.	VTS	2003	DBLP DOI BibTeX RDF
22	Xiaoding Chen, Michael S. Hsiao	Energy-Efficient Logic BIST Based on State Correlation Analysis.	VTS	2003	DBLP DOI BibTeX RDF
22	Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin	X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.	ITC	2003	DBLP DOI BibTeX RDF
22	Cheng Jia, Linda S. Milor	A BIST Solution for The Test of I/O Speed.	ITC	2003	DBLP DOI BibTeX RDF
22	Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante	Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores.	ITC	2003	DBLP DOI BibTeX RDF
22	Ramesh C. Tekumalla	On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures.	ITC	2003	DBLP DOI BibTeX RDF
22	Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang 0008	Low-Energy BIST Design for Scan-based Logic Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
22	Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee	An efficient BIST method for distributed small buffers.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
22	Seongmoon Wang, Sandeep K. Gupta 0001	DS-LFSR: a BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
22	Ismet Bayraktaroglu, Alex Orailoglu	Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
22	Ismet Bayraktaroglu, Alex Orailoglu	Gate Level Fault Diagnosis in Scan-Based BIST.	DATE	2002	DBLP DOI BibTeX RDF
22	Sangmin Bae, DongSup Song, Jihye Kim, Sungho Kang	An Efficient On-Line Monitoring BIST for Remote Service System.	AISA	2002	DBLP DOI BibTeX RDF
22	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF
22	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	MTDT	2002	DBLP DOI BibTeX RDF
22	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	ICCD	2002	DBLP DOI BibTeX RDF
22	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.	ICCD	2002	DBLP DOI BibTeX RDF
22	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
22	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	IOLTW	2002	DBLP DOI BibTeX RDF
22	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	IOLTW	2002	DBLP DOI BibTeX RDF
22	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST.	ISQED	2002	DBLP DOI BibTeX RDF	Test-per-Clock Schemes, Reseeding Techniques, Built-In Self-Test, Linear Feedback Shift Registers, Test Pattern Generation
22	Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus	A Hybrid BIST Architecture and Its Optimization for SoC Testing.	ISQED	2002	DBLP DOI BibTeX RDF
22	Karim Arabi	Logic BIST and Scan Test Techniques for Multiple Identical Blocks.	VTS	2002	DBLP DOI BibTeX RDF
22	René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	On Using Efficient Test Sequences for BIST.	VTS	2002	DBLP DOI BibTeX RDF
22	Aubin Roy, Stephen K. Sunter, Alessandra Fudoli, Davide Appello	High Accuracy Stimulus Generation for A/D Converter BIST.	ITC	2002	DBLP DOI BibTeX RDF
22	Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
22	Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara	Hybrid BIST Using Partially Rotational Scan.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
22	Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi	Fault Simulation for VHDL Based Test Bench and BIST Evaluation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
22	Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang	Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF
22	Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell	Analog BIST Generator for ADC Testing.	DFT	2001	DBLP DOI BibTeX RDF
22	Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian	Power-/Energy Efficient BIST Schemes for Processor Data Paths.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
22	Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich	Optimal Hardware Pattern Generation for Functional BIST.	DATE	2000	DBLP DOI BibTeX RDF
22	José Machado da Silva, J. Soeiro Duarte, José Silva Matos	Mixed-Signal BIST Using Correlation and Reconfigurable Hardware.	DATE	2000	DBLP DOI BibTeX RDF
22	Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng	A BIST Scheme for On-Chip ADC and DAC Testing.	DATE	2000	DBLP DOI BibTeX RDF
22	Michael Redeker, Markus Rudack, Thomas Lobbe, Dirk Niggemeyer	Using GLFSRs for Pseudo-Random Memory BIST.	MTDT	2000	DBLP DOI BibTeX RDF
22	Ondrej Novák, Jiri Nosek	On Using Deterministic Test Sets in BIST.	IOLTW	2000	DBLP DOI BibTeX RDF
22	Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand	Hardware Resource Minimization for Histogram-Based ADC BIST.	VTS	2000	DBLP DOI BibTeX RDF
22	Ismet Bayraktaroglu, Alex Orailoglu	Improved fault diagnosis in scan-based BIST via superposition.	DAC	2000	DBLP DOI BibTeX RDF
22	Andreas Steininger, Christoph Scherrer	On the Necessity of On-Line-BIST in Safety-Critical Applications - A Case Study.	FTCS	1999	DBLP DOI BibTeX RDF
22	Xiaowei Li 0001, Paul Y. S. Cheung	Data Path Synthesis for BIST with Low Area Overhead.	ASP-DAC	1999	DBLP DOI BibTeX RDF
22	Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
22	Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001	Test pattern generation for width compression in BIST.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
22	Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud	Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access.	VTS	1999	DBLP DOI BibTeX RDF