Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay	Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
17	David B. Thomas, Wayne Luk	The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
17	Rogelio Hasimoto-Beltrán	Freac-LUT: a New Dynamic Look-up Table Approach to Secure Chaotic Encryption.	Int. J. Bifurc. Chaos	2013	DBLP DOI BibTeX RDF
17	Stavros P. Dokouzyannis, Argiris P. Mokios	Evaluation Study of Systolic Array Processors Optimization and Mapping on k-LUT FPGA Devices.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
17	Khalid Omari, H. Peter White, Karl Staenz, Douglas J. King	Retrieval of Forest Canopy Parameters by Inversion of the PROFLAIR Leaf-Canopy Reflectance Model Using the LUT Approach.	IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.	2013	DBLP DOI BibTeX RDF
17	Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell	A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
17	Tadanari Taniguchi, Luka Eciolaza, Michio Sugeno	LUT Controller Design with Piecewise Bilinear Systems Using Estimation of Bounds for Approximation Errors.	J. Adv. Comput. Intell. Intell. Informatics	2013	DBLP DOI BibTeX RDF
17	Anh-Tuan Hoang, Takeshi Fujino	Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
17	Bilal Habib, Kris Gaj, Jens-Peter Kaps	FPGA PUF Based on Programmable LUT Delays.	DSD	2013	DBLP DOI BibTeX RDF
17	Parthasarathy M. B. Rao, Abdulazim Amouri, Saman Kiamehr, Mehdi Baradaran Tahoori	Altering LUT configuration for wear-out mitigation of FPGA-mapped designs.	FPL	2013	DBLP DOI BibTeX RDF
17	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	A packet classifier using LUT cascades based on EVMDDS (k).	FPL	2013	DBLP DOI BibTeX RDF
17	Anup Das 0001, Shyamsundar Venkataraman, Akash Kumar 0001	Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation.	FPL	2013	DBLP DOI BibTeX RDF
17	Viviane Lucy Santos de Souza, Abel G. Silva-Filho	MogaMap: An application of multi-objective genetic algorithm for LUT-based FPGA technology mapping.	ICECS	2013	DBLP DOI BibTeX RDF
17	Jung Rae Ryoo, Eun Sang Lee, Hyun Keun Park	Real-time implementation of an LUT-based image warping system.	ISR	2013	DBLP DOI BibTeX RDF
17	Richard J. B. Dobson, Kathleen Steinhöfel	Sa based power efficient FPGA LUT mapping.	GECCO (Companion)	2013	DBLP DOI BibTeX RDF
17	Lingwei Zhang, Hanjun Jiang, Fule Li, Jingjing Dong, Zhihua Wang 0001	A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue.	ISCAS	2013	DBLP DOI BibTeX RDF
17	Martin Kumm, Konrad Möller, Peter Zipf	Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs.	ISCAS	2013	DBLP DOI BibTeX RDF
17	Chung-Ping Hung, Paul S. Min	Access LUT without CAM - Improved Pearson hashing for collision reduction.	ICON	2013	DBLP DOI BibTeX RDF
17	Wei Lam Kong, Nicholas Chan Hua Vun	Design of LUT based RNS reverse converters.	ISCE	2013	DBLP DOI BibTeX RDF
17	Van-Phuc Hoang, Cong-Kha Pham	An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
17	Van-Phuc Hoang, Cong-Kha Pham	Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
17		An Efficient Biological Sequence Compression Technique Using LUT And Repeat In The Sequence	CoRR	2012	DBLP BibTeX RDF
17	Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu	Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.	MWSCAS	2012	DBLP DOI BibTeX RDF
17	Chris C. Wang, Guy G. F. Lemieux	Parallel FPGA placement based on individual LUT placement (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
17	Anh-Tuan Hoang, Takeshi Fujino	Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA.	FPGA	2012	DBLP DOI BibTeX RDF
17	Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen	Mapping into LUT structures.	DATE	2012	DBLP DOI BibTeX RDF
17	Luka Eciolaza, Michio Sugeno	On-line design of LUT controllers based on desired closed loop plant: Vertex Placement Principle.	FUZZ-IEEE	2012	DBLP DOI BibTeX RDF
17	Tadanari Taniguchi, Michio Sugeno	Design of LUT-controllers for nonlinear systems with PB models based on I/O linearization.	FUZZ-IEEE	2012	DBLP DOI BibTeX RDF
17	Keita Hirai, Shoji Tominaga	A LUT-based Method for Recovering Color Signals from High Dynamic Range Images.	CIC	2012	DBLP DOI BibTeX RDF
17	Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita	SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
17	Vicente Torres-Carot, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls	Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA.	ICECS	2012	DBLP DOI BibTeX RDF
17	Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini	An improved BCD adder using 6-LUT FPGAs.	NEWCAS	2012	DBLP DOI BibTeX RDF
17	Yi-Chung Chen, Hai Li 0001, Wei Zhang 0012	A novel peripheral circuit for RRAM-based LUT.	ISCAS	2012	DBLP DOI BibTeX RDF
17	Matthew Catanzaro, Dhireesha Kudithipudi	Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement.	SoCC	2012	DBLP DOI BibTeX RDF
17	Natalia Gurieva, Igor Guryev, Francisco-Javier Montecillo-Puente, Reynaldo Thompson Lopez	Optimized color LUT transformations by means of analysis of image memorable and subject important colors.	SIGGRAPH Posters	2012	DBLP DOI BibTeX RDF
17	Jochem Verrelst, Juan Pablo Rivera, Ganna Leonenko, Luis Alonso 0002, José F. Moreno	Optimizing LUT-based radiative transfer model inversion for retrieval of biophysical parameters using hyperspectral data.	IGARSS	2012	DBLP DOI BibTeX RDF
17	Lin-bo Luo, Sangwoo Ahn, Chang-shuai Wang, Jun Chen 0019, Jong-Wha Chong	Real-Time LUT-based color correction for cell phone cameras in low light conditions without frame memory.	ICCE	2012	DBLP DOI BibTeX RDF
17	Najoua Chalbi, Mohamed Boubaker, Mohamed Bedoui Hedi	Analytical dynamic power model for LUT based components.	DTIS	2012	DBLP DOI BibTeX RDF
17	Lindsay W. MacDonald	Colour Laser Scanner Characterisation by Enhanced LUT.	CGIV	2012	DBLP BibTeX RDF
17	Asbjørn Djupdal, Pauline C. Haddow	The route to a defect tolerant LUT through artificial evolution.	Genet. Program. Evolvable Mach.	2011	DBLP DOI BibTeX RDF
17	Ahmad Hormozi, Abumoslem Jannesari	Multi-Level 2D LUT as digital pre-distorter for linearizing memory affected RF power amplifiers.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
17	Qian Du 0004	A new GMSK modulation based on LUT.	EMEIT	2011	DBLP DOI BibTeX RDF
17	Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay	Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs.	DATE	2011	DBLP DOI BibTeX RDF
17	Ameer Abdelhadi, Guy G. F. Lemieux	Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations.	ReConFig	2011	DBLP DOI BibTeX RDF
17	Keheng Huang, Yu Hu 0001, Xiaowei Li 0001, Gengxin Hua, Hongjin Liu, Bo Liu 0018	Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
17	Kashfia Haque, Paul Beckett	A Radiation Hard Lut Block with Auto-Scrubbing.	FPL	2011	DBLP DOI BibTeX RDF
17	Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He 0001	Mitigating FPGA interconnect soft errors by in-place LUT inversion.	ICCAD	2011	DBLP DOI BibTeX RDF
17	Lin-bo Luo, Changshuai Wang, Jun Chen 0019, Sangwoo An, Yeumcheul Jeung, Jongwha Chong	Improved LUT-Based Image Warping for Video Cameras.	CSE	2011	DBLP DOI BibTeX RDF
17	Saman Kiamehr, Abdulazim Amouri, Mehdi Baradaran Tahoori	Investigation of NBTI and PBTI induced aging in different LUT implementations.	FPT	2011	DBLP DOI BibTeX RDF
17	David Dickin, Lesley Shannon	Exploring FPGA technology mapping for fracturable LUT minimization.	FPT	2011	DBLP DOI BibTeX RDF
17	Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga	Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs.	ISLPED	2011	DBLP BibTeX RDF
17	Chi-Man Pun, Jing-Jing Jiang, C. L. Philip Chen	Adaptive Client-Side LUT-Based Digital Watermarking.	TrustCom	2011	DBLP DOI BibTeX RDF
17	Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai	A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain.	ASICON	2011	DBLP DOI BibTeX RDF
17	Seydou-Nourou Ba, Khurram Waheed, G. Tong Zhou	Optimal Spacing of a Linearly Interpolated Complex-Gain LUT Predistorter.	IEEE Trans. Veh. Technol.	2010	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Jacek Bieganowski	Reduction in the number of LUT elements for control units with code sharing.	Int. J. Appl. Math. Comput. Sci.	2010	DBLP DOI BibTeX RDF
17	Pongstorn Maidee, Kia Bazargan	Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
17	Jing-Ming Guo	High efficiency ordered dither block truncation coding with dither array LUT and its scalable coding application.	Digit. Signal Process.	2010	DBLP DOI BibTeX RDF
17	Tayo Obafemi-Ajayi, Gady Agam, Ophir Frieder	Historical document enhancement using LUT classification.	Int. J. Document Anal. Recognit.	2010	DBLP DOI BibTeX RDF
17	David Sarrut, Jef Vandemeulebroucke	B-LUT: Fast and low memory B-spline image interpolation.	Comput. Methods Programs Biomed.	2010	DBLP DOI BibTeX RDF
17	Pramod Kumar Meher	LUT Optimization for Memory-Based Computation.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
17	Roberto Gutierrez, Vicente Torres-Carot, Javier Valls-Coquillat	FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques.	J. Syst. Archit.	2010	DBLP DOI BibTeX RDF
17	Pramod Kumar Meher	Novel input coding technique for high-precision LUT-based multiplication for DSP applications.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
17	Deepak Kumar, Pankaj Kumar, Manisha Pattanaik	Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application.	DSD	2010	DBLP DOI BibTeX RDF
17	Vishal Monga, Raja Bala	Algorithms for color look-up-table (LUT) design via joint optimization of node locations and output values.	ICASSP	2010	DBLP DOI BibTeX RDF
17	Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer	High Density Asynchronous LUT Based on Non-volatile MRAM Technology.	FPL	2010	DBLP DOI BibTeX RDF
17	Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu	Efficient FPGA Resynthesis Using Precomputed LUT Structures.	FPL	2010	DBLP DOI BibTeX RDF
17	Jae-Man Kim, Seung-Cheol Kim, Eun-Soo Kim	Memory reduction of N-LUT method using sub-principle fringe patterns.	ICTC	2010	DBLP DOI BibTeX RDF
17	Álvaro Vázquez, Florent de Dinechin	Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs.	FPT	2010	DBLP DOI BibTeX RDF
17	Yutaka Usui, Katsuya Kondo	3D object recognition based on confidence LUT of SIFT feature distance.	NaBIC	2010	DBLP DOI BibTeX RDF
17	Zhaohui Wang, Anna Aristova, Jon Yngve Hardeberg	Evaluating the effect of noise on 3D LUT-based color transformations.	CGIV/MCS	2010	DBLP BibTeX RDF
17	Taiga Takata, Yusuke Matsunaga	Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs.	IPSJ Trans. Syst. LSI Des. Methodol.	2009	DBLP DOI BibTeX RDF
17	Taiga Takata, Yusuke Matsunaga	Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
17	Te-Jen Chang, Chia-Long Wu, Der-Chyuan Lou, Ching-Yin Chen	A low-complexity LUT-based squaring algorithm.	Comput. Math. Appl.	2009	DBLP DOI BibTeX RDF
17	Dae-Ik Kim, Changki Lee	An Efficient Interpolation FIR Filter Using LUT.	J. Inform. and Commun. Convergence Engineering	2009	DBLP BibTeX RDF
17	Meng Ding, Ruofeng Tong 0001, Shenghui Liao, Jinxiang Dong	An extension to 3D topological thinning method based on LUT for colon centerline extraction.	Comput. Methods Programs Biomed.	2009	DBLP DOI BibTeX RDF
17	Stanislaw Deniziak, Mariusz Wisniewski	A symbolic RTL synthesis for LUT-based FPGAs.	DDECS	2009	DBLP DOI BibTeX RDF
17	Eduardo Luis Rhod, Luigi Carro	A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies.	ISVLSI	2009	DBLP DOI BibTeX RDF
17	Martín Vázquez 0001, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps	Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.	ReConFig	2009	DBLP DOI BibTeX RDF	BCD, add/subtract, addtion, FPGA, subtraction, decimal arithmetic
17	Tayo Obafemi-Ajayi, Gady Agam, Ophir Frieder	Efficient shape-LUT classification for document image restoration.	DRR	2009	DBLP DOI BibTeX RDF
17	Pramod Kumar Meher	New Approach to LUT Implementation and Accumulation for Memory-based Multiplication.	ISCAS	2009	DBLP DOI BibTeX RDF
17	Heebum Park, Guiwon Seo, Chulhee Lee	Quasi-bi-quadratic Interpolation for LUT Implementation for LCD TV.	IMAGAPP	2009	DBLP BibTeX RDF
17	Riyadh A. K. Mehdi 0001, Hakim Khali	Partitioning strategy for LUT-based applications using genetic algorithms.	AICCSA	2009	DBLP DOI BibTeX RDF
17	Stanislaw Deniziak, Mariusz Wisniewski	An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs.	DDECS	2008	DBLP DOI BibTeX RDF
17	Zhan Shi, Jianmin Zhou, Hiroyuki Hayashi, Tokuro Kubo	A coefficients extraction algorithm for LUT-based Hammerstein predistorters.	PIMRC	2008	DBLP DOI BibTeX RDF
17	Ruzica Jevtic, Carlos Carreras	Analytical High-Level Power Model for LUT-Based Components.	PATMOS	2008	DBLP DOI BibTeX RDF
17	Kirill Minkovich, Jason Cong	Mapping for better than worst-case delays in LUT-based FPGA designs.	FPGA	2008	DBLP DOI BibTeX RDF	better than worst-case, razor, switching probabilities, simulation, logic synthesis, technology mapping, FPGA lookup table
17	Ruzica Jevtic, Carlos Carreras, Domenik Helms	A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGA, low power, power estimation, high-level modelling
17	Umer Farooq 0001, Zied Marrakchi, Hayder Mrabet, Habib Mehrez	The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture.	ReConFig	2008	DBLP DOI BibTeX RDF	CAD tools, FPGA design
17	Karel Bruneel, Dirk Stroobandt	Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGA, CAD, dynamic reconfiguration, technology mapping
17	Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano	On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs.	ICECS	2008	DBLP DOI BibTeX RDF
17	Hayun Chung, Andrew Liu, Gu-Yeon Wei	A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13μm CMOS.	CICC	2008	DBLP DOI BibTeX RDF
17	Moritz Schmid, Daniel Ziener, Jürgen Teich	Netlist-level IP protection by watermarking for LUT-based FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
17	Tayo Obafemi-Ajayi, Gady Agam, Ophir Frieder	Ensemble LUT classification for degraded document enhancement.	DRR	2008	DBLP DOI BibTeX RDF
17	Nicolas Normand, Pierre Évenou	Medial Axis LUT Computation for Chamfer Norms Using H-Polytopes.	DGCI	2008	DBLP DOI BibTeX RDF
17	Kuo-Liang Chung, Yong-Huai Huang	Speed up the computation of randomized algorithms for detecting lines, circles, and ellipses using novel tuning- and LUT-based voting platform.	Appl. Math. Comput.	2007	DBLP DOI BibTeX RDF
17	Munehiro Matsuura, Tsutomu Sasao	BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
17	Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera	A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
17	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
17	Jason Cong, Kirill Minkovich	Optimality Study of Logic Synthesis for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
17	Bo Ai, Zhixing Yang, Changyong Pan, Shigang Tang, Taotao Zhang	Analysis on LUT Based Predistortion Method for HPA with Memory.	IEEE Trans. Broadcast.	2007	DBLP DOI BibTeX RDF