Search results for "VLSI-DAT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Ching-Che Chung, Duo Sheng, Chen-Han Chen	An all-digital phase-locked loop compiler with liberty timing files.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Chen-Yi Lee, Kelvin Yi-Tse Lai, Shu-Yu Hsu	Event-driven read-out circuits for energy-efficient sensor-SoC's.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Yanbing Wang, Hong Wang, Deyong Meng, Bingqin Zhou	Oscillation-based diagnosis by using harmonics analysis on analog filters.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Po-Hsun Wu, Che-Wen Chen, Chi-Ruo Wu, Tsung-Yi Ho	Triangle-based process hotspot classification with dummification in EUVL.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Chetan Prasad	Advanced CMOS reliability challenges.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn	The resilience wall: Cross-layer solution strategies.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai	A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Joseph Sankman, Minkyu Song, Dongsheng Ma 0001	A 40-MHz current-mode hysteretic controlled switching converter with digital push-pull current pumping technique for high performance microprocessors.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Kun-Chih Chen, Huai-Ting Li, An-Yeu Andy Wu	LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li	Skillfully diminishing antenna effect in layer assignment stage.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Chih-Hao Lin, Chih-Cheng Hsieh, Che-Chun Lin, Ren-Jr Chen	A dual-mode CMOS image sensor for optical wireless communication.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou	An ultra-low-power adaptive-body-bias control for subthreshold circuits.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar	Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee	Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Jean-Pierre Raskin	SOI technology: An opportunity for RF designers?	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Seok-Hee Lee	Scaling trends and challenges of advanced memory technology.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang	Two-staged parallel layer-aware partitioning for 3D designs.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Franz Dielacher, Marc Tiebout, Rudolf Lachner, Herbert Knapp, Klaus Aufinger, Willy Sansen	SiGe BiCMOS technology and circuits for active safety systems.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Rong-Zhou Kuo, Hao-Chiao Hong	A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Nick Cheng	Highly integrated 4G front end modules for handset applications - A designer's perspective.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Wei Zhang 0078, Yizhi Han, Fei Chen 0006, Bo Zhou 0008, Xican Chen, Woogeun Rhee, Zhihua Wang 0001	A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	Bumman Kim	Bias adapted operation of CMOS PA for handset application.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
1	James P. Young, Nick Cheng	Multimode multiband power amplifier optimization for mobile applications.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yin-Chi Peng, Chien-Chih Chen, Chia-Jung Chang, Tien-Fu Chen, Pen-Chung Yew	Cross-layer dynamic prefetching allocation strategies for high-performance multicores.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Federico A. Altolaguirre, Ming-Dou Ker	Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Tanya Nigam	CMOS reliability: From discrete device degradation to circuit aging.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu	A layout-aware automatic sizing approach for retargeting analog integrated circuits.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Hongyi Wang, Xi Hu, Quanfeng Liu, Gangdong Zhao, Dongzhe Luo	A novel on-chip current-sensing structure for current-mode DC-DC converter.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chun-Hung Lai, Yun-Chung Yang, Ing-Jer Huang	A versatile data cache for trace buffer support.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Laurent Le-Pailleur	FDSOI: A differentiator for application processors in consumer and mobile markets.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu	A process-scalable RF transmitter using 90nm and 65nm Si CMOS.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Cosette Y. H. Lin, Ryan H.-M. Huang, Charles H.-P. Wen, Austin C.-C. Chang	Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Hui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang	Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Shingo Yamanouchi, Kazuaki Kunihiro, Shinichi Hori, Masao Ikekawa, Naoki Nishi	RF and signal processing technologies for 4G mobile networks.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Vida Ilderem	M2M: Challenges and opportunities.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chia-Yu Yao, Yung-Hsiang Ho	A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ta-Kan Yen, Hsien-Kai Kuo, Bo-Cheng Charles Lai	A distributed thread scheduler for dynamic multithreading on throughput processors.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chih-Ting Yeh, Ming-Dou Ker	Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou	Power and area reduction in multi-stage addition using operand segmentation.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino	The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	R. Yuan, Shanq-Jang Ruan, Jürgen Götze	A practical NoC design for parallel DES computation.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin	A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Do-Gyoon Song, Jaeha Kim	A low-power high-radix switch fabric based on low-swing signaling and partially-activated input lines.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Shing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen	A configurable bus-tracer for error reproduction in post-silicon validation.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Kunzhi Yu, Xuqiang Zheng, Ke Huang 0003, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang 0001	A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Zong-Han Yang, Tsung-Yi Ho	Timing-aware clock gating of pulsed-latch circuits for low power design.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Jui-Chieh Liao, Wei-Yeh Shih, Kuan-Ju Huang, Wai-Chi Fang	An online recursive ICA based real-time multichannel EEG system on chip design with automatic eye blink artifact rejection.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Bill Penner	Multi-processor debug in SoC and processor designs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura	A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ted Chang	In and out of the cloud.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chih-Sheng Hou, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu	An FPGA-based test platform for analyzing data retention time distribution of DRAMs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Hsien-Hsin Sean Lee	The quest for a new dimension of system integration.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Rodd Novak	UltraCMOS® technology for high-performance switch paths and tunable components.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou	Worst-case IR-drop monitoring with 1GHz sampling rate.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Tsung-Ching Lin, Shin-Kai Chen, Chih-Wei Liu	A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chen-Yu Wang, Jhih-Sian Guo, Chi-Yuan Huang, Chien-Hung Tsai	A high effieciency DC/DC boost regulator with adaptive off/on-time control.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Yu-Siao Chen, Katherine Shu-Min Li	Low-cost testing of TSVs in 3D stacks with pre-bond testable dies.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Jeong-Tyng Li	Design challenges for analog & mixed signal designs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chung-Ming Huang, Wei-Da Guo, Chia-Re Shen, Chih-Chung Tsai	Silicon-package-board co-design for the eye diagram prediction of a 3Gbps HDMI transmitter.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Pei-Chia Patty Lin, Evason Du, Ren-Song Tsay	A fast and accurate instruction-oriented processor simulation approach.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yun-Chih Tsai, Tai-Hung Li, Tai-Chen Chen, Chung-Wei Yeh	Electromigration- and obstacle-avoiding routing tree construction.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu	A background calibration technique for fully dynamic flash ADCs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Thomas Lee	Terahertz electronics: Opportunities, challenges and technologies.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chin-Yu Lin, Tai-Cheng Lee	Jitter error cancellation technique in digital domain for ADC.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Gennadi Bersuker	Microscopic degradation models for advanced technology.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai	A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Min Tan 0004, Wing-Hung Ki	Current-mirror miller compensation: An improved frequency compensation technique for two-stage amplifiers.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Hung-Chang Yu, Ku-Feng Lin, Kai-Chun Lin, Yu-Der Chih, Sreedhar Natarajan	A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Po-An Tsai, Yu-Hsin Kuo, En-Jui Chang, Hsien-Kai Hsin, An-Yeu Wu	Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Kuan-Hung Chen	Reducing computation redundancy for high-efficiency view synthesis.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Jui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo	A view scalable multi-view video decoder system.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Eric Chang, Frankie Liu, Philip Amberg, Jon K. Lexau, Ron Ho	Efficient techniques for canceling transceiver noise.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ching-Che Chung, Duo Sheng, Wei-Siang Su	A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Jia-Hua Hong, Ming-Chun Liang, Jing-Yi Wong, Shuenn-Yuh Lee	A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai	Enabling inter-die co-optimization in 3-D IC with TSVs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chung-Han Chou, Nien-Yu Tsai, Hao Yu 0001, Yiyu Shi 0001, Jui-Hung Chien, Shih-Chieh Chang	On the futility of thermal through-silicon-vias.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Lei Wang 0070, Chun-Huat Heng, Yong Lian 0001	A sub-GHz mostly digital impulse radio UWB transceiver for wireless body sensor networks.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chang-Ming Lai, Yi-Chung Chen, Po-Chiun Huang	Time-domain analog-to-digital converters with domino delay lines.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Shyue-Kung Lu, Uang-Chang Lu, Seng-Wen Pong, Hao-Cheng Cheng	Efficient test and repair architectures for 3D TSV-based random access memories.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yu-Jie Fu, Guan-Lin Wu, Shao-Yi Chien	Real-time salient object detection engine for high definition videos.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Wenhui Zhao, Grantham K. H. Pang, Ngai Wong	Automatic adaptive multi-point moment matching for descriptor system model order reduction.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Jiann-Ching Guey	To 4G mobile communication and beyond.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Makiko Ito, Mitsuru Tomono, Yi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Yoshio Hirose	A novel processor design flow using processor description language applied to a vector coprocessor.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1		2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013	VLSI-DAT	2013	DBLP BibTeX RDF
1	Barry P. Linder, Eduard Cartier, S. Krishnan, Ernest Y. Wu	Improving and optimizing reliability in future technologies with high-κ dielectrics.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ching-Che Chung, Chang-Jun Li	A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Guo-An Jian, Jui-Sheng Lee, Kheng-Joo Tan, Peng-Sheng Chen, Jiun-In Guo	A real-time parallel scalable video encoder for multimedia streaming systems.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Caleb Y.-S. Cho, J. C. Wang, Lion Huang, Milo Weng, Yu-Fan Lin, Chia-Fu Lee, C. W. Lien, H. C. Feng, Tassa Yang, S. P. Liao, J. J. Wu, Yu-Der Chih, Sreedhar Natarajan	A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yi-Keng Hsieh, Hsieh-Hung Hsieh, Liang-Hung Lu	A wideband programmable-gain amplifier for 60GHz applications in 65nm CMOS.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng	Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ting-Wei Chiang, Chia-Hung Liu, Juinn-Dar Huang	Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Bo-Ting Yeh, Chun-Hung Yang, Kai-Cheung Juang, Chien-Hung Tsai	Sensorless dead-time exploration for digitally controlled switching converters.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ting-Zi Chen, Soon-Jyh Chang, Guan-Ying Huang	A successive approximation ADC with resistor-capacitor hybrid structure.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Diego Olego	Innovations in healthcare and semiconductor progress.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chin-Yu Lin, Yen-Chuan Huang, Tai-Cheng Lee	Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Kun-Chih Chen, Shu-Yen Lin, An-Yeu Wu	Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Mu-Hsuan Chuang, Yi-Hao Lo, Bo-Yi Wu, Yuan-Hao Huang	MIMO fingerprinting-based particle filter for mobile positioning systems.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng	Improve speed path identification with suspect path expressions.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen	Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Wen Chen 0016, Li-C. Wang, Jayanta Bhadra, Magdy S. Abadir	Novel test analysis to improve structural coverage - A commercial experiment.	VLSI-DAT	2013	DBLP DOI BibTeX RDF

Publications at "VLSI-DAT"( http://dblp.L3S.de/Venues/VLSI-DAT )