Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Raghavendra Kumar Sakali, P. Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Sk. Noor Mahammad |
Optimized Fault-Tolerant Adder Design Using Error Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(6), pp. 2350091:1-2350091:32, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Elham Esmaeili, Farshad Pesaran, Nabiollah Shiri |
A high-efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 51(6), pp. 2942-2965, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Erfan Abbasian, Maedeh Orouji, Sana Taghipour Anvari, Alireza Asadi, Ehsan Mahmoodi |
An ultra-low power and energy-efficient ternary Half-Adder based on unary operators and two ternary 3:1 multiplexers in 32-nm GNRFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 51(10), pp. 4969-4983, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Puli Raju, Vallabhuni Vijay, P. Ashok Babu, P. Sridhar |
State of the art design of adder modules: performance validation of GDI methodology for energy harvesting applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Syst. Assur. Eng. Manag. ![In: Int. J. Syst. Assur. Eng. Manag. 14(6), pp. 2176-2186, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Asma Iqbal, Syed Affan Daimi, Kamsali Manjunatha Chari |
Performance Efficient and Fault Tolerant Approximate Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 39(5), pp. 571-582, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Raghavendra Kumar Sakali, Sk. Noor Mahammad |
Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 39(1), pp. 111-122, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | K. Gavaskar, D. Malathi, G. Ravivarma, P. S. Priyatharshan, S. Rajeshwari, B. Sanjay |
Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 128(2), pp. 1417-1435, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Ayush Kanojia, Sachin Agrawal, Rohit Lorenzo |
Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 129(2), pp. 1097-1111, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Anum Khan, Arindom Chakraborty, Upal Barua Joy, Subodh Wairya, Mehedi Hasan |
Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 140, pp. 105949, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Elahe Baratalipour, Arezoo Kamran |
SAMA: Self-adjusting multi-cycle approximate adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 134, pp. 105740, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Seyedeh Fatemeh Deymad, Nabiollah Shiri, Farshad Pesaran |
High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 142, pp. 105972, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Khac-Hoang Ngo, Alexandre Graell i Amat, Giuseppe Durisi |
Irregular Repetition Slotted ALOHA Over the Binary Adder Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.11720, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay |
A Higher Radix Architecture for Quantum Carry-lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.02921, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Behrouz Safaiezadeh, Majid Haghparast, Lauri Kettunen |
Novel Efficient Scalable QCA XOR and Full Adder Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.13946, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | William Lu, Anuran Makur |
Permutation Capacity Region of Adder Multiple-Access Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2309.08054, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Junpeng Zhan |
Quantum Multiplier Based on Exponent Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2309.10204, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | József Balogh, The Nguyen, Patric R. J. Östergård, Ethan Patrick White, Michael C. Wigal |
Improving Uniquely Decodable Codes in Binary Adder Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2312.11723, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Mohammad Mosleh, Ali Newaz Bahar, Senay Yalçin |
A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nano Commun. Networks ![In: Nano Commun. Networks 36, pp. 100442, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | B. Annapoorani, P. Marikkannu |
Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Syst. Sci. Eng. ![In: Comput. Syst. Sci. Eng. 45(3), pp. 2659-2672, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Sangyeob Kim, Hoi-Jun Yoo |
C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4), pp. 1026-1039, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Nikos Temenos, Paul P. Sotiriadis |
A Stochastic Computing Sigma-Delta Adder Architecture for Efficient Neural Network Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1), pp. 285-294, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Xuemei Fan, Tingting Zhang, Hao Liu 0013, Shengli Lu, Jie Han 0001 |
A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1), pp. 237-248, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Mateja Batelic, Mario Stipcevic |
Stochastic Adder Circuits with Improved Entropy Output. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Entropy ![In: Entropy 25(12), pp. 1592, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Tooba Arifeen, Saeid Gorgin 0001, MohammadHosein Gholamrezaei, Abdus Sami Hassan, Milos D. Ercegovac, Jeong-A Lee |
Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 95(7), pp. 815-829, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Gwanghwi Seo, Sungju Ryu |
Area-efficient AdderNet hardware accelerator with merged adder tree structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(23), pp. 20230427, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Pedro Tauã Lopes Pereira, Guilherme Paim, Paulo F. Flores, Eduardo A. C. da Costa, Sergio Bampi |
AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN-W ![In: 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2023 - Workshops, Porto, Portugal, June 27-30, 2023, pp. 183-186, 2023, IEEE, 979-8-3503-2543-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Farzad Mozafari, Majid Ahmadi, Arash Ahmadi |
Design and Implementation of Full Adder Circuit Based on VTM-Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 389-393, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | He Zhao, Xi Chen 0025, Bin Yu, Yuehai Wang |
Adder Neural Networks for Speaker Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCS ![In: 8th International Conference on Computer and Communication Systems, ICCCS 2023, Guangzhou, China, April 21-23, 2023, pp. 12-16, 2023, IEEE, 978-1-6654-5612-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Siyi Wang, Anupam Chattopadhyay |
Reducing Depth of Quantum Adder using Ling Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2599-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Khac-Hoang Ngo, Alexandre Graell i Amat, Giuseppe Durisi |
Irregular Repetition Slotted ALOHA Over the Binary Adder Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: IEEE International Conference on Communications, ICC 2023, Rome, Italy, May 28 - June 1, 2023, pp. 5346-5351, 2023, IEEE, 978-1-5386-7462-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | William Lu, Anuran Makur |
Permutation Sum-Capacity of Binary Adder Multiple-Access Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIT ![In: IEEE International Symposium on Information Theory, ISIT 2023, Taipei, Taiwan, June 25-30, 2023, pp. 933-938, 2023, IEEE, 978-1-6654-7554-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Rémi Garcia 0002, Anastasia Volkova |
Multiple Constant Multiplication: From Target Constants to Optimized Pipelined Adder Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023, pp. 137-143, 2023, IEEE, 979-8-3503-4151-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Tiago da Silva Almeida, Isaías B. Felzmann, Lucas Wanner 0001 |
Experimental analysis of the symmetry of approximate adder designs in FPGA and ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBESC ![In: XIII Brazilian Symposium on Computing Systems Engineering, SBESC 2023, Porto Alegre, Brazil, November 21-24, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-9410-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Rafael da Silva, Mateus Grellert, Ricardo Reis 0001 |
An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-1834-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Rawan Mohammed, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan |
CNTFET-based Approximate Ternary Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Morgana M. A. da Rosa, Eduardo Costa 0001, Rafael Soares, Sergio Bampi |
Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Rodrigo Lopes, Leonardo Antonietti, Morgana M. A. da Rosa, Eduardo Costa 0001, Rafael Soares, Sergio Bampi |
New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Zhouchao Gan, Dongdong Zhang, Yinghao Ma, Chenyu Zhang, Xiangshui Miao, Xingsheng Wang |
Invited Paper: A Memristor-Based Stateful Majority-Inverter Graph Logic and 1-Bit Full Adder for In-Memory Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023, Hefei, China, October 27-29, 2023, pp. 95-98, 2023, IEEE, 979-8-3503-4428-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Parisa Rahimi, Myasar R. Tabany, Seyedali Pourmoafi |
A Novel Low Power and High Speed 9- Transistors Dynamic Full-Adder Cell Simulation and Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: IEEE Symposium on Computers and Communications, ISCC 2023, Gammarth, Tunisia, July 9-12, 2023, pp. 1287-1292, 2023, IEEE, 979-8-3503-0048-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Junyu Jiang |
Optimized Gate Sizing for Improved Performance and Power Efficiency in Adder Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICITEE ![In: Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering, ICITEE 2023, Changde, Hunan, China, November 3-5, 2023, pp. 74-78, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Yaroslav Nykolaychuk, Volodymyr Hryha, Nataliia Vozna, Ihor Pitukh, Lyudmila Hryha |
High-performance multi-bit adder-accumulators as components of the ALU in supercomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IntelITSIS ![In: Proceedings of the 4th International Workshop on Intelligent Information Technologies & Systems of Information Security, Khmelnytskyi, Ukraine, March 22-24, 2023., pp. 649-661, 2023, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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13 | Fabian Seiler, Nima TaheriNejad |
An IMPLY-based Semi-Serial Approximate In-Memristor Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NorCAS ![In: IEEE Nordic Circuits and Systems Conference, NorCAS 2023, Aalborg, Denmark, October 31 - Nov. 1, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-3757-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Ning Zhang, Shuo Ni, Tingting Qiao, Wenchao Liu 0001, He Chen |
An Extremely Pipelined FPGA-based accelerator of All Adder Neural Networks for On-board Remote Sensing Scene Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFPT ![In: International Conference on Field Programmable Technology, ICFPT 2023, Yokohama, Japan, December 12-14, 2023, pp. 258-261, 2023, IEEE, 979-8-3503-5911-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Hyochan An, Yu Chen 0070, Zichen Fan, Qirui Zhang 0001, Pierre Abillama, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester |
An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 422-423, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal |
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023, pp. 125-130, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Mengfan Xu, Yuejun Zhang, Huihong Zhang, Liang Wen, Tengfei Yuan, Pengjun Wang, Zhiyi Li |
Full-custom Design of Improved Carry Adder Circuit for CLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran |
Approximate Three-Operand Binary Adder for Error-Resilient Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2023, Ahmedabad, India, December 18-20, 2023, pp. 287-291, 2023, IEEE, 979-8-3503-8324-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Shilpa Sikdar, Trilochan Panigrahi |
Low Power and Area-Efficient Hybrid Adder for ALU Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2023, Ahmedabad, India, December 18-20, 2023, pp. 310-314, 2023, IEEE, 979-8-3503-8324-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Poh Yuin Lyn, Nor Azlin Ghazali, Mohamed Fauzi Packeer Mohamed, Muhammad Firdaus Akbar |
Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
RoViSP ![In: Proceedings of the 12th International Conference on Robotics, Vision, Signal Processing and Power Applications, RoViSP 2023, Penang, Malaysia, 28-29 August 2023., pp. 141-147, 2023, Springer, 978-981-99-9004-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | B. Ravi Kumar, P. Munaswamy, B. Chandrababu Naik, K. Swetha |
Implementation of Low Power and High Speed Dadda Multiplier using Xor-Xnor cell Based Hybrid Logic Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | S. Nagaleela, G. Shanthi, Boppa Manisha, Palle Bharath, Erram Praneeth |
Design of DADDA Multiplier Using High Performance and Low Power Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | M. Rajmohan, N. Venkata Subbaiah, P. Sanath Kumar Reddy |
Performance analysis of 8×8 Truncated Multiplier using 1-bit Hybrid Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Jianbang Ding, Suiyun Zhang, Linlin Li |
Adder Encoder for Pre-trained Language Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCL ![In: Chinese Computational Linguistics - 22nd China National Conference, CCL 2023, Harbin, China, August 3-5, 2023, Proceedings, pp. 339-347, 2023, Springer, 978-981-99-6206-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Naheem Olakunle Adesina, Md Azmot Ullah Khan, Jian Xu |
Design of Energy Efficient Ring Oscillator and Full Adder Circuit using Compact Model of MoS2 Channel TFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCWC ![In: 13th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2023, Las Vegas, NV, USA, March 8-11, 2023, pp. 907-914, 2023, IEEE, 979-8-3503-3286-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Sadhu Sai Ram, Kuruvilla Varghese |
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 343-347, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Yixuan Hu, Tengyu Zhang, Meng Li 0004, Renjie Wei, Liangzhen Lai, Yuan Wang 0001, Runsheng Wang, Ru Huang |
Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Hao Qiu, Takayasu Sakurai, Makoto Takamiya |
A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(8), pp. 2390-2403, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Keivan Saadi, Alireza Kashaninia, Reza Sabbaghi-Nadooshan |
All-optical half adder based on triangular lattice photonic crystals with uniform structural parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 43(3), pp. 204-211, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Saeid Seyedi, Nima Jafari Navimipour |
Designing a multi-layer full-adder using a new three-input majority gate based on quantum computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 34(4), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Yuan Gao, Bayan Omar Mohammed |
A new applicable and multilayer design of nanoscale adder-subtractor using quantum-dots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 34(21), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Mahsa Tahghigh |
An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 23(6), pp. 950-965, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Mahmood Rafiee, Nabiollah Shiri, Ayoub Sadeghi |
High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 14(1), pp. 47-50, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ali Ghorbani, Mehdi Dolatshahi, Sayed Mohammad Ali Zanjani, Behrang Barekatain |
A new low-power Dynamic-GDI full adder in CNFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 83, pp. 46-59, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | A. Arunkumar Gudivada, Gnanou Florence Sudha |
Novel optimized low power design of single-precision floating-point adder using Quantum-dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 78(4), pp. 6035-6053, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Ali H. Majeed, Esam Alkaldy |
High-performance adder using a new XOR gate in QCA technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 78(9), pp. 11564-11579, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Bianca Silveira, Guilherme Paim, Brunno Alves Abreu, Rafael dos Santos Ferreira, Cláudio Machado Diniz, Eduardo Antônio César da Costa, Sergio Bampi |
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 41(3), pp. 1577-1595, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Sandeep Dhariwal, Reeba Korah, Ravi Shankar Mishra, Gaurav Kumar |
Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Perform. Eng. ![In: Int. J. Perform. Eng. 18(1), pp. 22, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Shahbaz Hussain, Mehedi Hasan, Gazal Agrawal, Mohd. Hasan |
A high-performance full swing 1-bit hybrid full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 16(3), pp. 210-217, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Saeid Seyedi, Behrouz Pourghebleh, Nima Jafari Navimipour |
A new coplanar design of a 4-bit ripple carry adder based on quantum-dot cellular automata technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 16(1), pp. 64-70, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour |
Tolerant and low power subtractor with 4: 2 compressor and a new TG-PTL-float full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 16(6), pp. 437-460, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Pratiksha Shukla, Pramod Kumar, Prasanna Kumar Misra |
An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(11), pp. 4548-4552, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Shaowei Wang, Guangjun Xie, Xin Cheng 0001, Yongqiang Zhang 0006 |
Weighted-Adder-Based Polynomial Computation Using Correlated Unipolar Stochastic Bitstreams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(11), pp. 4528-4532, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Nikos Temenos, Paul P. Sotiriadis |
Modeling a Stochastic Computing Nonscaling Adder and its Application in Image Sharpening. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(5), pp. 2543-2547, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa |
Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 101, pp. 107999, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Raju Ganna, Shanky Saxena, Govind Singh Patel |
Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(17), pp. 2250292:1-2250292:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Naeem Maroof, Ali Y. Al-Zahrani |
A Double Bit Approximate Adder Providing a New Design Perspective for Gate-Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(4), pp. 2250065:1-2250065:21, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001 |
Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(18), pp. 2292001:1-2292001:2, December 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat |
Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(8), pp. 2250146:1-2250146:15, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001 |
High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(11), pp. 2250200:1-2250200:16, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Uppugunduru Anil Kumar, G. Sahith, Sumit K. Chatterjee, Syed Ershad Ahmed |
A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(3), pp. 2250049:1-2250049:17, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu 0001 |
High-Speed Adder Design Space Exploration via Graph Neural Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8), pp. 2657-2670, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Mi Lin, Qi Han, Wenyao Luo, Xuliang Wang, Junjie Chen, Weifeng Lyu |
A ternary memristor full adder based on literal operation and module operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(8), pp. 2932-2940, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Kancharla Vijaya Vardhan, Sarada Musala |
Ultra-Low-Power Modulo Adder with Thermometer Coding for Uncertain RNS Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Uncertain Syst. ![In: J. Uncertain Syst. 15(3), pp. 2241011:1-2241011:20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Muhammad Ali Akbar, Bo Wang 0012, Amine Bermak |
Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Open J. Circuits Syst. ![In: IEEE Open J. Circuits Syst. 3, pp. 50-58, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | K. Praghash, S. Arun Metha, B. Sai Tanuja, K. Preethi, N. P. N. S. Chandana |
Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 126(4), pp. 3041-3069, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Samuel H. Florin, Matthew H. Ho, Zilin Jiang |
On the Binary Adder Channel With Complete Feedback, With an Application to Quantitative Group Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 68(5), pp. 2839-2856, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian |
A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 18(4), pp. 74:1-74:20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | S. Aathilakshmi, R. Vimala, K. R. Aravind Britto |
Design of M-tree Adder using majority logic for removal of artifacts in bio signal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 123, pp. 104901, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Guodong Yin, Mufeng Zhou, Yiming Chen, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li |
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2212.04320, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal |
A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2203.09665, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Omar Fawzi, Paul Fermé |
Beating the Sum-Rate Capacity of the Binary Adder Channel with Non-Signaling Correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.10968, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Gökberk Erdogan, Georg Maringer, Nikita Polyanskii |
Signature Codes for a Noisy Adder Multiple Access Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.10735, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Mohammad Mosleh, Ali Newaz Bahar, Jadav Chandra Das, Debashis De, Senay Yalçin |
An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nano Commun. Networks ![In: Nano Commun. Networks 34, pp. 100412, December 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Tomoyuki Tanaka, Christopher L. Ayala, Nobuyuki Yoshikawa |
A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 105-C(6), pp. 270-276, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Marshal Raj, Raja Sekar Kumaresan, G. Lakshminarayanan |
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 39(5), pp. 88-97, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Sebastian Renner, Enrico Pozzobon, Jürgen Mottok |
Evolving a Boolean Masked Adder Using Neuroevolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADIoT ![In: Attacks and Defenses for the Internet-of-Things - 5th International Workshop, ADIoT 2022, Copenhagen, Denmark, September 30, 2022, Revised Selected Papers, pp. 21-40, 2022, Springer, 978-3-031-21310-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Oguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij |
Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 126-133, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Behnam Ghavami, Mahdi Sajedi, Mohsen Raji, Zhenman Fang, Lesley Shannon |
A Majority-based Approximate Adder for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 53-59, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Ashish Reddy Bommana, Srinivas Boppu |
A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022, pp. 305-312, 2022, IEEE, 978-1-6654-6499-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad Ali Akbar, Bo Wang 0012, Amine Bermak |
Evaluating the Optimal Self-Checking Carry Propagate Adder for Cryptographic Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022, pp. 10-13, 2022, IEEE, 978-1-6654-6499-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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