Search results for "adder"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Raghavendra Kumar Sakali, P. Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Sk. Noor Mahammad	Optimized Fault-Tolerant Adder Design Using Error Analysis.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
13	Elham Esmaeili, Farshad Pesaran, Nabiollah Shiri	A high-efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
13	Erfan Abbasian, Maedeh Orouji, Sana Taghipour Anvari, Alireza Asadi, Ehsan Mahmoodi	An ultra-low power and energy-efficient ternary Half-Adder based on unary operators and two ternary 3:1 multiplexers in 32-nm GNRFET technology.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
13	Puli Raju, Vallabhuni Vijay, P. Ashok Babu, P. Sridhar	State of the art design of adder modules: performance validation of GDI methodology for energy harvesting applications.	Int. J. Syst. Assur. Eng. Manag.	2023	DBLP DOI BibTeX RDF
13	Asma Iqbal, Syed Affan Daimi, Kamsali Manjunatha Chari	Performance Efficient and Fault Tolerant Approximate Adder.	J. Electron. Test.	2023	DBLP DOI BibTeX RDF
13	Raghavendra Kumar Sakali, Sk. Noor Mahammad	Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm.	J. Electron. Test.	2023	DBLP DOI BibTeX RDF
13	K. Gavaskar, D. Malathi, G. Ravivarma, P. S. Priyatharshan, S. Rajeshwari, B. Sanjay	Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
13	Ayush Kanojia, Sachin Agrawal, Rohit Lorenzo	Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
13	Anum Khan, Arindom Chakraborty, Upal Barua Joy, Subodh Wairya, Mehedi Hasan	Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Elahe Baratalipour, Arezoo Kamran	SAMA: Self-adjusting multi-cycle approximate adder.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Seyedeh Fatemeh Deymad, Nabiollah Shiri, Farshad Pesaran	High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Khac-Hoang Ngo, Alexandre Graell i Amat, Giuseppe Durisi	Irregular Repetition Slotted ALOHA Over the Binary Adder Channel.	CoRR	2023	DBLP DOI BibTeX RDF
13	Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay	A Higher Radix Architecture for Quantum Carry-lookahead Adder.	CoRR	2023	DBLP DOI BibTeX RDF
13	Behrouz Safaiezadeh, Majid Haghparast, Lauri Kettunen	Novel Efficient Scalable QCA XOR and Full Adder Designs.	CoRR	2023	DBLP DOI BibTeX RDF
13	William Lu, Anuran Makur	Permutation Capacity Region of Adder Multiple-Access Channels.	CoRR	2023	DBLP DOI BibTeX RDF
13	Junpeng Zhan	Quantum Multiplier Based on Exponent Adder.	CoRR	2023	DBLP DOI BibTeX RDF
13	József Balogh, The Nguyen, Patric R. J. Östergård, Ethan Patrick White, Michael C. Wigal	Improving Uniquely Decodable Codes in Binary Adder Channels.	CoRR	2023	DBLP DOI BibTeX RDF
13	Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Mohammad Mosleh, Ali Newaz Bahar, Senay Yalçin	A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation.	Nano Commun. Networks	2023	DBLP DOI BibTeX RDF
13	B. Annapoorani, P. Marikkannu	Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder.	Comput. Syst. Sci. Eng.	2023	DBLP DOI BibTeX RDF
13	Sangyeob Kim, Hoi-Jun Yoo	C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2023	DBLP DOI BibTeX RDF
13	Nikos Temenos, Paul P. Sotiriadis	A Stochastic Computing Sigma-Delta Adder Architecture for Efficient Neural Network Design.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2023	DBLP DOI BibTeX RDF
13	Xuemei Fan, Tingting Zhang, Hao Liu 0013, Shengli Lu, Jie Han 0001	A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2023	DBLP DOI BibTeX RDF
13	Mateja Batelic, Mario Stipcevic	Stochastic Adder Circuits with Improved Entropy Output.	Entropy	2023	DBLP DOI BibTeX RDF
13	Tooba Arifeen, Saeid Gorgin 0001, MohammadHosein Gholamrezaei, Abdus Sami Hassan, Milos D. Ercegovac, Jeong-A Lee	Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product.	J. Signal Process. Syst.	2023	DBLP DOI BibTeX RDF
13	Gwanghwi Seo, Sungju Ryu	Area-efficient AdderNet hardware accelerator with merged adder tree structure.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
13	Pedro Tauã Lopes Pereira, Guilherme Paim, Paulo F. Flores, Eduardo A. C. da Costa, Sergio Bampi	AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation.	DSN-W	2023	DBLP DOI BibTeX RDF
13	Farzad Mozafari, Majid Ahmadi, Arash Ahmadi	Design and Implementation of Full Adder Circuit Based on VTM-Logic Gates.	MWSCAS	2023	DBLP DOI BibTeX RDF
13	He Zhao, Xi Chen 0025, Bin Yu, Yuehai Wang	Adder Neural Networks for Speaker Verification.	ICCCS	2023	DBLP DOI BibTeX RDF
13	Siyi Wang, Anupam Chattopadhyay	Reducing Depth of Quantum Adder using Ling Structure.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
13	Khac-Hoang Ngo, Alexandre Graell i Amat, Giuseppe Durisi	Irregular Repetition Slotted ALOHA Over the Binary Adder Channel.	ICC	2023	DBLP DOI BibTeX RDF
13	William Lu, Anuran Makur	Permutation Sum-Capacity of Binary Adder Multiple-Access Channels.	ISIT	2023	DBLP DOI BibTeX RDF
13	Rémi Garcia 0002, Anastasia Volkova	Multiple Constant Multiplication: From Target Constants to Optimized Pipelined Adder Graphs.	FPL	2023	DBLP DOI BibTeX RDF
13	Tiago da Silva Almeida, Isaías B. Felzmann, Lucas Wanner 0001	Experimental analysis of the symmetry of approximate adder designs in FPGA and ASIC.	SBESC	2023	DBLP DOI BibTeX RDF
13	Rafael da Silva, Mateus Grellert, Ricardo Reis 0001	An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder.	SBCCI	2023	DBLP DOI BibTeX RDF
13	Rawan Mohammed, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan	CNTFET-based Approximate Ternary Adder Design.	ICECS	2023	DBLP DOI BibTeX RDF
13	Morgana M. A. da Rosa, Eduardo Costa 0001, Rafael Soares, Sergio Bampi	Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder.	ICECS	2023	DBLP DOI BibTeX RDF
13	Rodrigo Lopes, Leonardo Antonietti, Morgana M. A. da Rosa, Eduardo Costa 0001, Rafael Soares, Sergio Bampi	New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies.	ICECS	2023	DBLP DOI BibTeX RDF
13	Zhouchao Gan, Dongdong Zhang, Yinghao Ma, Chenyu Zhang, Xiangshui Miao, Xingsheng Wang	Invited Paper: A Memristor-Based Stateful Majority-Inverter Graph Logic and 1-Bit Full Adder for In-Memory Computing Systems.	ICTA	2023	DBLP DOI BibTeX RDF
13	Parisa Rahimi, Myasar R. Tabany, Seyedali Pourmoafi	A Novel Low Power and High Speed 9- Transistors Dynamic Full-Adder Cell Simulation and Design.	ISCC	2023	DBLP DOI BibTeX RDF
13	Junyu Jiang	Optimized Gate Sizing for Improved Performance and Power Efficiency in Adder Circuits.	ICITEE	2023	DBLP DOI BibTeX RDF
13	Yaroslav Nykolaychuk, Volodymyr Hryha, Nataliia Vozna, Ihor Pitukh, Lyudmila Hryha	High-performance multi-bit adder-accumulators as components of the ALU in supercomputers.	IntelITSIS	2023	DBLP BibTeX RDF
13	Fabian Seiler, Nima TaheriNejad	An IMPLY-based Semi-Serial Approximate In-Memristor Adder.	NorCAS	2023	DBLP DOI BibTeX RDF
13	Ning Zhang, Shuo Ni, Tingting Qiao, Wenchao Liu 0001, He Chen	An Extremely Pipelined FPGA-based accelerator of All Adder Neural Networks for On-board Remote Sensing Scene Classification.	ICFPT	2023	DBLP DOI BibTeX RDF
13	Hyochan An, Yu Chen 0070, Zichen Fan, Qirui Zhang 0001, Pierre Abillama, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester	An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal	A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
13	Mengfan Xu, Yuejun Zhang, Huihong Zhang, Liang Wen, Tengfei Yuan, Pengjun Wang, Zhiyi Li	Full-custom Design of Improved Carry Adder Circuit for CLBs.	ASICON	2023	DBLP DOI BibTeX RDF
13	Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran	Approximate Three-Operand Binary Adder for Error-Resilient Applications.	iSES	2023	DBLP DOI BibTeX RDF
13	Shilpa Sikdar, Trilochan Panigrahi	Low Power and Area-Efficient Hybrid Adder for ALU Operation.	iSES	2023	DBLP DOI BibTeX RDF
13	Poh Yuin Lyn, Nor Azlin Ghazali, Mohamed Fauzi Packeer Mohamed, Muhammad Firdaus Akbar	Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC).	RoViSP	2023	DBLP DOI BibTeX RDF
13	B. Ravi Kumar, P. Munaswamy, B. Chandrababu Naik, K. Swetha	Implementation of Low Power and High Speed Dadda Multiplier using Xor-Xnor cell Based Hybrid Logic Full Adder.	ICCCNT	2023	DBLP DOI BibTeX RDF
13	S. Nagaleela, G. Shanthi, Boppa Manisha, Palle Bharath, Erram Praneeth	Design of DADDA Multiplier Using High Performance and Low Power Full Adder.	ICCCNT	2023	DBLP DOI BibTeX RDF
13	M. Rajmohan, N. Venkata Subbaiah, P. Sanath Kumar Reddy	Performance analysis of 8×8 Truncated Multiplier using 1-bit Hybrid Full Adder.	ICCCNT	2023	DBLP DOI BibTeX RDF
13	Jianbang Ding, Suiyun Zhang, Linlin Li	Adder Encoder for Pre-trained Language Model.	CCL	2023	DBLP DOI BibTeX RDF
13	Naheem Olakunle Adesina, Md Azmot Ullah Khan, Jian Xu	Design of Energy Efficient Ring Oscillator and Full Adder Circuit using Compact Model of MoS2 Channel TFET.	CCWC	2023	DBLP DOI BibTeX RDF
13	Sadhu Sai Ram, Kuruvilla Varghese	Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder.	APCCAS	2023	DBLP DOI BibTeX RDF
13	Yixuan Hu, Tengyu Zhang, Meng Li 0004, Renjie Wei, Liangzhen Lai, Yuan Wang 0001, Runsheng Wang, Ru Huang	Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network.	DAC	2023	DBLP DOI BibTeX RDF
13	Hao Qiu, Takayasu Sakurai, Makoto Takamiya	A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
13	Keivan Saadi, Alireza Kashaninia, Reza Sabbaghi-Nadooshan	All-optical half adder based on triangular lattice photonic crystals with uniform structural parameters.	Photonic Netw. Commun.	2022	DBLP DOI BibTeX RDF
13	Saeid Seyedi, Nima Jafari Navimipour	Designing a multi-layer full-adder using a new three-input majority gate based on quantum computing.	Concurr. Comput. Pract. Exp.	2022	DBLP DOI BibTeX RDF
13	Yuan Gao, Bayan Omar Mohammed	A new applicable and multilayer design of nanoscale adder-subtractor using quantum-dots.	Concurr. Comput. Pract. Exp.	2022	DBLP DOI BibTeX RDF
13	Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Mahsa Tahghigh	An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending.	Frontiers Inf. Technol. Electron. Eng.	2022	DBLP DOI BibTeX RDF
13	Mahmood Rafiee, Nabiollah Shiri, Ayoub Sadeghi	High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures.	IEEE Embed. Syst. Lett.	2022	DBLP DOI BibTeX RDF
13	Ali Ghorbani, Mehdi Dolatshahi, Sayed Mohammad Ali Zanjani, Behrang Barekatain	A new low-power Dynamic-GDI full adder in CNFET technology.	Integr.	2022	DBLP DOI BibTeX RDF
13	A. Arunkumar Gudivada, Gnanou Florence Sudha	Novel optimized low power design of single-precision floating-point adder using Quantum-dot Cellular Automata.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
13	Ali H. Majeed, Esam Alkaldy	High-performance adder using a new XOR gate in QCA technology.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
13	Bianca Silveira, Guilherme Paim, Brunno Alves Abreu, Rafael dos Santos Ferreira, Cláudio Machado Diniz, Eduardo Antônio César da Costa, Sergio Bampi	The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
13	Sandeep Dhariwal, Reeba Korah, Ravi Shankar Mishra, Gaurav Kumar	Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications.	Int. J. Perform. Eng.	2022	DBLP DOI BibTeX RDF
13	Shahbaz Hussain, Mehedi Hasan, Gazal Agrawal, Mohd. Hasan	A high-performance full swing 1-bit hybrid full adder cell.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
13	Saeid Seyedi, Behrouz Pourghebleh, Nima Jafari Navimipour	A new coplanar design of a 4-bit ripple carry adder based on quantum-dot cellular automata technology.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
13	Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour	Tolerant and low power subtractor with 4: 2 compressor and a new TG-PTL-float full adder cell.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
13	Pratiksha Shukla, Pramod Kumar, Prasanna Kumar Misra	An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
13	Shaowei Wang, Guangjun Xie, Xin Cheng 0001, Yongqiang Zhang 0006	Weighted-Adder-Based Polynomial Computation Using Correlated Unipolar Stochastic Bitstreams.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
13	Nikos Temenos, Paul P. Sotiriadis	Modeling a Stochastic Computing Nonscaling Adder and its Application in Image Sharpening.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
13	Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa	Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
13	Raju Ganna, Shanky Saxena, Govind Singh Patel	Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Naeem Maroof, Ali Y. Al-Zahrani	A Double Bit Approximate Adder Providing a New Design Perspective for Gate-Level Design.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001	Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat	Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001	High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Uppugunduru Anil Kumar, G. Sahith, Sumit K. Chatterjee, Syed Ershad Ahmed	A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu 0001	High-Speed Adder Design Space Exploration via Graph Neural Processes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
13	Mi Lin, Qi Han, Wenyao Luo, Xuliang Wang, Junjie Chen, Weifeng Lyu	A ternary memristor full adder based on literal operation and module operation.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
13	Kancharla Vijaya Vardhan, Sarada Musala	Ultra-Low-Power Modulo Adder with Thermometer Coding for Uncertain RNS Applications.	J. Uncertain Syst.	2022	DBLP DOI BibTeX RDF
13	Muhammad Ali Akbar, Bo Wang 0012, Amine Bermak	Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration.	IEEE Open J. Circuits Syst.	2022	DBLP DOI BibTeX RDF
13	K. Praghash, S. Arun Metha, B. Sai Tanuja, K. Preethi, N. P. N. S. Chandana	Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
13	Samuel H. Florin, Matthew H. Ho, Zilin Jiang	On the Binary Adder Channel With Complete Feedback, With an Application to Quantitative Group Testing.	IEEE Trans. Inf. Theory	2022	DBLP DOI BibTeX RDF
13	Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian	A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology.	ACM J. Emerg. Technol. Comput. Syst.	2022	DBLP DOI BibTeX RDF
13	S. Aathilakshmi, R. Vimala, K. R. Aravind Britto	Design of M-tree Adder using majority logic for removal of artifacts in bio signal.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
13	Guodong Yin, Mufeng Zhou, Yiming Chen, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li	A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface.	CoRR	2022	DBLP DOI BibTeX RDF
13	Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal	A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design.	CoRR	2022	DBLP DOI BibTeX RDF
13	Omar Fawzi, Paul Fermé	Beating the Sum-Rate Capacity of the Binary Adder Channel with Non-Signaling Correlations.	CoRR	2022	DBLP DOI BibTeX RDF
13	Gökberk Erdogan, Georg Maringer, Nikita Polyanskii	Signature Codes for a Noisy Adder Multiple Access Channel.	CoRR	2022	DBLP DOI BibTeX RDF
13	Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Mohammad Mosleh, Ali Newaz Bahar, Jadav Chandra Das, Debashis De, Senay Yalçin	An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform.	Nano Commun. Networks	2022	DBLP DOI BibTeX RDF
13	Tomoyuki Tanaka, Christopher L. Ayala, Nobuyuki Yoshikawa	A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
13	Marshal Raj, Raja Sekar Kumaresan, G. Lakshminarayanan	Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF
13	Sebastian Renner, Enrico Pozzobon, Jürgen Mottok	Evolving a Boolean Masked Adder Using Neuroevolution.	ADIoT	2022	DBLP DOI BibTeX RDF
13	Oguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating.	DSD	2022	DBLP DOI BibTeX RDF
13	Behnam Ghavami, Mahdi Sajedi, Mohsen Raji, Zhenman Fang, Lesley Shannon	A Majority-based Approximate Adder for FPGAs.	DSD	2022	DBLP DOI BibTeX RDF
13	Ashish Reddy Bommana, Srinivas Boppu	A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization.	MCSoC	2022	DBLP DOI BibTeX RDF
13	Muhammad Ali Akbar, Bo Wang 0012, Amine Bermak	Evaluating the Optimal Self-Checking Carry Propagate Adder for Cryptographic Processor.	MCSoC	2022	DBLP DOI BibTeX RDF