Search results for "designs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Sumit Gupta, Nikil D. Dutt, Rajesh Gupta 0001, Alexandru Nicolau	Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow.	DATE	2004	DBLP DOI BibTeX RDF
14	Jifeng He 0001, Zhiming Liu 0001, Xiaoshan Li, Shengchao Qin	A Relational Model for Object-Oriented Designs.	APLAS	2004	DBLP DOI BibTeX RDF	UTP, Semantics, Object Orientation, Refinement
14	Raymond A. Heald, Ping Wang	Variability in sub-100nm SRAM designs.	ICCAD	2004	DBLP DOI BibTeX RDF
14	Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu	Architecting voltage islands in core-based system-on-a-chip designs.	ISLPED	2004	DBLP DOI BibTeX RDF	multiple VDD, low-power, floorplanning, system-on-a-chip, voltage island
14	Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu	Extending the Applicability of Parallel-Serial Scan Designs.	ICCD	2004	DBLP DOI BibTeX RDF
14	Masahiro Fujita	Formal Verification of C Language Based VLSI Designs.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Han-Yu Chuang, Huai-Kuang Tsai, Cheng-Yan Kao	Optimal Designs for Microarray Experiments.	ISPAN	2004	DBLP DOI BibTeX RDF
14	Sangyoon Lee, Tian Chen, Jongseo Kim, Sungho Han, Zhigeng Pan, Gerard Jounghyun Kim	Affective Property Evaluation of Virtual Product Designs.	VR	2004	DBLP DOI BibTeX RDF
14	Jon-Lark Kim, Vera Pless	Designs in Additive Codes over GF(4).	Des. Codes Cryptogr.	2003	DBLP DOI BibTeX RDF	additive code, Assmus-Mattson theorem, generalized t-design
14	Thomas Beth, Chris Charnes, Markus Grassl, Gernot Alber, Aldo Delgado, Michael Mussinger	A New Class of Designs Which Protect against Quantum Jumps.	Des. Codes Cryptogr.	2003	DBLP DOI BibTeX RDF
14	Kenichiro Tanabe	A Criterion for Designs in {\tf="P101461" Z}_4-codes on the Symmetrized Weight Enumerator.	Des. Codes Cryptogr.	2003	DBLP DOI BibTeX RDF	Z 4-codes, Assmus-Mattson theorem, harmonic weight, enumerator
14	Nguyen Truong Thang, Takuya Katayama	Towards a Sound Modular Model Checking of Collaboration-Based Software Designs.	APSEC	2003	DBLP DOI BibTeX RDF
14	Yu-Chiun Lin, Shi-Yu Huang	Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
14	Mark Ratcliffe 0001, Lynda Thomas, Wayne Ellis, Benjy J. Thomasson	Capturing collaborative designs to assist the pedagogical process.	ITiCSE	2003	DBLP DOI BibTeX RDF	design capture, learning to program, pedagogy
14	Russell C. H. Cheng, Owen D. Jones	Issues on simulation and optimization II: robust hybrid designs for real-time simulation trials.	WSC	2003	DBLP DOI BibTeX RDF
14	James Lin	Design technology challenges for system and chip level designs in very deep submicron technologies.	CODES+ISSS	2003	DBLP DOI BibTeX RDF
14	Gregory Hornby	Generative Representations for Evolving Families of Designs.	GECCO	2003	DBLP DOI BibTeX RDF
14	William H. Kao, Wenkung K. Chu	Noise constraint driven placement for mixed signal designs.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
14	Ishtiaq Rasool Khan, Masahiro Okuda, Ryoji Ohba	New designs of frequency selective FIR digital filters.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
14	Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu 0001	Zero overhead watermarking technique for FPGA designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	configuration bitstream, timing analyzer, user constraint file, zero overhead, performance, FPGA, place and route, IP protection
14	Srivaths Ravi 0001, Anand Raghunathan, Srimat T. Chakradhar	Efficient RTL Power Estimation for Large Designs.	VLSI Design	2003	DBLP DOI BibTeX RDF
14	Laurence Goodby, Alex Orailoglu, Paul M. Chau	Microarchitectural synthesis of performance-constrained, low-power VLSI designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	DSP datapath design, High-level synthesis, low-power design
14	Amit R. Pandey, Janak H. Patel	An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs.	DATE	2002	DBLP DOI BibTeX RDF
14	Oswaldo Cadenas, Graham M. Megson	Improving mW/MHz Ratio in FPGAs Pipelined Designs.	DSD	2002	DBLP DOI BibTeX RDF
14	David Bruce Adams, Layne T. Watson, Zafer Gürdal	Blending of Composite Panel Designs Using Genetic Algorithms.	IPDPS	2002	DBLP DOI BibTeX RDF
14	Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy	Noise propagation and failure criteria for VLSI designs.	ICCAD	2002	DBLP DOI BibTeX RDF
14	Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama	Trends in Low Power Digital System-on-Chip Designs (invited).	ISQED	2002	DBLP DOI BibTeX RDF	Low-Power CMOS, Design, SoC, Digital
14	Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Chanhee Oh	Noise Injection and Propagation in High Performance Designs.	ISQED	2002	DBLP DOI BibTeX RDF
14	Yun Shao 0002, Irith Pomeranz, Sudhakar M. Reddy	Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
14	Lionel C. Briand, Yvan Labiche, G. Soccar	Automating Impact Analysis and Regression Test Selection Based on UML Designs.	ICSM	2002	DBLP DOI BibTeX RDF
14	Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee	Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB.	ASP-DAC	2001	DBLP DOI BibTeX RDF	MATLAB
14	Shi-Yu Huang	Towards the logic defect diagnosis for partial-scan designs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
14	Franz Wotawa	Using Multiple Models for Debugging VHDL Designs.	IEA/AIE	2001	DBLP DOI BibTeX RDF
14	Pauline C. Haddow, Piet van Remortel	From Here To There : Future Robust Ehw Technologies For Large Digital Designs.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
14	Yves Le Traon, Farid Ouabdesselam, Chantal Robach	Analyzing Testability on Data Flow Designs.	ISSRE	2000	DBLP DOI BibTeX RDF
14	Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara	Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs.	FMCAD	2000	DBLP DOI BibTeX RDF
14	Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi	Controller-based power management for control-flow intensive designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
14	Peter G. Boyvalenkov, Danyo Danev, Svetla Nikova	Nonexistence of Certain Spherical Designs of Odd Strengths and Cardinalities.	Discret. Comput. Geom.	1999	DBLP DOI BibTeX RDF
14	Nazanin Mansouri, Ranga Vemuri	Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs.	DATE	1999	DBLP DOI BibTeX RDF
14	Víctor A. Braberman, Miguel Felder	Verification of Real-Time Designs: Combining Scheduling Theory with Automatic Formal Verification.	ESEC / SIGSOFT FSE	1999	DBLP DOI BibTeX RDF
14	Klaus Schneider 0001, Michaela Huhn, George Logothetis	Validation of Object-Oriented Concurrent Designs by Model Checking.	CHARME	1999	DBLP DOI BibTeX RDF
14	Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang	Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs.	ARVLSI	1999	DBLP DOI BibTeX RDF
14	Svetla Nikova, Ventzislav Nikov	Some Applications of Bounds for Designs to the Cryptography.	IMACC	1999	DBLP DOI BibTeX RDF
14	HyungWon Kim 0001, John P. Hayes	Delay Fault Testing of Designs with Embedded IP Cores.	VTS	1999	DBLP DOI BibTeX RDF
14	Yiorgos Makris, Alex Orailoglu	RTL Test Justification and Propagation Analysis for Modular Designs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	RTL testability analysis, test justification, test propagation, DFT, modular design
14	Minako Sawaki, Norihiro Hagita	Text-Line Extraction and Character Recognition of Document Headlines With Graphical Designs Using Complementary Similarity Measure.	IEEE Trans. Pattern Anal. Mach. Intell.	1998	DBLP DOI BibTeX RDF	projection feature, displacement matching, OCR, Character recognition, adaptive thresholding, character segmentation
14	Wen-Jong Fang, Allen C.-H. Wu	Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
14	Udo Brockmeyer, Gunnar Wittich	Real-Time Verification of Statemate Designs.	CAV	1998	DBLP DOI BibTeX RDF
14	Yannis Smaragdakis, Don S. Batory	Implementing Layered Designs with Mixin Layers.	ECOOP	1998	DBLP DOI BibTeX RDF
14	Dirk Stroobandt, Fadi J. Kurdahi	On the Characterization of Multi-Point Nets in Electronic Designs.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Multi-point nets, Net degree distribution, Interconnection complexity, Rent's rule
14	Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung	Compilation tools for run-time reconfigurable designs.	FCCM	1997	DBLP DOI BibTeX RDF
14	Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal	Optimizing Designs Containing Black Boxes.	DAC	1997	DBLP DOI BibTeX RDF
14	Minako Sawaki, Norihiro Hagita, Kenichiro Ishii	Robust Character Recognition of Gray-Scaled Images with Graphical Designs and Noise.	ICDAR	1997	DBLP DOI BibTeX RDF
14	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
14	Nam Ling	A special purpose formal verifier for systolic designs in DSP applications.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
14	Morteza Saheb Zamani, Graham R. Hellestrand	A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs.	IWANN	1995	DBLP DOI BibTeX RDF
14	Jason Cong, Yuzheng Ding	FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
14	Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri	Estimating the Complexity of Synthesized Designs from FSM Specifications.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
14	Reiner Hähnle, Werner Kernig	Verification of Switch-Level Designs with Many-Valued Logic.	LPAR	1993	DBLP DOI BibTeX RDF
14	Peter G. Boyvalenkov, Svetla Nikova	New lower bounds for some spherical designs.	Algebraic Coding	1993	DBLP DOI BibTeX RDF
14	Niraj K. Jha	Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
14	Barbara Mirel	Usability and hardcopy manuals: evaluating research designs and methods.	SIGDOC	1990	DBLP DOI BibTeX RDF
14	Chang Nian Zhang, Behrooz A. Shirazi, David Y. Y. Yun	Computing multiple modulo summation (abstract only): a new algorithm, its VLSI designs and applications.	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
14	George S. Avrunin, Jack C. Wileden	Describing and Analyzing Distributed Software System Designs.	ACM Trans. Program. Lang. Syst.	1985	DBLP DOI BibTeX RDF	DYMOL
14	Andrew B. Kahng, Vijayalakshmi Srinivasan	Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis
14	Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	Reduced ATE Interface for High Test Data Compression.	ETS	2011	DBLP DOI BibTeX RDF	channel bandwidth management, embedded deterministic test, test interface, tri-modal compression, test data compression, scan-based designs
14	Jantima Polpinij, Aditya K. Ghose, Hoa Khanh Dam	Business Rules Discovery from Process Design Repositories.	SERVICES	2010	DBLP DOI BibTeX RDF	the Apriori Algorithm, Business Rules, Process Designs
14	B. K. Mishra 0001, Sandhya Save	Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance.	ICSAP	2010	DBLP DOI BibTeX RDF	Analog circuit designs methodologies, Analog design automation, Op-amps, AMS, Simulated Annealing, CAD, SoC, ASIC, SPICE, EDA tools
14	Marc D. Riedel, Soha Hassoun, Ron Weiss, Pamela Silver, J. Christopher Anderson, Richard M. Murray	Joint DAC/IWBDA special session engineering biology: fundamentals and applications.	DAC	2010	DBLP DOI BibTeX RDF	bio-design automation, biological circuits, cellular programming, robustness, control, feedback, computational biology, system biology, modular designs, synthetic biology
14	My T. Thai, Taieb Znati	On the complexity and approximation of non-unique probe selection using d -disjunct matrix.	J. Comb. Optim.	2009	DBLP DOI BibTeX RDF	Non-unique probe, Non-adaptive group testing, d-disjunct matrix, Pooling designs
14	Dingyi Pei	New Family of Non-Cartesian Perfect Authentication Codes.	IWCC	2009	DBLP DOI BibTeX RDF	perfect authentication codes, subfield rational normal curves, partially balanced designs, spoofing attacks
14	Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky	Speculation in elastic systems.	DAC	2009	DBLP DOI BibTeX RDF	elastic designs, protocols, synthesis, speculation
14	Hong-Bin Chen, Frank K. Hwang	A survey on nonadaptive group testing algorithms through the angle of decoding.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Nonadaptive algorithms, Group testing, Pooling designs
14	S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod	Bridge Defect Diagnosis for Multiple-Voltage Design.	ETS	2008	DBLP DOI BibTeX RDF	Logic based Diagnosis, Multiple-Vdd designs, Resistive Bridging Faults
14	Georgios Kalogridis, Chris J. Mitchell	Using Non-adaptive Group Testing to Construct Spy Agent Routes.	ARES	2008	DBLP DOI BibTeX RDF	spy agents, agent routes, decoy agents, group testing, pooling designs, trust evaluation
14	Chiara Di Francescomarino, Paolo Tonella	Crosscutting Concern Documentation by Visual Query of Business Processes.	Business Process Management Workshops	2008	DBLP DOI BibTeX RDF	Process design methods and methodologies, Maintenance of process designs
14	Josep Domingo-Ferrer, Maria Bras-Amorós	Peer-to-Peer Private Information Retrieval.	Privacy in Statistical Databases	2008	DBLP DOI BibTeX RDF	Privacy in statistical databases, private information retrieval, combinatorial designs
14	Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai	X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	on-chip collection of test data, selective compaction of test responses, fault diagnosis, DFT, embedded test, scan-based designs
14	C. A. Rodger, S. K. Westbrook	Decompositions of lambda K v .	J. Comb. Optim.	2007	DBLP DOI BibTeX RDF	Pairwise balanced designs, Graph decompositions
14	H. B. Chen, Ding-Zhu Du, Frank K. Hwang	An unexpected meeting of four seemingly unrelated problems: graph testing, DNA complex screening, superimposed codes and secure key distribution.	J. Comb. Optim.	2007	DBLP DOI BibTeX RDF	Graph testing, Group testing, Superimposed codes, Pooling designs
14	Gideon Avigad	multi-Multi-Objective Optimization Problem and Its Solution by a MOEA.	EMO	2007	DBLP DOI BibTeX RDF	Family of designs, Communality, Engineering design
14	Shekhar Borkar	Tackling variability and reliability challenges.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	transistor subthreshold leakage, reliability, variability, VLSI designs, technology scaling
14	Hong Gao 0001, Frank K. Hwang, My T. Thai, Weili Wu 0001, Taieb Znati	Construction of d(H)-disjunct matrix for group testing in hypergraphs.	J. Comb. Optim.	2006	DBLP DOI BibTeX RDF	DNA library screening, Complex, Group testing, Pooling designs
14	Demetrius Arraes Nunes, Daniel Schwabe	Rapid prototyping of web applications combining domain specific languages and model driven design.	WWW	2006	DBLP DOI BibTeX RDF	model-based designs, hypermedia authoring
14	José López Vicario, Carles Antón-Haro	Cross-layer interaction between spatial and multi-user diversity in selective feedback systems: outage capacity analysis.	IWCMC	2006	DBLP DOI BibTeX RDF	multi-antenna schemes, selective scheduling, cross-layer designs, wireless systems, multi-user diversity, spatial diversity
14	Jan Camenisch, Abhi Shelat, Dieter Sommer, Roger Zimmermann	Securing user inputs for the web.	Digital Identity Management	2006	DBLP DOI BibTeX RDF	user interface designs
14	Demetrius Arraes Nunes, Daniel Schwabe	Rapid prototyping of web applications combining domain specific languages and model driven design.	ICWE	2006	DBLP DOI BibTeX RDF	model-based designs, hypermedia authoring
14	John C. Giordano, Martin C. Carlisle	Toward a more effective visualization tool to teach novice programmers.	SIGITE Conference	2006	DBLP DOI BibTeX RDF	RAPTOR, java, designs, flowcharts
14	Michael J. Flynn, Patrick Hung	Microprocessor Design Issues: Thoughts on the Road Ahead.	IEEE Micro	2005	DBLP DOI BibTeX RDF	SIA, performance consideration, reliability, Power, SoC designs, microprocessor design, process technology
14	John P. McSorley	Double Arrays, Triple Arrays and Balanced Grids with v=r+c - 1.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	double arrays, triple arrays, balanced grids, designs, arrays
14	Matthew James Munro	Product Metrics for Automatic Identification of "Bad Smell" Design Problems in Java Source-Code.	IEEE METRICS	2005	DBLP DOI BibTeX RDF	Software Metrics, Refactoring, Object-Oriented Designs
14	Benjamin J. Raphael, Lung-Tien Liu, George Varghese	A Uniform Projection Method for Motif Discovery in DNA Sequences.	IEEE ACM Trans. Comput. Biol. Bioinform.	2004	DBLP DOI BibTeX RDF	random projection, Motif discovery, combinatorial designs, low-discrepancy sequences, transcription factor binding sites
14	S. Purushothaman Iyer, David Hislop, Paul L. Jones, Jaime Lee, Frederick Pearce, Stephen Van Albert	Introductory paper.	Int. J. Softw. Tools Technol. Transf.	2004	DBLP DOI BibTeX RDF	Software in medical devices, Safety of software, Analysis of requirements and designs, US Food and Drug Administration, Formal methods
14	Thierry Nodenot, Christophe Marquesuzaà, Pierre Laforcade, Christian Sallaberry	Model based engineering of learning situations for adaptive web based educational systems.	WWW (Alternate Track Papers & Posters)	2004	DBLP DOI BibTeX RDF	UML language, architectures and designs for web-based learning delivery environments, models and metamodels, specification of educational applications
14	José Javier Dolado, Mark Harman, Mari Carmen Otero, Lin Hu 0005	An Empirical Investigation of the Influence of a Type of Side Effects on Program Comprehension.	IEEE Trans. Software Eng.	2003	DBLP DOI BibTeX RDF	Side-effect-free programs, crossover designs, program comprehension
14	Lars Liebmann	Layout impact of resolution enhancement techniques: impediment or opportunity?	ISPD	2003	DBLP DOI BibTeX RDF	radically restricted designs, resolution enhancement techniques, design for manufacturability, lithography
14	Fernando L. Pelayo, Fernando Cuartero, Valentín Valero Ruiz, Diego Cazorla	An example of performance evaluation by using the stochastic process algebra: ROSA.	RTCSA	2000	DBLP DOI BibTeX RDF	ROSA, algebraic language, performance indexes, Reasoning On Stochastic Algebras, average time to send a message, performance evaluation, performance evaluation, fault tolerance, real-time systems, formal methods, temporal logic, case studies, specification languages, process algebra, algebraic specification, stochastic process algebra, real-time requirements, designs specifications, Alternating Bit Protocol, temporal requirements
14	Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Hu 0001	Efficient algorithms for acceptable design exploration.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	acceptable designs, inclusion scheduling, module utility, design exploration, module selections
14	Amir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh	Quality of EDA CAD Tools: Definitions, Metrics and Directions.	ISQED	2000	DBLP DOI BibTeX RDF	Design Quality Metrics, Integrated Design Exploration, Incremental Synthesis, Layout-Driven Synthesis' System-Level Interconnect Prediction and Planning, Tool Interoperability, Deep Submicron Designs
14	Yuejian Wu	Diagnosis of Scan Chain Failures.	DFT	1998	DBLP DOI BibTeX RDF	scan chain designs, fault diagnosis, design for testability