Search results for "fault-free"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Chi-Hsiang Yeh, Behrooz Parhami, Hua Lee, Emmanouel A. Varvarigos	2.5n-Step Sorting on n*n Meshes in the Presence of o(sqrt(n)) Worst-Case Faults.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
5	Hyosoon Lee, Heonshik Shin, Sang Lyul Min	Worst Case Timing Requirement of Real-Time Tasks with Time Redundancy.	RTCSA	1999	DBLP DOI BibTeX RDF	Fault Tolerance, Real-Time Scheduling, Rollback Recovery, Time Redundancy
5	Amy L. Murphy, Gian Pietro Picco	Reliable Communication for Highly Mobile Agents.	ASA/MA	1999	DBLP DOI BibTeX RDF
5	Fred J. Meyer, Fabrizio Lombardi, Jun Zhao 0005	Good Processor Identification in Two-Dimensional Grids.	DFT	1999	DBLP DOI BibTeX RDF	regular array, repair, PMC model, sequential diagnosis, homogeneous system
5	Krishnendu Chakrabarty	Zero-aliasing space compaction using linear compactors with bounded overhead.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
5	Dimitris Nikolos	Self-Testing Embedded Two-Rail Checkers.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	parity tree, embedded self-testing, self testing, two-rail checker, parity checker
5	J. Yeandel, D. Thulborn, Simon Jones	The Design and Implementation of an On-Line Testable UART.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	design, test, application, partitioning, system level
5	Rosa Rodríguez-Montañés, Joan Figueras	Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ testability, CMOS, deep-submicron
5	Evangelos Kranakis, Danny Krizanc, Andrzej Pelc	Fault-Tolerant Broadcasting in Radio Networks (Extended Abstract).	ESA	1998	DBLP DOI BibTeX RDF
5	Paul F. Reynolds Jr., Craig Williams, Raymond R. Wagner Jr.	Isotach Networks.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	interprocess coordination, isochronicity, interconnection networks, concurrency control, multiprocessor systems, atomicity, sequential consistency, Logical time
5	Chor Ping Low, Hon Wai Leong	On the reconfiguration of degradable VLSI/WSI arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
5	J. Yeandel, D. Thulborn, Simon Jones	An on-line testable UART implemented using IFIS.	VTS	1997	DBLP DOI BibTeX RDF	data communication equipment, online testable UART, IFIS methodology, complex integrated circuit, FPGA technology, dual-rail coding, failure detection, handshaking protocol
5	C. A. Fleischer, Lee A. Belfore II	A new approach for testing artificial neural networks.	VTS	1997	DBLP DOI BibTeX RDF	interconnection deletion faults, faulted ANN, activation function gains, testing, artificial neural networks, neural chips, transient behavior
5	Krishnendu Chakrabarty, John P. Hayes	Test response compaction using multiplexed parity trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
5	Norman F. Schneidewind	Reliability and Risk Analysis for Software that Must be Safe.	IEEE METRICS	1996	DBLP DOI BibTeX RDF	Software Reliability, Risk Analysis, Software Safety
5	Guy G. Berthet, Henri J. Nussbaumer	A Unified Theory for f1/f2-Diagnosable Communication Networks.	EDCC	1996	DBLP DOI BibTeX RDF
5	Koppolu Sasidhar, Abhijit Chatterjee	Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates.	VLSI Design	1996	DBLP DOI BibTeX RDF
5	Norman F. Schneidewind	Reliability Modeling for Safety Critical Software.	Ada-Europe	1996	DBLP DOI BibTeX RDF
5	Kaiyuan Huang, Vinod K. Agarwal, Laurence E. LaForge, Krishnaiyan Thulasiraman	A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
5	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
5	Sandip Kundu	Diagnosing scan chain faults.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
5	Yonatan Aumann, Judit Bar-Ilan, Uriel Feige	On the Cost of Recomputing: Tight Bounds on Pebbling with Faults.	ICALP	1994	DBLP DOI BibTeX RDF
5	Bogdan S. Chlebus, Krzysztof Diks, Andrzej Pelc	Sparse Networks Supporting Efficient Reliable Broadcasting.	ICALP	1993	DBLP DOI BibTeX RDF
5	Sy-Yen Kuo, Ing-Yi Chen	Efficient reconfiguration algorithms for degradable VLSI/WSI arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
5	Pinaki Mazumder, Janak H. Patel	An efficient design of embedded memories and their testability analysis using Markov chains.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Embedded random-access memories, random testing and testable design
5	Sandeep N. Bhatt, Fan R. K. Chung, Frank Thomson Leighton, Arnold L. Rosenberg	Tolerating Faults in Synchronization Networks.	CONPAR	1992	DBLP DOI BibTeX RDF
5	Alexander Wang, Robert Cypher, Ernst W. Mayr	Embedding complete binary trees in faulty hypercubes.	SPDP	1991	DBLP DOI BibTeX RDF
5	Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli	Reconfiguration of VLSI arrays by covering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
5	Hsi-Ching Shih, Jacob A. Abraham	Transistor-level test generation for physical failures in CMOS circuits.	DAC	1986	DBLP DOI BibTeX RDF