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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 778 occurrences of 456 keywords
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Results
Found 529 publication records. Showing 529 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
5 | Chi-Hsiang Yeh, Behrooz Parhami, Hua Lee, Emmanouel A. Varvarigos |
2.5n-Step Sorting on n*n Meshes in the Presence of o(sqrt(n)) Worst-Case Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS/SPDP ![In: 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 12-16 April 1999, San Juan, Puerto Rico, Proceedings, pp. 436-440, 1999, IEEE Computer Society, 0-7695-0143-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
5 | Hyosoon Lee, Heonshik Shin, Sang Lyul Min |
Worst Case Timing Requirement of Real-Time Tasks with Time Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 6th International Workshop on Real-Time Computing and Applications Symposium (RTCSA '99), 13-16 December 1999, Hong Kong, China, pp. 410-, 1999, IEEE Computer Society, 0-7695-0306-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Fault Tolerance, Real-Time Scheduling, Rollback Recovery, Time Redundancy |
5 | Amy L. Murphy, Gian Pietro Picco |
Reliable Communication for Highly Mobile Agents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASA/MA ![In: 1st International Symposium on Agent Systems and Applications / 3rd International Symposium on Mobile Agents (ASA/MA '99), 3-6 October 1999, Palm Springs, CA, USA, pp. 141-151, 1999, IEEE Computer Society, 0-7695-0340-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
5 | Fred J. Meyer, Fabrizio Lombardi, Jun Zhao 0005 |
Good Processor Identification in Two-Dimensional Grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 348-356, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
regular array, repair, PMC model, sequential diagnosis, homogeneous system |
5 | Krishnendu Chakrabarty |
Zero-aliasing space compaction using linear compactors with bounded overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5), pp. 452-457, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
5 | Dimitris Nikolos |
Self-Testing Embedded Two-Rail Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 69-79, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
parity tree, embedded self-testing, self testing, two-rail checker, parity checker |
5 | J. Yeandel, D. Thulborn, Simon Jones |
The Design and Implementation of an On-Line Testable UART. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(3), pp. 187-198, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
design, test, application, partitioning, system level |
5 | Rosa Rodríguez-Montañés, Joan Figueras |
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 490-494, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDDQ testability, CMOS, deep-submicron |
5 | Evangelos Kranakis, Danny Krizanc, Andrzej Pelc |
Fault-Tolerant Broadcasting in Radio Networks (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA '98, 6th Annual European Symposium, Venice, Italy, August 24-26, 1998, Proceedings, pp. 283-294, 1998, Springer, 3-540-64848-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
5 | Paul F. Reynolds Jr., Craig Williams, Raymond R. Wagner Jr. |
Isotach Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(4), pp. 337-348, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
interprocess coordination, isochronicity, interconnection networks, concurrency control, multiprocessor systems, atomicity, sequential consistency, Logical time |
5 | Chor Ping Low, Hon Wai Leong |
On the reconfiguration of degradable VLSI/WSI arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), pp. 1213-1221, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
5 | J. Yeandel, D. Thulborn, Simon Jones |
An on-line testable UART implemented using IFIS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 344-349, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
data communication equipment, online testable UART, IFIS methodology, complex integrated circuit, FPGA technology, dual-rail coding, failure detection, handshaking protocol |
5 | C. A. Fleischer, Lee A. Belfore II |
A new approach for testing artificial neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 245-251, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
interconnection deletion faults, faulted ANN, activation function gains, testing, artificial neural networks, neural chips, transient behavior |
5 | Krishnendu Chakrabarty, John P. Hayes |
Test response compaction using multiplexed parity trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11), pp. 1399-1408, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Norman F. Schneidewind |
Reliability and Risk Analysis for Software that Must be Safe. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE METRICS ![In: 3rd IEEE International Software Metrics Symposium (METRICS 1996), From Measurement to Empirical Results, March 25-26, 1996, Berlin, Germany, pp. 142-, 1996, IEEE Computer Society, 0-8186-7364-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Software Reliability, Risk Analysis, Software Safety |
5 | Guy G. Berthet, Henri J. Nussbaumer |
A Unified Theory for f1/f2-Diagnosable Communication Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings, pp. 421-438, 1996, Springer, 3-540-61772-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Koppolu Sasidhar, Abhijit Chatterjee |
Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 65-68, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Norman F. Schneidewind |
Reliability Modeling for Safety Critical Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ada-Europe ![In: Reliable Software Technologies - Ada-Europe '96, 1996 Ada-Europe International Conference on Reliable Software Technologies, Montreux, Switzerland, June 10-14, 1996, Proceedings, pp. 17-37, 1996, Springer, 3-540-61317-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Kaiyuan Huang, Vinod K. Agarwal, Laurence E. LaForge, Krishnaiyan Thulasiraman |
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(4), pp. 363-372, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
5 | Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto |
Universal test complexity of field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 259-265, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable |
5 | Sandip Kundu |
Diagnosing scan chain faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(4), pp. 512-516, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
5 | Yonatan Aumann, Judit Bar-Ilan, Uriel Feige |
On the Cost of Recomputing: Tight Bounds on Pebbling with Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 21st International Colloquium, ICALP94, Jerusalem, Israel, July 11-14, 1994, Proceedings, pp. 47-58, 1994, Springer, 3-540-58201-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
5 | Bogdan S. Chlebus, Krzysztof Diks, Andrzej Pelc |
Sparse Networks Supporting Efficient Reliable Broadcasting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 20nd International Colloquium, ICALP93, Lund, Sweden, July 5-9, 1993, Proceedings, pp. 388-397, 1993, Springer, 3-540-56939-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
5 | Sy-Yen Kuo, Ing-Yi Chen |
Efficient reconfiguration algorithms for degradable VLSI/WSI arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10), pp. 1289-1300, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
5 | Pinaki Mazumder, Janak H. Patel |
An efficient design of embedded memories and their testability analysis using Markov chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(3), pp. 235-250, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Embedded random-access memories, random testing and testable design |
5 | Sandeep N. Bhatt, Fan R. K. Chung, Frank Thomson Leighton, Arnold L. Rosenberg |
Tolerating Faults in Synchronization Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 92 - VAPP V, Second Joint International Conference on Vector and Parallel Processing, Lyon, France, September 1-4, 1992, Proceedings, pp. 1-12, 1992, Springer, 3-540-55895-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
5 | Alexander Wang, Robert Cypher, Ernst W. Mayr |
Embedding complete binary trees in faulty hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, SPDP 1991, 2-5 December 1991, Dallas, Texas, USA, pp. 112-119, 1991, IEEE Computer Society, 0-8186-2310-1. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
5 | Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli |
Reconfiguration of VLSI arrays by covering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9), pp. 952-965, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
5 | Hsi-Ching Shih, Jacob A. Abraham |
Transistor-level test generation for physical failures in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 243-249, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
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