Search results for "netlist"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh	Fast and accurate estimation of floorplans in logic/high-level synthesis.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
10	Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino	Power Macromodeling for a High Quality RT-Level Power Estimation.	ISQED	2000	DBLP DOI BibTeX RDF
10	Panagiotis Manolios	Correctness of Pipelined Machines.	FMCAD	2000	DBLP DOI BibTeX RDF
10	Yu-Liang Wu, Wangning Long, Hongbing Fan	A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks.	VLSI Design	2000	DBLP DOI BibTeX RDF	Alternative wiring, Graph-based pattern matching, Logic synthesis
10	Abhijit Ghosh, Ranga Vemuri	Formal Verification of Synthesized Mixed Signal Designs Using *BMDs.	VLSI Design	2000	DBLP DOI BibTeX RDF
10	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
10	Vladimir V. Saposhnikov, V. Moshanin, Valerij V. Saposhnikov, Michael Gössel	Experimental Results for Self-Dual Multi-Output Combinational Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF
10	Shenggao Li, Brian Okoon, Mona Mostafa Hella, Mohammed Ismail 0001, Maya Rubeiz	The Implementation of a VHDL-AMS to SPICE Converter.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
10	Gregory H. Chisholm, Steven T. Eckmann, Christopher M. Lain, Robert Veroff	Understanding Integrated Circuits.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
10	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists.	CAV	1999	DBLP DOI BibTeX RDF
10	Yun-Yin Lian, Youn-Long Lin	Layout-based Logic Decomposition for Timing Optimization.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting	A CAD Suite for High-Performance FPGA Design.	FCCM	1999	DBLP DOI BibTeX RDF	adaptive computing systems, high-performance FPGA design, FPGAs, configurable computing
10	Russell Tessier	Incremental Compilation for Logic Emulation.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	virtual wire, scheduling, partitioning, incremental, logic emulation
10	Rolf Drechsler, Wolfgang Günther 0001	Generation of Optimal Universal Logic Modules.	EUROMICRO	1999	DBLP DOI BibTeX RDF
10	Dimitrios Kagaris, Spyros Tragoudas	Embedded cores using built-in mechanisms.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Rolf Drechsler, Marc Herbstritt, Bernd Becker 0001	Grouping heuristics for word-level decision diagrams.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Ramón González Carvajal, Antonio Jesús Torralba Silgado, Rafael L. Millán, Leopoldo García Franquelo	Automatic synthesis of analog and mixed-signal fuzzy controllers with emphasis in power consumption.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
10	Debabrata Ghosh, Franc Brglez	Equivalence classes of circuit mutants for experimental design.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
10	Michael D. Hutton, Jonathan Rose	Equivalence classes of clone circuits for physical-design benchmarking.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
10	Wai-Kei Mak, D. F. Wong 0001	A fast hypergraph minimum cut algorithm.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
10	Ronnie L. Wright, Michael A. Shanblatt	Reducing BDD Size by Exploiting Structural Connectivity.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
10	Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin	Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations.	VLSI Design	1999	DBLP DOI BibTeX RDF
10	Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil	Characterization and parameterized generation of synthetic combinational benchmark circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
10	Xiao Quan Li, Marwan A. Jabri	Machine learning-based VLSI cells shape function estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
10	Jordan S. Swartz, Vaughn Betz, Jonathan Rose	A Fast Routability-Driven Router for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
10	Min Xu, Fadi J. Kurdahi	Layout-Driven High Level Synthesis for FPGA Based Architectures.	DATE	1998	DBLP DOI BibTeX RDF
10	Qi Wang, Sarma B. K. Vrudhula	Data Driven Power Optimization of Sequential Circuits.	DATE	1998	DBLP DOI BibTeX RDF	logic synthesis low power design sequential circuits digital circuit testing verification
10	Hans van Gageldonk, Kees van Berkel 0001, Ad M. G. Peeters, Daniel Baumann, Daniel Gloor, Gerhard Stegmann	An Asynchronous Low-Power 80C51 Microcontroller.	ASYNC	1998	DBLP DOI BibTeX RDF	VLSI-programming, low-power, microcontrollers, asynchronous design
10	Jianping Lu, Sofiène Tahar	Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
10	Sela Mador-Haim, Limor Fix	Input Elimination and Abstraction in Model Checking.	FMCAD	1998	DBLP DOI BibTeX RDF
10	Zinaida V. Apanovich, Alexander G. Marchuk	Top-Down Approach to Technology Migration for Full-Custom Mask Layouts.	VLSI Design	1998	DBLP DOI BibTeX RDF	Technology migration, decomposition, compaction, rerouting
10	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.	DAC	1998	DBLP DOI BibTeX RDF
10	Ralph H. J. M. Otten, Robert K. Brayton	Planning for Performance.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
10	Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe	Watermarking Techniques for Intellectual Property Protection.	DAC	1998	DBLP DOI BibTeX RDF	system-on-chip test, testing embedded core, intellectual property test
10	Jason Cong, Songjie Xu	Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
10	Pi-Yu Chung, Ibrahim N. Hajj	Diagnosis and correction of multiple logic design errors in digital circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
10	Wolfgang Kunz, Dominik Stoffel, Prem R. Menon	Logic optimization and equivalence checking by implication analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
10	Lars W. Hagen, Andrew B. Kahng	Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
10	Dilvan de Abreu Moreira, Les T. Walczowski	AGENTS a distributed client-server system for leaf cell generation.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	genetic algorithms, software agents, client/server model
10		Testing Embedded Cores.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
10	K. S. Seong, C. M. Kyung	Two-way partitioning based on direction vector [layout design].	ED&TC	1997	DBLP DOI BibTeX RDF
10	Srinivasa Rao Arikati, Ravi Varadarajan	A signature based approach to regularity extraction.	ICCAD	1997	DBLP DOI BibTeX RDF	regular structure extraction, Physical design
10	Ibrahim M. Elfadel, David D. Ling	A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks.	ICCAD	1997	DBLP DOI BibTeX RDF	Arnoldi iteration, multipoint Pade' approximation, passivity, model-order reduction
10	Chua Hong Chuck, Chin Teck Chai, Tan Gim Chua	A structured approach for routing of MCMs.	KES (1)	1997	DBLP DOI BibTeX RDF
10	Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs	Diagnostic Test Pattern Generation for Sequential Circuits.	VTS	1997	DBLP DOI BibTeX RDF
10	Jianzhong Shi, Akash Randhar, Dinesh Bhatia	Macro Block Based FPGA Floorplanning.	VLSI Design	1997	DBLP DOI BibTeX RDF	macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
10	John F. Croix, D. F. Wong 0001	A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis.	DAC	1997	DBLP DOI BibTeX RDF
10	Helena Krupnova, Ali Abbara, Gabriele Saucier	A Hierarchy-Driven FPGA Partitioning Method.	DAC	1997	DBLP DOI BibTeX RDF
10	Charles J. Alpert, Andrew B. Kahng	A general framework for vertex orderings with applications to circuit clustering.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
10	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
10	Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson	Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
10	Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou	A power modeling and characterization method for the CMOS standard cell library.	ICCAD	1996	DBLP DOI BibTeX RDF	power characterization, power consumption, power estimation
10	Hans T. Heineken, Wojciech Maly	Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.	ICCAD	1996	DBLP DOI BibTeX RDF	Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield
10	N. Mani	A two-way graph partitioning using a heuristic procedure.	ANZIIS	1996	DBLP DOI BibTeX RDF
10	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
10	C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora	Estimation of Power from Module-level Netlists.	VLSI Design	1996	DBLP DOI BibTeX RDF
10	Kei-Yong Khoo, Jason Cong	An efficient multilayer MCM router based on four-via routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
10	Eric Lemoine, David Merceron	Run time reconfiguration of FPGA for scanning genomic databases.	FCCM	1995	DBLP DOI BibTeX RDF
10	Roman Kuznar, Franc Brglez	PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	optimization, FPGA, partitioning, resynthesis, critical path delay
10	Manfred Henftling, Hannes C. Wittmann, Kurt Antreich	A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization.	ICCAD	1995	DBLP DOI BibTeX RDF	test generation, ATPG, propagation
10	Jin-Tai Yan	Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning.	ICCD	1995	DBLP DOI BibTeX RDF	fuzzy neural nets, connection-oriented net model, fuzzy clustering techniques, K-way circuit partitioning, chain net model, cut analysis, multiple-pin net, edge-weighted graph, MCNC circuit benchmarks, partitioning balance, partitioning cut, computational complexity, complexity, fuzzy logic, high level synthesis, circuit analysis computing, hypergraph, fuzzy c-means clustering, mapped graph, fuzzy memberships
10	Chien-In Henry Chen, Joel T. Yuen	Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
10	Valentino Liberali, Victor da Fonte Dias, M. Ciapponi, Franco Maloberti	TOSCA: a simulator for switched-capacitor noise-shaping A/D converters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
10	Stephen T. Frezza, Steven P. Levitan	SPAR: a schematic place and route system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
10	Stella N. Batalama, Dimitrios A. Pados, Theodore S. Papatheodorou	A heuristic single-row router minimizing interstreet crossings.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
10	Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth	Generating Tests for Delay Faults in Nonscan Circuits.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
10	John D. Calhoun, Franc Brglez	A framework and method for hierarchical test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
10	Larry G. Jones	An incremental zero/integer delay switch-level simulation environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
10	Raffaele Costa, Francesco Curatelli, Daniele D. Caviglia, Giacomo M. Bisio	Symbolic generation of constrained random logic cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
10	Raul Camposano	From Behavior to Structure: High-Level Synthesis.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
10	Wolfgang Meier	Hierarchical layout verification for submicron designs.	EURO-DAC	1990	DBLP DOI BibTeX RDF
10	Michael Zimmermann, Manfred Geilert	Generation of embedded RAMs with built-in test using object-oriented programming.	EURO-DAC	1990	DBLP DOI BibTeX RDF
10	Roni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski	Percolation Based Synthesis.	DAC	1990	DBLP DOI BibTeX RDF
10	Dwight D. Hill, Don Shugard	Global Routing Considerations in a Cell Synthesis System.	DAC	1990	DBLP DOI BibTeX RDF
10	Erik C. Carlson, Rob A. Rutenbar	Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW.	DAC	1990	DBLP DOI BibTeX RDF
10	Peter Ramyalal Suaris, Gershon Kedem	A quadrisection-based combined place and route scheme for standard cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
10	Charles J. Poirier	Excellerator: custom CMOS leaf cell layout generator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
10	Wolfgang Borutzky	Combining Behavioral Block Diagram Modelling with Circuit Simulation.	EUROCAST	1989	DBLP DOI BibTeX RDF	mixed behavioral, circuit-level modelling, electrical macromodels, continuous system simulation, electronic control systems, circuit simulation, functional simulation, block diagrams, signal processing systems
10	Richard H. Lathrop, Robert J. Hall 0001, Gavan Duffy, K. Mark Alexander, Robert S. Kirk	Advances in Functional Abstraction from Structure.	DAC	1988	DBLP BibTeX RDF
10	Robin L. Steele	An Expert System Application in Semicustom VLSI Design.	DAC	1987	DBLP DOI BibTeX RDF
10	Richard H. Lathrop, Robert J. Hall 0001, Robert S. Kirk	Functional Abstraction from Structure in VLSI Simulation Models.	DAC	1987	DBLP DOI BibTeX RDF
10	Ahsan Bootehsaz, Robert A. Cottrell	A technology independent approach to hierarchical IC layout extraction.	DAC	1986	DBLP DOI BibTeX RDF
10	Stef van Vlierberghe, Jeff Rijmenants, Walter Heyns	Symbolic hierarchical artwork generation system.	DAC	1985	DBLP DOI BibTeX RDF