Search results for "silicon"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Eugenio Culurciello, Andreas G. Andreou	Capacitive coupling of data and power for 3D silicon-on-insulator VLSI.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
15	André van Schaik, Shih-Chii Liu	AER EAR: a matched silicon cochlea pair with address event representation interface.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Francesco Carrara, Angelo Scuderi, Antonio Scuderi, Geraldo Bottiglieri, Giuseppe Palmisano	Silicon bipolar linear power amplifier for WCDMA mobile applications.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Eugenio Culurciello, Philippe O. Pouliquen, Andreas G. Andreou, Kim Strohbehn, Steven E. Jaskulek	A monolithic isolation amplifier in silicon-on-insulator CMOS.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	José L. Núñez-Yáñez, Vassilios A. Chouliaras	Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.	ASAP	2005	DBLP DOI BibTeX RDF
15	Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles	How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.	ISQED	2005	DBLP DOI BibTeX RDF
15	Brian Taba, Kwabena Boahen 0001	Balancing Guidance Range and Strength Optimizes Self-organization by Silicon Growth Cones.	ICANN (2)	2005	DBLP DOI BibTeX RDF
15	Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode	Scaling to the End of Silicon with EDGE Architectures.	Computer	2004	DBLP DOI BibTeX RDF
15	Swapnil Bahl	A Novel Method for Silicon Configurable Test Flow and Algorithms for Testing, Debugging and Characterizing Different Types of Embedded Memories through a Shared Controller.	MTDT	2004	DBLP DOI BibTeX RDF
15	Jonathan Rose	Hard vs. Soft: The Central Question of Pre-Fabricated Silicon.	ISMVL	2004	DBLP DOI BibTeX RDF
15	Shanrui Zhang, Minsu Choi, Nohpill Park	Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme.	DFT	2004	DBLP DOI BibTeX RDF
15	S. S. Prasad, Pradip Mandal	A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability.	VLSI Design	2004	DBLP DOI BibTeX RDF
15	Ghanshyam Nayak, P. R. Mukund	Chip Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS VCO using Embedded Passives in a Silicon Package.	VLSI Design	2004	DBLP DOI BibTeX RDF
15	P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala	Package-silicon co-design - Experiment with an SOC design.	VLSI Design	2004	DBLP DOI BibTeX RDF
15	Gaye Lightbody, Roger F. Woods, Richard L. Walke	Design of a parameterizable silicon intellectual property core for QR-based RLS filtering.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
15	Alyssa B. Apsel, Eugenio Culurciello, Andreas G. Andreou, K. Aliberti	Thin film PIN photodiodes for optoelectronic silicon on sapphire CMOS.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
15	Te-Hsin Huang, Ertan Zencir, Mehmet R. Yuce, Numan Sadi Dogan, Wentai Liu, Ercument Arvas	A 22-mW 435 MHz silicon on insulator CMOS high-gain LNA for subsampling receivers.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Seiji Kameda, Tetsuya Yagi	A silicon retina system that calculates direction of motion.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
15	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak	Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.	ITC	2003	DBLP DOI BibTeX RDF
15		News: Intel expands advanced 300-mm wafer production; IBM claims world's smallest computer circuits; IEEE 802.11b chip market growth; Samsung extends system LSI commitment; light-emitting silicon; new gas sensors.	IEEE Micro	2002	DBLP DOI BibTeX RDF
15	Steven C. Chan, Kenneth L. Shepard, Dae-Jin Kim	Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
15	Blaise Gassend, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas	Silicon physical random functions.	CCS	2002	DBLP DOI BibTeX RDF	physical random function, unclonability, identification, smartcard, tamper resistance, physical security
15	Tal Lavian, Phil Wang, Franco Travostino, Siva Subramanian, Ramesh Durairaj, Doan B. Hoang, Vijak Sethaput, David E. Culler	Enabling Active Flow Manipulation in Silicon-Based Network Forwarding Engines.	DANCE	2002	DBLP DOI BibTeX RDF
15	Todd E. Peterson, D. W. Wilson, Harrison H. Barrett	A small-animal imaging system based on silicon strip detectors.	ISBI	2002	DBLP DOI BibTeX RDF
15	Kees Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen	Networks on Silicon: Combining Best-Effort and Guaranteed Services.	DATE	2002	DBLP DOI BibTeX RDF
15	Paul Wielage, Kees Goossens	Networks on Silicon: Blessing or Nightmare?	DSD	2002	DBLP DOI BibTeX RDF
15	Mohammad Al-Towaiq, Huda Al-Aamri	A Parallel Implementation of GESPP on a Cluster of Silicon Graphics Workstations.	ICPADS	2002	DBLP DOI BibTeX RDF	Algorithms, Parallel Computing, Linear Systems
15	Fernando Silveira, Denis Flandre	A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
15	Yuri E. Gorbachev, Mikhail A. Zatevakhin, Valeria V. Krzhizhanovskaya, A. A. Ignatiev, V. K. Protopopov, N. V. Sokolova, A. B. Witenberg	Distributed Simulation of Amorphous Hydrogenated Silicon Films: Numerical Experiments on a Linux Based Computing Environment.	International Conference on Computational Science (1)	2001	DBLP DOI BibTeX RDF
15	Valeria V. Krzhizhanovskaya, Mikhail A. Zatevakhin, A. A. Ignatiev, Yuri E. Gorbachev, Peter M. A. Sloot	Distributed Simulation of Silicon-Based Film Growth.	PPAM	2001	DBLP DOI BibTeX RDF
15	B. Prasad, P. J. George, Chandra Shekhar 0001	High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors.	VLSI Design	2001	DBLP DOI BibTeX RDF
15	B. Senapati, Chinmay K. Maiti, Nirmal B. Chakrabarti	Silicon Heterostructure Devices for RF Wireless Communication.	VLSI Design	2000	DBLP DOI BibTeX RDF	SiGe-HBT, planar inductor, RF amplifier, RFICs
15	Kenneth L. Shepard, Dae-Jin Kim	Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology.	DAC	2000	DBLP DOI BibTeX RDF
15	Jonghan Shin, Christof Koch	Dynamic range and sensitivity adaptation in a silicon spiking neuron.	IEEE Trans. Neural Networks	1999	DBLP DOI BibTeX RDF
15	D. Guillet, K. Mourgues, R. Rogel, H. Lhermite, Olivier Bonnaud	Student Realization in Cleanroom of Silicon-Germanium Thin Film Transistors.	MSE	1999	DBLP DOI BibTeX RDF
15	Jonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew I. Frank, Rajeev Barua, Saman P. Amarasinghe	Parallelizing Applications into Silicon.	FCCM	1999	DBLP DOI BibTeX RDF
15	Theo A. C. M. Claasen	The Changing Semiconductor Industry: From Components to Silicon Systems.	EUROMICRO	1999	DBLP DOI BibTeX RDF
15	Kurt Keutzer, A. Richard Newton	The MARCO/DARPA Gigascale Silicon Research Center.	ICCD	1999	DBLP DOI BibTeX RDF
15	Philipp Häfliger, Christoph Rasche	Floating gate analog memory for parameter and variable storage in a learning silicon neuron.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
15	Tadashi Shibata	Right brain computing hardware: a psychological brain model on silicon.	KES (3)	1998	DBLP DOI BibTeX RDF
15	Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost	A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology.	ISLPED	1998	DBLP DOI BibTeX RDF
15	Young-Jun Kwon, Ben Mathew, Hong Hao	FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.	ITC	1998	DBLP DOI BibTeX RDF
15	S. Samel, Bert Gyselinckx, Ivo Bolsens, Hugo De Man	Designing Systems On Silicon: A Digital Spread Spectrum Pager.	VLSI Design	1996	DBLP DOI BibTeX RDF	System Design Methodologies, HW/SW Co-design, DSP Applications
15	Yevgeny V. Mamontov, Magnus Willander	Accounting thermal noise in mathematical models of quasi-homogeneous regions in silicon devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
15	Frans P. M. Beenker, Barry J. Dekker, Richard Stans, Max van der Star	Implementing Macro Test in Silicon Compiler Design.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
15	J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man	CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler.	EURO-DAC	1990	DBLP DOI BibTeX RDF
15	Mehrdad Negahban, Daniel Gajski	Silicon compilation of switched: capacitor networks.	EURO-DAC	1990	DBLP DOI BibTeX RDF
15	Philippe Bondono, Ahmed Amine Jerraya, Armand Hornik, Bernard Courtois, D. Bonifas	NAUTILE: a safe environment for silicon compilation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
15	D. David Forsythe, Atul P. Agarwal, Chune-Sin Yeh, Sheldon Aronowitz, Bhaskar Gadepally	NASFLOW, a Simulation Tool for Silicon Technology Development.	DAC	1990	DBLP DOI BibTeX RDF
15	Richard W. Linderman, Paul C. Rossbach, David M. Gallagher	Design and application of an optimizing XROM silicon compiler.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
15	Toshiaki Tanaka, Tsutomu Kobayashi, Osamu Karatsu	HARP: FORTRAN to silicon [compilation system].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
15	Baher Haroun, Mohamed I. Elmasry	Architectural synthesis for DSP silicon compilers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
15	Stephen Nelson	Using silicon and gallium arsenide technologies for new supercomputer design.	ICS	1988	DBLP DOI BibTeX RDF
15	Gotaro Odawara, Masahiro Tomita, Kazuhiko Hattori, Osamu Okuzawa, Toshiaki Hirata, Masayasu Ochiai	A Human Machine Interface for Silicon Compilation.	DAC	1988	DBLP BibTeX RDF
15	Raul Camposano	Design Process Model in the Yorktown Silicon Compiler.	DAC	1988	DBLP BibTeX RDF
15	Richard I. Hartley, Peter F. Corbett	A Digit-Serial Silicon Compiler.	DAC	1988	DBLP BibTeX RDF
15	Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp	The ALGIC Silicon Compiler System: Implementation, Design Experience and Results.	DAC	1987	DBLP DOI BibTeX RDF
15	David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin	Automated layout synthesis in the YASC silicon compiler.	DAC	1986	DBLP DOI BibTeX RDF
15	Manfred Glesner, Johannes Schuck, R. B. Steck	SCAT - a new statistical timing verifier in a silicon compiler system.	DAC	1986	DBLP DOI BibTeX RDF
15	Russel L. Steinweg, Susan J. Aguirre, Kerry Pierce, Scott Nance	Silicon compilation of gate array bases.	DAC	1985	DBLP DOI BibTeX RDF
15	Timothy Blackman, Jeffrey R. Fox, Christopher Rosebrugh	The Silc silicon compiler: language and features.	DAC	1985	DBLP DOI BibTeX RDF
15	David E. Krekelberg, Gerald E. Sobelman, Chu S. Jhon	Yet another silicon compiler.	DAC	1985	DBLP DOI BibTeX RDF
12	Matthew Canton	The presence table: a reactive surface for ambient connection.	TEI	2011	DBLP DOI BibTeX RDF
12	Jieyi Long, Seda Ogrenci Memik	A framework for optimizing thermoelectric active cooling systems.	DAC	2010	DBLP DOI BibTeX RDF	thermal runaway, thermoelectric cooling, optimization
12	Samta Bansal, Juan C. Rey, Andrew Yang, Myung-Soo Jang, L. C. Lu, Philippe Magarshack, Pol Marchal, Riko Radojcic	3-D stacked die: now or future?	DAC	2010	DBLP DOI BibTeX RDF	integrated circuits, 3-D
12	Zhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen 0002	Emerging nanodevice paradigm: Graphene-based electronics for nanoscale computing.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Graphene device, negative differential resistance, tight-binding model, memory structure
12	Zheng Li, Ahalapitiya H. Jayatissa, Lash Mapa, Ezzatollah Salari, A. C. Jayasuriya	Electrochemical sensors for detection of biomolecules.	EIT	2009	DBLP DOI BibTeX RDF
12	Elena Angeli, Chiara Manneschi, Luca Repetto, Giuseppe Firpo, Corrado Boragno, Ugo Valbusa	Fabrication of Elastomeric Nanofluidic Devices for Manipulation of Long DNA Molecules.	NanoNet	2009	DBLP DOI BibTeX RDF	Nanochannels, DNA Separation, Nanoconfinement, PDMS
12	Raúl Martínez, Francisco José Alfaro, José L. Sánchez 0002, José M. Claver	Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms.	Euro-Par	2009	DBLP DOI BibTeX RDF
12	Xiaosong Sun	Small Structure State Detection with Fiber-optic Sensors and Neural Network.	WKDD	2009	DBLP DOI BibTeX RDF
12	Yi-Chi Chen, Hui-Chin Yang, Chung-Ping Chung, Wei-Ting Wang	Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing.	CSE (2)	2009	DBLP DOI BibTeX RDF
12	Duo Ding, David Z. Pan	OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture.	SLIP	2009	DBLP DOI BibTeX RDF	photonic networks-on-chip, low power, computer aided design, high performance
12	Tomohisa Ito, Takeshi Yamaguchi, Hiroshi Yoshikawa	High resolution computer-generated cylindrical hologram.	IUCS	2009	DBLP DOI BibTeX RDF	computer-generated hologram, cylindrical hologram, fringe printer, holography
12	Roto Le, Sherief Reda, R. Iris Bahar	High-performance, cost-effective heterogeneous 3D FPGA architectures.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	3D integrated circuits, heterogeneous FPGA design
12	Rakesh S. Anigundi, Hongbin Sun 0001, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002	Architecture design exploration of three-dimensional (3D) integrated DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
12	Yongquan Fan, Zeljko Zilic	Accelerating jitter tolerance qualification for high speed serial interfaces.	ISQED	2009	DBLP DOI BibTeX RDF
12	Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski	A full-rate truly monolithic CMOS CDR for low-cost applications.	CCECE	2009	DBLP DOI BibTeX RDF
12	Sudeep Pasricha	Exploring serial vertical interconnects for 3D ICs.	DAC	2009	DBLP DOI BibTeX RDF	serial interconnect, VLSI, networks on chip, 3D ICs
12	Nishant Patil, Albert Lin, Jie Zhang 0007, H.-S. Philip Wong, Subhasish Mitra	Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.	DAC	2009	DBLP DOI BibTeX RDF	CNFET, carbon nanotube transistor, carbon nanotubes
12	Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi	Creating an affordable 22nm node using design-lithography co-optimization.	DAC	2009	DBLP DOI BibTeX RDF	design technology co-optimization, templates, DFM, regular fabric
12	Xiaofeng Wu 0001, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall	A Novel Delta Sigma Control System Processor and Its VLSI Implementation.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
12	Nazish Aslam, Mark Milward, Ahmet T. Erdogan, Tughrul Arslan	Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
12	Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra	Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
12	Stephen K. Sunter, Aubin Roy	Noise-Insensitive Digital BIST for any PLL or DLL.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	BIST, Jitter, Design for test, PLL, Mixed-signal test, DLL
12	Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang	A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	profiling, design for testability, Diagnosis, fault, scan chain
12	David Heriban, Michaël Gauthier	Robotic micro-assembly of microparts using a piezogripper.	IROS	2008	DBLP DOI BibTeX RDF
12	Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii	Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.	DATE	2008	DBLP DOI BibTeX RDF
12	Kaiyu Chen, Sharad Malik, Priyadarsan Patra	Runtime validation of memory ordering using constraint graph checking.	HPCA	2008	DBLP DOI BibTeX RDF
12	Grant Martin	Panel: Best ways to use billions of devices on a chip.	ASP-DAC	2008	DBLP DOI BibTeX RDF
12	Noel Tomás, Julio Sahuquillo, Salvador Petit, Pedro López 0001	Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot.	Euro-Par	2008	DBLP DOI BibTeX RDF
12	Luc Ceuppens, Alan Sardella, Daniel Kharitonov	Power Saving Strategies and Technologies in Network Equipment Opportunities and Challenges, Risk and Rewards.	SAINT	2008	DBLP DOI BibTeX RDF	network, power, routers, green
12	Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.	ICCAD	2008	DBLP DOI BibTeX RDF
12	Tao Chen 0010, Liguo Chen, Lining Sun, Jiachou Wang, Xinxin Li	A Sidewall Piezoresistive Force Sensor Used in a MEMS Gripper.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Microgripper, Sidewall piezoresistive sensor, MEMS
12	Shan Yan, Bill Lin 0001	Design of application-specific 3D Networks-on-Chip architectures.	ICCD	2008	DBLP DOI BibTeX RDF
12	Andrea Pellegrini, Kypros Constantinides, Dan Zhang 0004, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin	CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework.	ICCD	2008	DBLP DOI BibTeX RDF
12	Daniel Matolin, Christoph Posch, Rainer Wohlgenannt, Thomas Maier	A 64×64 pixel temporal contrast microbolometer infrared sensor.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Liang Lu, John V. McCanny, Sakir Sezer	Multi-standard sub-pixel interpolation architecture for video Motion Estimation.	SoCC	2008	DBLP DOI BibTeX RDF
12	Richard Ficek, Radimir Vrba, Ondrej Jasek, Marek Eliás 0002, Lenka Zajickova, Hana Hornochova	Carbon Nanostructures in MEMS Applications.	ICONS	2008	DBLP DOI BibTeX RDF	field emission current, MEMS, Carbon nanotubes, pressure sensor
12	Tak H. Ning	GLSVLSI 2008 invited/keynote talk.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	soi, cmos scaling
12	Hongbin Sun 0001, Nanning Zheng 0001, Tong Zhang 0002	Realization of L2 Cache Defect Tolerance Using Multi-bit ECC.	DFT	2008	DBLP DOI BibTeX RDF