Search results for "ASICs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Thierry J.-F. Omnés, Francky Catthoor, Thierry Franzetti	Multi-dimensional Selection Techniques for Minimizing Memory Bandwidth in High-Throughput Embedded Systems.	HiPC	2000	DBLP DOI BibTeX RDF
10	Michel Renovell	A Specific Test Methodology for Symmetric SRAM-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
10	Jeremy Ekman, Christoph Berger, Fouad E. Kiamilev, X. Wang, Henk A. E. Spaanenburg, Philippe J. Marchand, Sadik C. Esener	A Distributed Computing Demonstration System Using FSOI Inter-processor Communication.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
10	Khoan Truong	A Simple Built-In Self Test For Dual Ported SRAMs.	MTDT	2000	DBLP DOI BibTeX RDF
10	Luca Fanucci, Sergio Saponara, Andrea Cenciotti	IP Reuse VLSI Architecture for Low Complexity Fast Motion Estimation in Multimedia Applications.	EUROMICRO	2000	DBLP DOI BibTeX RDF
10	Carlo Guardiani, Andrzej J. Strojwas	Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead?	ISQED	2000	DBLP DOI BibTeX RDF
10	Bernard Girau	Building a 2D-Compatible Multilayer Neural Network.	IJCNN (2)	2000	DBLP DOI BibTeX RDF
10	Vivek Chickermane, Scott Richter, Carl Barnhart	Integrating Logic BIST in VLSI Designs with Embedded Memories.	VTS	2000	DBLP DOI BibTeX RDF
10	Dennis Abts, Mike Roberts, David J. Lilja	A Balanced Approach to High-Level Verification: Performance Trade-Offs in Verifying Large-Scale Multiprocessors.	ICPP	2000	DBLP DOI BibTeX RDF
10	Thierry J.-F. Omnés, Thierry Franzetti, Francky Catthoor	Interactive co-design of high throughput embedded multimedia.	DAC	2000	DBLP DOI BibTeX RDF
10	Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy	Survival strategies for mixed-signal systems-on-chip (panel session).	DAC	2000	DBLP DOI BibTeX RDF
10	Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens	High-level simulation of substrate noise generation including power supply noise coupling.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
10	Krzysztof Kuchcinski	Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints.	DATE	1999	DBLP DOI BibTeX RDF
10	Kiyoshi Nikawa, Shoji Inoue, Kazuyuki Morimoto, Shinya Sone	Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
10	Nikil D. Dutt, Brian Kelley	On the rapid prototyping and design of a wireless communication system on a chip (abstract).	ICCAD	1999	DBLP DOI BibTeX RDF
10	Alexander Schwarz, Bärbel Mertsching, M. Brucke, Wolfgang Nebel, Jürgen Tchorz, Birger Kollmeier	Implementing a Quantitative Model for the "Effective" Signal Processing in the Auditory System on a Dedicated Digital VLSI Hardware.	EUROMICRO	1999	DBLP DOI BibTeX RDF
10	Krzysztof Kuchcinski	Synthesis of Distributed Embedded Systems.	EUROMICRO	1999	DBLP DOI BibTeX RDF
10	Per Lindgren, Rolf Drechsler, Bernd Becker 0001	Synthesis of Pseudo Kronecker Lattice Diagrams.	ICCD	1999	DBLP DOI BibTeX RDF
10	Martin Engels, Bernhard Hoppe, Hermann Meuth, Reiner Peters	A single chip 200 MHz digital correlation system for laser spectroscopy with 512 correlation channels.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
10	Antonio García 0001, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor	RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Kanad Chakraborty, Natesan Venkateswaran	Congestion Mitigation During Placement.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
10	Robert C. Aitken	Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage.	VTS	1999	DBLP DOI BibTeX RDF
10	Fabien Clermidy, Thierry Collette, Michael Nicolaidis	A New Placement Algorithm Dedicated to Parallel Computers: Bases and Application.	PRDC	1999	DBLP DOI BibTeX RDF
10	S. Ramanathan, V. Visvanathan, S. K. Nandy 0001	Synthesis of Configurable Architectures for DSP Algorithms.	VLSI Design	1999	DBLP DOI BibTeX RDF
10	D. Craig Wilcox, Lyndon G. Pierson, Perry J. Robertson, Edward L. Witzke, Karl Gass	A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond.	CHES	1999	DBLP DOI BibTeX RDF
10	Srihari Varada, Vitalice K. Oduol, A. Shelat	Data Flow and Buffer Management in Multi-Channel Data Link Controller.	LCN	1999	DBLP DOI BibTeX RDF	TDM networks, Data flow management, ASIC, Buffer management
10	Dave Johnson 0003, Venkatesh Akella, Bret Stott	Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
10	Ti-Yen Yen, Wayne H. Wolf	Performance Estimation for Real-Time Distributed Embedded Systems.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	distributed systems, real-time systems, Embedded systems, performance analysis, periodic tasks
10	John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak	Efficiently Supporting Fault-Tolerance in FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF	fault-tolerance, FPGA
10	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop	Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems.	DATE	1998	DBLP DOI BibTeX RDF	Real time systems, Embedded systems, System design, Design automation, Performance estimation, Hardware/Software co-design, Process scheduling, System-level synthesis
10	M. Svajda, B. Straka, Hans A. R. Manhaeve	IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit.	DATE	1998	DBLP DOI BibTeX RDF
10	Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx	Simulation of ATM Switches Using Dynamically Reconfigurable FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
10	Michael Eisenring, Jürgen Teich	Interfacing Hardware and Software.	FPL	1998	DBLP DOI BibTeX RDF	automatic interface synthesis, low power design, rapid prototyping, hardware/software codesign
10	Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch	A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
10	Azra Rashid, Jason Leonard, William H. Mangione-Smith	Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability.	FCCM	1998	DBLP DOI BibTeX RDF
10	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop	Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems.	EUROMICRO	1998	DBLP DOI BibTeX RDF
10	Alex Orailoglu	Graceful Degradation in Synthesis of VLSI ICs.	DFT	1998	DBLP DOI BibTeX RDF	permanent fault resilience, high level synthesis of fault-tolerant ICs, Safety Critical Systems, graceful degradation, Fault-tolerant microarchitectures
10	Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv	User Defined Coverage - A Tool Supported Methodology for Design Verification.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
10	Laurent Freund, Michel Israël, Frédéric Rousseau 0001, J. M. Bergé, Michel Auguin, Cécile Belleudy, Guy Gogniat	A codesign experiment in acoustic echo cancellation GMDF.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	communications, codesign, HW/SW partitioning
10	Jie Gong, Daniel Gajski, Smita Bakshi	Model refinement for hardware-software codesign.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	sofware-hardware codesign, functional model, implementation model, model refinement
10	Allan H. Anderson, Gary A. Shaw	Executable Requirements and Specifications.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
10	Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar	A scheme for multiple on-chip signature checking for embedded SRAMs.	ED&TC	1997	DBLP DOI BibTeX RDF
10	Viera Stopjaková, Hans A. R. Manhaeve	CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
10	Stefan Sjöholm, Lennart Lindh	The need for Co-simulation in ASIC-verification.	EUROMICRO	1997	DBLP DOI BibTeX RDF
10	Timo Koskinen, Peter Y. K. Cheung	Hierarchical tolerance analysis using statistical behavioral models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
10	Sandi Habinc, Peter Sinander	Using VHDL for Board Level Simulation.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
10	Mick Tegethoff, Tom Chen 0001	Sensitivity Analysis of Critical Parameters in Board Test.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
10	Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess	A Constructive Method for Exploiting Code Motion.	ISSS	1996	DBLP DOI BibTeX RDF	conditional resource sharing, scheduling, high-level synthesis, code generation, conditionals, Code motion, search space pruning
10	Mark J. Bentum, Martin M. Samsom, Cornelis H. Slump	A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
10	Daniel D. Gajski, Frank Vahid	Specification and Design of Embedded Hardware-Software Systems.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF
10	Jean Paul Calvez, Olivier Pasquier	Performance assessment of embedded Hw/Sw systems.	ICCD	1995	DBLP DOI BibTeX RDF	embedded Hw/Sw systems, VLSI components, heterogeneous multiprocessor architectures, complex real-time applications, performance indexes, real-time event occurrences, software tasks, hardware functions, real-time performance analyzer, MCSE methodology, performance evaluation, real-time systems, VLSI, systems analysis, application specific integrated circuits, ASIC, performance assessment, event trace
10	Pierpaolo Baglietto, Massimo Maresca, A. Migliaro, Mauro Migliardi	Parallel Implementation of the Full Search Block Matching Algorithm for Motion Estimation.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI, Motion Estimation, Video Coding, Processor Array
10	Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski	A chip set for pipeline and parallel pipeline FFT architectures.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
10	Anthony M. Hill, Sung-Mo Kang	Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits.	PPSN	1994	DBLP DOI BibTeX RDF
10	David Karchmer, Jonathan Rose	Definition and solution of the memory packing problem for field-programmable systems.	ICCAD	1994	DBLP DOI BibTeX RDF
10	I. D. Dear, Chryssa Dislis, Anthony P. Ambler, J. H. Dick	Economic Effects in Design and Test.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
10	David A. Fechser	A Methodology for Debugging ASIC Prototypes in the Field.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
10	Giovanni De Micheli, David C. Ku, Frédéric Mailhot 0001, Thomas K. Truong	The Olympus Synthesis System.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
10	Tuomo Tikkanen, Timo Lappänen, Jorma Kivelä	Structured analysis and VHDL in embedded ASIC design and verification.	EURO-DAC	1990	DBLP DOI BibTeX RDF
10	Kin-Hong Lee, Kwong-Sak Leung, Sin Man Cheang	The Implementation of A PC-Based List Processor for Symbolic Computation.	DISCO	1990	DBLP DOI BibTeX RDF
10	Wayne H. Wolf	The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines.	DAC	1990	DBLP DOI BibTeX RDF
10	Michael A. B. Jackson, Arvind Srinivasan 0004, Ernest S. Kuh	Clock Routing for High-Performance ICs.	DAC	1990	DBLP DOI BibTeX RDF
10	Mitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli	ORCA a Sea-of-Gates Place and Route System.	DAC	1989	DBLP DOI BibTeX RDF
10	Brian Apgar, Bret Bersack, Abraham Mammen	A display system for the Stellar graphics supercomputer model GS1000.	SIGGRAPH	1988	DBLP DOI BibTeX RDF
10	E. Berkcan, Manuel A. d'Abreu, W. Laughton	Analog Compilation Based on Successive Decompositions.	DAC	1988	DBLP BibTeX RDF