Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | YongHwan Kim, Sanghoon Kwak, Taewhan Kim |
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 17(4), pp. 43:1-43:29, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Mostafa Rahimi Azghadi, Omid Kavehei, Keivan Navi |
A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1204.2048, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
16 | |
A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1204.1845, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
16 | Rajkumar Sarma, Veerati Raju |
Design and Performance Analysis of hybrid adders for high speed arithmetic circuit ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1207.2840, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
16 | Pradeep S. Nair, Savithra Eratne, Eugene B. John |
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 8(4), pp. 464-471, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Taskin Koçak, Preeti Patil |
Design and implementation of high-performance high-valency ling adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012, pp. 224-229, 2012, IEEE, 978-1-4673-1187-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas |
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012, pp. 225-230, 2012, IEEE Computer Society, 978-1-4673-2234-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Shashikant Sharma, Manisha Pattanaik, Balwinder Raj |
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: International Symposium on Electronic System Design, ISEDs 2012, Kolkata, India, December 19-22, 2012, pp. 272-275, 2012, IEEE, 978-1-4673-4704-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | R. Uma, Jebashini Ponnian |
Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: International Symposium on Electronic System Design, ISEDs 2012, Kolkata, India, December 19-22, 2012, pp. 111-115, 2012, IEEE, 978-1-4673-4704-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Fateme Naderpour, Seok-Bum Ko |
Improved Design of High-Radix Signed-Digit Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: International Symposium on Electronic System Design, ISEDs 2012, Kolkata, India, December 19-22, 2012, pp. 107-110, 2012, IEEE, 978-1-4673-4704-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Kiyoung Kim, Taewhan Kim |
Algorithm for synthesizing design context-aware fast carry-skip adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, pp. 795-800, 2012, IEEE, 978-1-4673-0770-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Carl Ingemarsson, Petter Kallstrom, Oscar Gustafsson |
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 71-74, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Weiqiang Liu 0001, Máire O'Neill, Earl E. Swartzlander Jr. |
A review of QCA adders and metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers, ACSCC 2012, Pacific Grove, CA, USA, November 4-7, 2012, pp. 747-751, 2012, IEEE, 978-1-4673-5050-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky |
Modeling and synthesis of quality-energy optimal approximate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, pp. 728-735, 2012, ACM, 978-1-4577-1398-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Babak Zamanlooy, Ashley Novak, Mitra Mirhassani |
Complexity Study of the Continuous Valued Number System Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012, Victoria, BC, Canada, May 14-16, 2012, pp. 116-121, 2012, IEEE Computer Society, 978-1-4673-0908-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Stevo D. Bailey, Mircea R. Stan |
A new taxonomy for reconfigurable prefix adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 1227-1230, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Michael B. Sullivan 0001, Earl E. Swartzlander Jr. |
Long Residue Checking for Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft, The Netherlands, July 9-11, 2012, pp. 177-180, 2012, IEEE Computer Society, 978-1-4673-2243-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Tso-Bing Juang, Hsin-Hao Peng, Han-Lung Kuo |
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012, pp. 239-242, 2012, IEEE, 978-1-4673-2989-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa |
Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012, pp. 603-606, 2012, IEEE, 978-1-4577-1728-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Optimized design of parallel carry-select adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 44(1), pp. 62-74, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mariano Aguirre-Hernandez, Mónico Linares Aranda |
CMOS Full-Adders for Energy-Efficient Arithmetic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(4), pp. 718-721, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Swaroop Ghosh, Kaushik Roy 0001 |
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(8), pp. 1504-1507, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos |
On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 30(6), pp. 1445-1461, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mónico Linares Aranda, Mariano Aguirre-Hernandez |
New High-Performance Full Adders Using an Alternative Logic Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computación y Sistemas ![In: Computación y Sistemas 14(3), 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
16 | Keivan Navi, Akbar Doostaregan, Mohammad Hossein Moaiyeri, Omid Hashemipour |
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fuzzy Sets Syst. ![In: Fuzzy Sets Syst. 185(1), pp. 111-124, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Dong Shi, Ya Jun Yu |
Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1), pp. 126-136, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Alexey Gutin, Philip Jacob 0001, Michael Chu, Paul M. Belemjian, Mitchell R. LeRoy, Russell P. Kraft, John F. McDonald 0001 |
Carry Chains for Ultra High-Speed SiGe HBT Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9), pp. 2201-2210, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Jeff Rebacz, Erdal Oruklu, Jafar Saniie |
Fast Signed-Digit Multi-operand Decimal Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. ![In: Circuits Syst. 2(3), pp. 225-236, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo |
Area-efficient 3-input decimal adders using simplified carry and sum vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011, pp. 25-30, 2011, IEEE, 978-1-4577-0171-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Hong Diep Nguyen, Bogdan Pasca 0001, Thomas B. Preußer |
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 232-237, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
carry-chain, carry-select, carry-increment, FPGA, addition |
16 | Saeid Gorgin 0001, Ghassem Jaberipur |
A Family of High Radix Signed Digit Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011, pp. 112-120, 2011, IEEE Computer Society, 978-0-7695-4318-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Neil Burgess |
Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011, pp. 103-111, 2011, IEEE Computer Society, 978-0-7695-4318-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mathias Faust, Chip-Hong Chang |
Low error bit width reduction for structural adders of FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011, pp. 713-716, 2011, IEEE, 978-1-4577-0617-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Ahmed Fawaz, Ameen Jaber, Ali Kassem 0003, Ali Chehab, Ayman I. Kayssi |
Assessing testing techniques for resistive-open defects in nanometer CMOS adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 165-168, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Matthew Keeter, David Money Harris, Andrew Macrae, Rebecca Glick, Madeleine Ong, Justin Schauer |
Implementation of 32-bit Ling and Jackson adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers, ACSCC 2011, Pacific Grove, CA, USA, November 6-9, 2011, pp. 170-175, 2011, IEEE, 978-1-4673-0321-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Ghassem Jaberipur, Behrooz Parhami, Saeed Nejati |
On building general modular adders from standard binary arithmetic components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers, ACSCC 2011, Pacific Grove, CA, USA, November 6-9, 2011, pp. 154-159, 2011, IEEE, 978-1-4673-0321-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | K. S. Vasundara Patel, K. S. Gurumurthy |
Design of High Performance Quaternary Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011, Tuusula, Finland, May 23-25, 2011, pp. 22-26, 2011, IEEE Computer Society, 978-0-7695-4405-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Akansha Baliga, Deepa Yagain |
Design of High Speed Adders Using CMOS and Transmission Gates in Submicron Technology: A Comparative Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: 4th International Conference on Emerging Trends in Engineering and Technology, ICETET 2011, Mauritius, November 18-20, 2011, pp. 284-289, 2011, IEEE Computer Society, 978-0-7695-4561-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem |
An approach to energy-error tradeoffs in approximate ripple carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 211-216, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
16 | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 217-222, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
16 | Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy 0001 |
IMPACT: imprecise adders for low-power approximate computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 409-414, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
16 | Kai Du, Peter J. Varman, Kartik Mohanram |
Static window addition: A new paradigm for the design of variable latency adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011, pp. 455-456, 2011, IEEE Computer Society, 978-1-4577-1953-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Carlos Diego Moreno-Moreno, Pilar Martínez, Francisco Bellido 0001, Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002 |
Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IT Revolutions ![In: IT Revolutions - Third International ICST Conference, Córdoba, Spain, March 23-25, 2011, Revised Selected Papers, pp. 237-248, 2011, Springer, 978-3-642-32303-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Jinghang Liang, Jie Han 0001, Fabrizio Lombardi |
On the Reliable Performance of Sequential Adders for Soft Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 3-10, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | H. Boddapati, A. Naregalkar, B. L. Raju |
Novel asynchronous adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25 - 26, 2011, pp. 1055-1058, 2011, ACM, 978-1-4503-0449-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Manoj Kumar 0005, Sujata Pandey, Sandeep Kumar Arya |
Design of CMOS Energy Efficient Single Bit Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPAGC ![In: High Performance Architecture and Grid Computing - International Conference, HPAGC 2011, Chandigarh, India, July 19-20, 2011. Proceedings, pp. 159-168, 2011, Springer, 978-3-642-22576-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija |
Energy-Efficient Design Methodologies: High-Performance VLSI Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 45(6), pp. 1220-1233, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | K. Scott Hemmert, Keith D. Underwood |
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 3(3), pp. 11:1-11:30, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou |
Fast modulo 2n+1 multi-operand adders and residue generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 43(1), pp. 42-48, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Gery Bioul, Martín Vázquez 0001, Jean-Pierre Deschamps, Gustavo Sutter |
High-Speed FPGA 10's Complement Adders-Subtractors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2010, pp. 219764:1-219764:14, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Jeff Jones, Andrew Adamatzky |
Towards Physarum binary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biosyst. ![In: Biosyst. 101(1), pp. 51-58, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Naofumi Takagi, Masamitsu Tanaka |
Comparisons of Synchronous-Clocking SFQ Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 93-C(4), pp. 429-434, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | V. P. Suprun, D. A. Gorodetskii |
Synthesis of n-operand modulo-three adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autom. Control. Comput. Sci. ![In: Autom. Control. Comput. Sci. 44(3), pp. 171-177, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1008.3344, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Anindya Das, Ifat Jahangir, Masud Hasan |
On the Design and Analysis of Quaternary Serial and Parallel Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1009.2622, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1008.3311, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Jeff Jones, Andrew Adamatzky |
Towards Physarum Binary Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1005.2303, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Janusz Biernat |
Fast fault-tolerant adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Crit. Comput. Based Syst. ![In: Int. J. Crit. Comput. Based Syst. 1(1/2/3), pp. 117-127, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Ismo Hänninen, Jarmo Takala |
Binary Adders on Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 58(1), pp. 87-103, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Feng Liu 0029, Qingping Tan, Gang Chen 0004 |
Formal proof of prefix adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Comput. Model. ![In: Math. Comput. Model. 52(1-2), pp. 191-199, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Dietmar Fey, Steffen Limmer |
Unconventional Computing - Reversible Signed Digit Adders for Future Nanocomputing Devices (Unkonventionelles Rechnen - reversible Addierer für künftiges Nanocomputing). ![Search on Bibsonomy](Pics/bibsonomy.png) |
it Inf. Technol. ![In: it Inf. Technol. 52(3), pp. 147-152, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Abdoul Rjoub, Al-Mamoon Al-Othman |
The Influence of the Nanometer Technology on Performance of CPL Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. ![In: J. Comput. 5(3), pp. 337-344, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Haridimos T. Vergos |
A Family of Area-Time Efficient Modulo 2n+1 Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 442-443, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mónico Linares Aranda, Ramón Báez, Oscar González-Díaz |
Hybrid adders for high-speed arithmetic circuits: A comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCE ![In: Proceedings of the 7th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2010 (Formerly known as ICEEE), September 8-10, 2010, Tuxtla Gutierrez, Mexico, pp. 546-549, 2010, IEEE, 978-1-4244-7312-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu |
A general mathematical model of probabilistic ripple-carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 1100-1105, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca 0001 |
Pipelined FPGA Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy, pp. 422-427, 2010, IEEE Computer Society, 978-0-7695-4179-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Savithra Eratne, Claudia Romo, Eugene John |
Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2010 International Conference on Computer Design, CDES 2010, July 12-15, 2010, Las Vegas Nevada, USA, pp. 61-66, 2010, CSREA Press, 1-60132-135-X. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem, Avani Devarasetty, Phani Deepak Parasuramuni |
Optimizing energy to minimize errors in dataflow graphs using approximate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010, pp. 177-186, 2010, ACM, 978-1-60558-903-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici |
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 1715-1718, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Feng Liu 0029, QingPing Tan, Xiaoyu Song, Gang Chen 0004 |
Formal Proof for a General Architecture of Hybrid Prefix/Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (1) ![In: Algorithms and Architectures for Parallel Processing, 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings. Part I, pp. 193-204, 2010, Springer, 978-3-642-13118-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Santosh Ghosh, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury |
High speed Fp multipliers and adders on FPGA platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, DASIP 2010, Edinburgh, Scotland, UK, October 26-28, 2010, Electronic Chips & Systems design Initiative, ECSI, pp. 21-26, 2010, IEEE, 978-1-4244-8735-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Yongpan Liu, Yinan Sun, Yihao Zhu, Huazhong Yang |
Design methodology of variable latency adders with multistage function speculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 824-830, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu |
Modeling of Probabilistic Ripple-Carry Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 201-206, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ripple-carry adder, noies modeling, error propagation, Probabilistic computation |
16 | Tso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan |
Area-efficient parallel-prefix Ling adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 736-739, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Padmanabhan Balasubramanian |
Self-Timed Logic and the Design of Self-Timed Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
16 | Snorre Aunet, Hans Kristian Otnes Berge |
Statistical Simulations on Perceptron-Based Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Artificial Intelligence ![In: Encyclopedia of Artificial Intelligence (3 Volumes), pp. 1474-1481, 2009, IGI Global, 9781599048499. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
16 | Radu Zlatanovici, Sean Kao, Borivoje Nikolic |
Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 44(2), pp. 569-583, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Michael Kirkedal Thomsen, Holger Bock Axelsen |
Parallelization of Reversible Ripple-Carry Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Process. Lett. ![In: Parallel Process. Lett. 19(2), pp. 205-222, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Kyo Takahashi, Shingo Sato, Tadamichi Kudo, Yoshitaka Tsunekawa |
High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2), pp. 633-637, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Sanghoon Kwak, Jeong-Gun Lee, Eun-Gu Jung, Dongsoo Har, Milos D. Ercegovac, Jeong-A Lee |
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 18(4), pp. 787-800, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mary D. Pulukuri, Charles E. Stroud |
On Built-In Self-Test for Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 25(6), pp. 343-346, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Keivan Navi, Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Omid Hashemipour, Babak Mazloom Nezhad |
Two new low-power Full Adders based on majority-not gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(1), pp. 126-130, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Wancheng Zhang, Nan-Jian Wu |
Compact non-binary fast adders using single-electron devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(8), pp. 1244-1254, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello |
Designing High-Speed Adders in Power-Constrained Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 56-II(2), pp. 172-176, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Keivan Navi |
Two New Low-Power and High-Performance Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. ![In: J. Comput. 4(2), pp. 119-126, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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16 | Heejoung Park, Yuki Yamanashi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Akira Fujimaki |
Design of fast digit-serial adders using SFQ logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(19), pp. 1408-1413, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Feng Liu 0029, Fariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed, Gang Chen 0004, Xiaoyu Song, QingPing Tan |
A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece, pp. 281-286, 2009, IEEE Computer Society, 978-0-7695-3782-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Martín Vázquez 0001, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps |
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 42-47, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
BCD, add/subtract, addtion, FPGA, subtraction, decimal arithmetic |
16 | Ghassem Jaberipur, Behrooz Parhami |
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009, pp. 57-64, 2009, IEEE Computer Society, 978-0-7695-3670-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Chung-Kuan Cheng |
Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009, pp. 212, 2009, IEEE Computer Society, 978-0-7695-3670-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | R. P. P. Singh, Parveen Kumar, Balwinder Singh |
Performance Analysis of Fast Adders Using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARTCom ![In: ARTCom 2009, International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India, 27-28 October 2009, pp. 189-193, 2009, IEEE Computer Society, 978-0-7695-3845-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Ching Zhou, Bruce M. Fleischer, Michael Gschwind, Ruchir Puri |
64-bit prefix adders: Power-efficient topologies and design solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings, pp. 179-182, 2009, IEEE, 978-1-4244-4071-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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16 | Masaki Murozuka, Kazumasa Ikeura, Fumiyuki Adachi, Kazuya Machida, Takao Waho |
Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 245-249, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mathias Faust, Chip-Hong Chang |
Optimization of Structural Adders in Fixed Coefficient Transposed Direct Form FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 2185-2188, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu |
Efficient approaches for designing reversible Binary Coded Decimal adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 39(12), pp. 1693-1703, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Zine Abid, Hayssam El-Razouk, Dalia A. El-Dib |
Low power multipliers based on new hybrid full adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 39(12), pp. 1509-1515, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Keivan Navi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Babak Mazloom Nezhad, Omid Hashemipour, K. Shams |
Ultra high speed Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 5(18), pp. 744-749, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Michael Kirkedal Thomsen, Robert Glück |
Optimized reversible binary-coded decimal adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 54(7), pp. 697-706, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Nobutaka Kito, Naofumi Takagi |
Level-Testability of Multi-operand Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 260-262, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou |
Efficient modulo 2n + 1 multi-operand adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 694-697, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|