Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Shadi T. Khasawneh, Kanad Ghose |
An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija |
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Gregorio Cappuccino, Andrea Pugliese 0002, Giuseppe Cocorullo |
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Daniel González, Luis Parrilla 0001, Antonio García 0001, Encarnación Castillo, Antonio Lloris-Ruíz |
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Vassilis Paliouras, Johan Vounckx, Diederik Verkest (eds.) |
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Miguel Casas-Sanchez, Jose Rizo-Morente, Chris J. Bleakley |
Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSP. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Rohdenburg, Volker Hohmann, Birger Kollmeier |
Tutorial Hearing Aid Algorithms. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine |
Temperature Dependency in UDSM Process. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo |
Logic-Level Fast Current Simulation for Digital CMOS Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | David Rios-Arambula, Aurélien Buhrig, Marc Renaudin |
Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Armin Wellig, Julien Zory |
Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Yici Cai, Bin Liu 0007, Qiang Zhou 0001, Xianlong Hong |
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine |
A Method to Design Compact Dual-rail Asynchronous Primitives. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Jean-Félix Perotto, Stefan Cserveny |
Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | William R. Roberts, Dimitrios Velenis |
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis |
Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Theodoros Giannopoulos, Vassilis Paliouras |
Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan |
Efficient Simulation of Power/Ground Networks with Package and Vias. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Wolfgang Nebel, Bärbel Mertsching, Birger Kollmeier |
Digital Hearing Aids: Challenges and Solutions for Ultra Low Power. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Eduardo Tavares, Raimundo S. Barreto, Paulo Romero Martins Maciel, Meuse N. Oliveira Jr., Adilson Arcoverde, Gabriel Alves, Ricardo Massa Ferreira Lima, Leonardo Barros, Arthur Bessa |
An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
Fast Low-Power 64-Bit Modular Hybrid Adder. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Ashutosh Chakraborty, Enrico Macii, Massimo Poncino |
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Hyun-Ho Kim, Jung Hee Kim, Yong-hyeog Kang, Young Ik Eom |
An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Jan M. Rabaey |
Traveling the Wild Frontier of Ultra Low-Power Design. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Francisco-Javier Veredas, Jordi Carrabina |
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Giorgos Dimitrakopoulos, Dimitris Nikolos |
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard |
Speed Indicators for Circuit Optimization. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Haralambos Michail, Athanasios Kakarountas, George N. Selimis, Costas E. Goutis |
Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Tajana Simunic, Kresimir Mihic, Giovanni De Micheli |
Optimization of Reliability and Power Consumption in Systems on a Chip. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Pankaj Golani, Peter A. Beerel |
Back Annotation in High Speed Asynchronous Design. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor |
Systematic Preprocessing of Data Dependent Constructs for Embedded Systems. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat |
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
Differential Pull Down Networks, Side-channel attack, Differential Power Analysis, Binary Decision Diagrams |
1 | Yuanlin Lu, Vishwani D. Agrawal |
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Josep Rius 0001, José Pineda de Gyvez, Maurice Meijer |
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Ricardo Massa Ferreira Lima, Angelo Ribeiro, César A. L. de Oliveira, Adilson Arcoverde, Raimundo S. Barreto, Eduardo Tavares, Leonardo Amorim |
A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel |
A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto 0001, Michael C. Huang 0001, Francisco Tirado |
A Power-Efficient and Scalable Load-Store Queue Design. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001 |
Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Radu Zlatanovici, Borivoje Nikolic |
Power - Performance Optimization for Custom Digital Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark |
Statistical Critical Path Analysis Considering Correlations. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Howard Chen 0001, Louis Hsu |
Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Alexis De Vos, Yvan Van Rentergem |
Power Consumption in Reversible Logic Addressed by a Ramp Voltage. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Huizhan Yi, Xuejun Yang |
Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Amjad Mohsen, Richard Hofmann |
Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | José Manuel Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, Jose Manuel Mendias |
Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Eckhard Grass, Frank Winkler 0001, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz |
Enhanced GALS Techniques for Datapath Applications. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Mariagrazia Graziano, Cristiano Forzan, Davide Pandini |
Power Supply Selective Mapping for Accurate Timing Analysis. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Odysseas G. Koufopavlou, George N. Selimis, Nicolas Sklavos 0001, Paris Kitsos |
Cryptography: Circuits and Systems Approach. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Roshan Weerasekera, Li-Rong Zheng 0001, Dinesh Pamunuwa, Hannu Tenhunen |
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura |
Dynamic Instruction Cascading on GALS Microprocessors. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Siobhán Launders, Colin Doyle, Wesley Cooper |
Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis 0001, Roberto Zafalon |
Energy-Aware System-on-Chip for 5 GHz Wireless LANs. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Miodrag Vujkovic, David Wadkins, Carl Sechen |
Efficient Post-layout Power-Delay Curve Generation. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Vasily G. Moshnyaga, Eiji Morikawa |
Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar |
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Hamid Reza Sadr M. N |
A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
Differential transconductors, negative resistors, analog circuits and filters, widely tunable circuits, GHz range frequencies, continuous-time filters, Q-enhanced active filters, Gm-C filters, low power, RF, VCO, low noise |
1 | Thomas Eisenbach, Bärbel Mertsching, Nikolaus Voß, Frank Schmidtmeier |
Optimization of Modules for Digital Audio Processing. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Babak Salamat, Amirali Baniasadi |
Area-Aware Pipeline Gating for Embedded Processors. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev |
PSK Signalling on NoC Buses. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Prassanna Sithambaram, Alberto Macii, Enrico Macii |
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Ireneusz Brzozowski, Andrzej Kos |
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele |
The Optimal Wire Order for Low Power CMOS. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Magdy A. Bayoumi |
Wireless Sensor Networks: A New Life Paradigm. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Bécharia Nadji |
Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
Anodic oxidation, Pure water, Fixed Charges, interface States density, Si/SiO2, Electrical characterisation, MOS Structures, Fowler-Nordheim tunnelling |
1 | Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel |
Power-Clock Gating in Adiabatic Logic Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | José Luis Rosselló, Sebastià A. Bota, Jaume Segura 0001 |
Compact Static Power Model of Complex CMOS Gates. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Nabil Badereddine, Patrick Girard 0001, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault |
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo |
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Yijun Liu, Stephen B. Furber |
The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Arne Schulz, Wolfgang Nebel |
Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Ali Manzak |
Temperature Aware Datapath Scheduling. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat |
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Francisco de Toro, Raúl Jiménez, Manuel Sanchez-Raya, Julio Ortega 0001 |
Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Sung-Bae Park |
DLV (Deep Low Voltage): Circuits and Devices. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Bert Geelen, Gauthier Lafruit, Vissarion Ferentinos, Rudy Lauwereins, Diederik Verkest |
Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Konstantina Karagianni, Vassilis Paliouras |
Low-Power Aspects of Nonlinear Signal Processing. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino |
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne |
Performance Metric Based Optimization Protocol. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Ana Rusu, Alexei Borodenkov, Mohammed Ismail 0001, Hannu Tenhunen |
Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis |
A Novel Constant-Time Fault-Secure Binary Counter. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Kenny Johansson, Oscar Gustafsson, Lars Wanhammar |
Power Estimation for Ripple-Carry Adders with Correlated Input Data. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan |
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Enrico Macii, Odysseas G. Koufopavlou, Vassilis Paliouras (eds.) |
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Jean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli |
Embedded EEPROM Speed Optimization Using System Power Supply Resources. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Millán 0001, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa |
Signal Sampling Based Transition Modeling for Digital Gates Characterization. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Yin Wang, Xianlong Hong, Tong Jing, Yang Yang 0040, Xiaodong Hu 0001, Guiying Yan |
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Dimitrios Velenis, Eby G. Friedman |
Buffer Sizing for Crosstalk Induced Delay Uncertainty. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
Pipelines in Dynamic Dual-Rail Circuits. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Francesco Pessolano, R. I. M. P. Meijer |
A 260ps Quasi-static ALU in 90nm CMOS. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Carlo Brandolese, William Fornaciari, Fabio Salice |
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow |
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Mircea R. Stan, Yan Zhang 0028 |
Perfect 3-Limited-Weight Code for Low Power I/O. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Carlo Dallavalle |
Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson |
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Leonardo Valencia |
Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Alexander Maili, Damian Dalton, Christian Steger |
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|