Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | YongHwan Kim, Sanghoon Kwak, Taewhan Kim |
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint. |
ACM Trans. Design Autom. Electr. Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Mostafa Rahimi Azghadi, Omid Kavehei, Keivan Navi |
A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders |
CoRR |
2012 |
DBLP BibTeX RDF |
|
16 | |
A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders |
CoRR |
2012 |
DBLP BibTeX RDF |
|
16 | Rajkumar Sarma, Veerati Raju |
Design and Performance Analysis of hybrid adders for high speed arithmetic circuit |
CoRR |
2012 |
DBLP BibTeX RDF |
|
16 | Pradeep S. Nair, Savithra Eratne, Eugene B. John |
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance. |
J. Low Power Electron. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Taskin Koçak, Preeti Patil |
Design and implementation of high-performance high-valency ling adders. |
DDECS |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas |
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. |
ISVLSI |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Shashikant Sharma, Manisha Pattanaik, Balwinder Raj |
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. |
ISED |
2012 |
DBLP DOI BibTeX RDF |
|
16 | R. Uma, Jebashini Ponnian |
Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance Analysis. |
ISED |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Fateme Naderpour, Seok-Bum Ko |
Improved Design of High-Radix Signed-Digit Adders. |
ISED |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Kiyoung Kim, Taewhan Kim |
Algorithm for synthesizing design context-aware fast carry-skip adders. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Carl Ingemarsson, Petter Kallstrom, Oscar Gustafsson |
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Weiqiang Liu 0001, Máire O'Neill, Earl E. Swartzlander Jr. |
A review of QCA adders and metrics. |
ACSCC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky |
Modeling and synthesis of quality-energy optimal approximate adders. |
ICCAD |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Babak Zamanlooy, Ashley Novak, Mitra Mirhassani |
Complexity Study of the Continuous Valued Number System Adders. |
ISMVL |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Stevo D. Bailey, Mircea R. Stan |
A new taxonomy for reconfigurable prefix adders. |
ISCAS |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Michael B. Sullivan 0001, Earl E. Swartzlander Jr. |
Long Residue Checking for Adders. |
ASAP |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Tso-Bing Juang, Hsin-Hao Peng, Han-Lung Kuo |
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders. |
ISOCC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa |
Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. |
APCCAS |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Optimized design of parallel carry-select adders. |
Integr. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mariano Aguirre-Hernandez, Mónico Linares Aranda |
CMOS Full-Adders for Energy-Efficient Arithmetic Applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Swaroop Ghosh, Kaushik Roy 0001 |
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking. |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos |
On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. |
Circuits Syst. Signal Process. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mónico Linares Aranda, Mariano Aguirre-Hernandez |
New High-Performance Full Adders Using an Alternative Logic Structure. |
Computación y Sistemas |
2011 |
DBLP BibTeX RDF |
|
16 | Keivan Navi, Akbar Doostaregan, Mohammad Hossein Moaiyeri, Omid Hashemipour |
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders. |
Fuzzy Sets Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Dong Shi, Ya Jun Yu |
Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Alexey Gutin, Philip Jacob 0001, Michael Chu, Paul M. Belemjian, Mitchell R. LeRoy, Russell P. Kraft, John F. McDonald 0001 |
Carry Chains for Ultra High-Speed SiGe HBT Adders. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Jeff Rebacz, Erdal Oruklu, Jafar Saniie |
Fast Signed-Digit Multi-operand Decimal Adders. |
Circuits Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo |
Area-efficient 3-input decimal adders using simplified carry and sum vectors. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Hong Diep Nguyen, Bogdan Pasca 0001, Thomas B. Preußer |
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
carry-chain, carry-select, carry-increment, FPGA, addition |
16 | Saeid Gorgin 0001, Ghassem Jaberipur |
A Family of High Radix Signed Digit Adders. |
IEEE Symposium on Computer Arithmetic |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Neil Burgess |
Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI. |
IEEE Symposium on Computer Arithmetic |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mathias Faust, Chip-Hong Chang |
Low error bit width reduction for structural adders of FIR filters. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Ahmed Fawaz, Ameen Jaber, Ali Kassem 0003, Ali Chehab, Ayman I. Kayssi |
Assessing testing techniques for resistive-open defects in nanometer CMOS adders. |
ICECS |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Matthew Keeter, David Money Harris, Andrew Macrae, Rebecca Glick, Madeleine Ong, Justin Schauer |
Implementation of 32-bit Ling and Jackson adders. |
ACSCC |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Ghassem Jaberipur, Behrooz Parhami, Saeed Nejati |
On building general modular adders from standard binary arithmetic components. |
ACSCC |
2011 |
DBLP DOI BibTeX RDF |
|
16 | K. S. Vasundara Patel, K. S. Gurumurthy |
Design of High Performance Quaternary Adders. |
ISMVL |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Akansha Baliga, Deepa Yagain |
Design of High Speed Adders Using CMOS and Transmission Gates in Submicron Technology: A Comparative Study. |
ICETET |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem |
An approach to energy-error tradeoffs in approximate ripple carry adders. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
16 | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
16 | Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy 0001 |
IMPACT: imprecise adders for low-power approximate computing. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
16 | Kai Du, Peter J. Varman, Kartik Mohanram |
Static window addition: A new paradigm for the design of variable latency adders. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Carlos Diego Moreno-Moreno, Pilar Martínez, Francisco Bellido 0001, Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002 |
Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers. |
IT Revolutions |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Jinghang Liang, Jie Han 0001, Fabrizio Lombardi |
On the Reliable Performance of Sequential Adders for Soft Computing. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
16 | H. Boddapati, A. Naregalkar, B. L. Raju |
Novel asynchronous adders. |
ICWET |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Manoj Kumar 0005, Sujata Pandey, Sandeep Kumar Arya |
Design of CMOS Energy Efficient Single Bit Full Adders. |
HPAGC |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija |
Energy-Efficient Design Methodologies: High-Performance VLSI Adders. |
IEEE J. Solid State Circuits |
2010 |
DBLP DOI BibTeX RDF |
|
16 | K. Scott Hemmert, Keith D. Underwood |
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs. |
ACM Trans. Reconfigurable Technol. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou |
Fast modulo 2n+1 multi-operand adders and residue generators. |
Integr. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Gery Bioul, Martín Vázquez 0001, Jean-Pierre Deschamps, Gustavo Sutter |
High-Speed FPGA 10's Complement Adders-Subtractors. |
Int. J. Reconfigurable Comput. |
2010 |
DBLP BibTeX RDF |
|
16 | Jeff Jones, Andrew Adamatzky |
Towards Physarum binary adders. |
Biosyst. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Naofumi Takagi, Masamitsu Tanaka |
Comparisons of Synchronous-Clocking SFQ Adders. |
IEICE Trans. Electron. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | V. P. Suprun, D. A. Gorodetskii |
Synthesis of n-operand modulo-three adders. |
Autom. Control. Comput. Sci. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders |
CoRR |
2010 |
DBLP BibTeX RDF |
|
16 | Anindya Das, Ifat Jahangir, Masud Hasan |
On the Design and Analysis of Quaternary Serial and Parallel Adders |
CoRR |
2010 |
DBLP BibTeX RDF |
|
16 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders |
CoRR |
2010 |
DBLP BibTeX RDF |
|
16 | Jeff Jones, Andrew Adamatzky |
Towards Physarum Binary Adders |
CoRR |
2010 |
DBLP BibTeX RDF |
|
16 | Janusz Biernat |
Fast fault-tolerant adders. |
Int. J. Crit. Comput. Based Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Ismo Hänninen, Jarmo Takala |
Binary Adders on Quantum-Dot Cellular Automata. |
J. Signal Process. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Feng Liu 0029, Qingping Tan, Gang Chen 0004 |
Formal proof of prefix adders. |
Math. Comput. Model. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Dietmar Fey, Steffen Limmer |
Unconventional Computing - Reversible Signed Digit Adders for Future Nanocomputing Devices (Unkonventionelles Rechnen - reversible Addierer für künftiges Nanocomputing). |
it Inf. Technol. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Abdoul Rjoub, Al-Mamoon Al-Othman |
The Influence of the Nanometer Technology on Performance of CPL Full Adders. |
J. Comput. |
2010 |
DBLP BibTeX RDF |
|
16 | Haridimos T. Vergos |
A Family of Area-Time Efficient Modulo 2n+1 Adders. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mónico Linares Aranda, Ramón Báez, Oscar González-Díaz |
Hybrid adders for high-speed arithmetic circuits: A comparison. |
CCE |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu |
A general mathematical model of probabilistic ripple-carry adders. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca 0001 |
Pipelined FPGA Adders. |
FPL |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Savithra Eratne, Claudia Romo, Eugene John |
Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. |
CDES |
2010 |
DBLP BibTeX RDF |
|
16 | Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem, Avani Devarasetty, Phani Deepak Parasuramuni |
Optimizing energy to minimize errors in dataflow graphs using approximate adders. |
CASES |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici |
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Feng Liu 0029, QingPing Tan, Xiaoyu Song, Gang Chen 0004 |
Formal Proof for a General Architecture of Hybrid Prefix/Carry-Select Adders. |
ICA3PP (1) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Santosh Ghosh, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury |
High speed Fp multipliers and adders on FPGA platform. |
DASIP |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Yongpan Liu, Yinan Sun, Yihao Zhu, Huazhong Yang |
Design methodology of variable latency adders with multistage function speculation. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu |
Modeling of Probabilistic Ripple-Carry Adders. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
ripple-carry adder, noies modeling, error propagation, Probabilistic computation |
16 | Tso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan |
Area-efficient parallel-prefix Ling adders. |
APCCAS |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Padmanabhan Balasubramanian |
Self-Timed Logic and the Design of Self-Timed Adders. |
|
2010 |
RDF |
|
16 | Snorre Aunet, Hans Kristian Otnes Berge |
Statistical Simulations on Perceptron-Based Adders. |
Encyclopedia of Artificial Intelligence |
2009 |
DBLP BibTeX RDF |
|
16 | Radu Zlatanovici, Sean Kao, Borivoje Nikolic |
Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example. |
IEEE J. Solid State Circuits |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Michael Kirkedal Thomsen, Holger Bock Axelsen |
Parallelization of Reversible Ripple-Carry Adders. |
Parallel Process. Lett. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Kyo Takahashi, Shingo Sato, Tadamichi Kudo, Yoshitaka Tsunekawa |
High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Sanghoon Kwak, Jeong-Gun Lee, Eun-Gu Jung, Dongsoo Har, Milos D. Ercegovac, Jeong-A Lee |
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming. |
J. Circuits Syst. Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mary D. Pulukuri, Charles E. Stroud |
On Built-In Self-Test for Adders. |
J. Electron. Test. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Keivan Navi, Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Omid Hashemipour, Babak Mazloom Nezhad |
Two new low-power Full Adders based on majority-not gates. |
Microelectron. J. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Wancheng Zhang, Nan-Jian Wu |
Compact non-binary fast adders using single-electron devices. |
Microelectron. J. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello |
Designing High-Speed Adders in Power-Constrained Environments. |
IEEE Trans. Circuits Syst. II Express Briefs |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Keivan Navi |
Two New Low-Power and High-Performance Full Adders. |
J. Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Heejoung Park, Yuki Yamanashi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Akira Fujimaki |
Design of fast digit-serial adders using SFQ logic circuits. |
IEICE Electron. Express |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Feng Liu 0029, Fariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed, Gang Chen 0004, Xiaoyu Song, QingPing Tan |
A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Martín Vázquez 0001, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps |
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
BCD, add/subtract, addtion, FPGA, subtraction, decimal arithmetic |
16 | Ghassem Jaberipur, Behrooz Parhami |
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues. |
IEEE Symposium on Computer Arithmetic |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Chung-Kuan Cheng |
Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders. |
IEEE Symposium on Computer Arithmetic |
2009 |
DBLP DOI BibTeX RDF |
|
16 | R. P. P. Singh, Parveen Kumar, Balwinder Singh |
Performance Analysis of Fast Adders Using VHDL. |
ARTCom |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Ching Zhou, Bruce M. Fleischer, Michael Gschwind, Ruchir Puri |
64-bit prefix adders: Power-efficient topologies and design solutions. |
CICC |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Masaki Murozuka, Kazumasa Ikeura, Fumiyuki Adachi, Kazuya Machida, Takao Waho |
Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mathias Faust, Chip-Hong Chang |
Optimization of Structural Adders in Fixed Coefficient Transposed Direct Form FIR Filters. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu |
Efficient approaches for designing reversible Binary Coded Decimal adders. |
Microelectron. J. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Zine Abid, Hayssam El-Razouk, Dalia A. El-Dib |
Low power multipliers based on new hybrid full adders. |
Microelectron. J. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Keivan Navi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Babak Mazloom Nezhad, Omid Hashemipour, K. Shams |
Ultra high speed Full Adders. |
IEICE Electron. Express |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Michael Kirkedal Thomsen, Robert Glück |
Optimized reversible binary-coded decimal adders. |
J. Syst. Archit. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Nobutaka Kito, Naofumi Takagi |
Level-Testability of Multi-operand Adders. |
ATS |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou |
Efficient modulo 2n + 1 multi-operand adders. |
ICECS |
2008 |
DBLP DOI BibTeX RDF |
|