Search results for "datapath"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Victor J. Lam, Kunle Olukotun	DCP: an algorithm for datapath/control partitioning of synthesizable RTL models.	ICCD	1998	DBLP DOI BibTeX RDF
17	Allen C.-H. Wu	Datapath Optimization Using Layout Information: An Empirical Study.	VLSI Design	1997	DBLP DOI BibTeX RDF
17	Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin	DP-Gen: a datapath generator for multiple-FPGA applications.	ASP-DAC	1997	DBLP DOI BibTeX RDF
17	Masayuki Yamaguchi, Akihisa Yamada 0001, Toshihiro Nakaoka, Takashi Kambe	Architecture evaluation based on the datapath structure and parallel constraint.	ASP-DAC	1997	DBLP DOI BibTeX RDF
17	Wolfram Drescher, Kay Bachmann, Gerhard P. Fettweis	VLSI architecture for datapath integration of arithmetic over GF(2 m) on digital signal processors.	ICASSP	1997	DBLP DOI BibTeX RDF
17	I. Chakrabarti, Dipankar Sarkar 0001, Arun K. Majumdar	Inductive Verification of Sequential Circuits with a Datapath.	VLSI Design	1997	DBLP DOI BibTeX RDF
17	Young-No Kim, Hae-Dong Lee, Sun-Young Hwang	An interconnect Allocation Algorithm for Performance-Driven Datapath Synthesis.	J. Circuits Syst. Comput.	1996	DBLP DOI BibTeX RDF
17	Carl Ebeling, Darren C. Cronquist, Paul Franklin	RaPiD - Reconfigurable Pipelined Datapath.	FPL	1996	DBLP DOI BibTeX RDF
17	Christos A. Papachristou, Mehrdad Nourani	False path exclusion in delay analysis of RTL-based datapath-controller designs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
17	Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji	An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF
17	Ramin Hojati, Robert K. Brayton	Automatic Datapath Abstraction In Hardware Systems.	CAV	1995	DBLP DOI BibTeX RDF
17	Tsuyoshi Isshiki, Wayne Wei-Ming Dai	High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems.	FPGA	1995	DBLP DOI BibTeX RDF
17	Hae-Dong Lee, Sun-Young Hwang	A scheduling algorithm for multiport memory minimization in datapath synthesis.	ASP-DAC	1995	DBLP DOI BibTeX RDF
17	Andrew A. Duncan, David C. Hendry	Area efficient DSP datapath synthesis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
17	Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman	Floorplanning with Datapath Optimization.	ISCAS	1995	DBLP DOI BibTeX RDF
17	Kyumyung Choi, Steven P. Levitan	Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics.	ISCAS	1995	DBLP DOI BibTeX RDF
17	Norman Yeung, Barbara Zivkov, Gülbin Ezer	Unified Datapath: An Innovative Approach to the Design of a Low-Cost, Low-Power, High-Performance Microprocessor.	COMPCON	1994	DBLP DOI BibTeX RDF
17	Tsuyoshi Isshiki, Wayne Wei-Ming Dai	Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM).	FPL	1994	DBLP DOI BibTeX RDF
17	Steve C.-Y. Huang, Wayne H. Wolf	How datapath allocation affects controller delay.	HLSS	1994	DBLP DOI BibTeX RDF
17	D. Sreenivasa Rao, Fadi J. Kurdahi	Controller and datapath trade-offs in hierarchical RT-level synthesis.	HLSS	1994	DBLP DOI BibTeX RDF
17	Hitomi Sato, Michihiro Yamazaki, Masahiro Fujita	YEPHCAD and FLORA: Logic Synthesis for Control and Datapath.	ICCD	1994	DBLP DOI BibTeX RDF
17	Baher Haroun, Behzard Sajjadi	Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs.	ICCD	1994	DBLP DOI BibTeX RDF
17	John Paul Neil	Simulated annealing based datapath synthesis.		1994	RDF
17	Andrew A. Duncan, David C. Hendry	DSP datapath synthesis eliminating global interconnect.	EURO-DAC	1993	DBLP DOI BibTeX RDF
17	Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey	High level synthesis for reconfigurable datapath structures.	ICCAD	1993	DBLP DOI BibTeX RDF
17	Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji	An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis.	VLSI Design	1993	DBLP DOI BibTeX RDF
17	Vincent Olive, R. Airiau, J. M. Bergé, Anne Robert	Using VHDL for datapath synthesis.	EURO-DAC	1992	DBLP DOI BibTeX RDF
17	Goro Suzuki, Tetsuya Yamamoto, Kyoji Yuyama, Kotaro Hirasawa	MOSAIC: a tile-based datapath layout generator.	ICCAD	1992	DBLP DOI BibTeX RDF
17	Masahiro Fujita	RTL Design Verification by Making Use of Datapath Information.	ICCD	1992	DBLP DOI BibTeX RDF
17	Biswadip Mitra, Parimal Pal Chaudhuri	Combined Synthesis of Easily Testable Datapath and Control Designs.	VLSI Design	1992	DBLP DOI BibTeX RDF
17	C. Safina, Régis Leveugle	Clocking scheme selection for circuits made up of a controller and a datapath.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
17	Steve C.-Y. Huang, Wayne H. Wolf	Timing-Driven State Assignment for Controller-Datapath Systems.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
17	Lotfi Ben Ammar, Alain Greiner	FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
17	Amnon Baron Cohen, Michael Shechory	Pathway: A datapath layout assembler.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
17	David W. Knapp	Datapath optimization using feedback.	EURO-DAC	1991	DBLP BibTeX RDF
17	Allen C.-H. Wu, Daniel D. Gajski	Glue-logic partitioning for floorplans with a rectilinear datapath.	EURO-DAC	1991	DBLP BibTeX RDF
17	Amnon Baron Cohen, Michael Shechory	Track Assignment in the Pathway Datapath Layout Assembler.	ICCAD	1991	DBLP DOI BibTeX RDF
17	C. Y. Roger Chen, Michael Z. Moricz	Datapath Scheduling for Two-Level Pipelining.	DAC	1991	DBLP DOI BibTeX RDF
17	S. J. Harrold	Gate array implementation of a multichannel accumulator using a serial datapath.	Microprocess. Microsystems	1990	DBLP DOI BibTeX RDF
17	Neerav Berry, Barry M. Pangrle	SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system.	EURO-DAC	1990	DBLP DOI BibTeX RDF
17	David Knapp	Feedback-Driven Datapath Optimization in Fasolt.	ICCAD	1990	DBLP DOI BibTeX RDF
17	Donald Curry	Schematic specification of datapath layout.	ICCD	1989	DBLP DOI BibTeX RDF
17	N. S. H. Brooks, R. J. Mack	A novel approach to the synthesis of practical datapath architectures using artificial intelligence techniques.	ICCD	1988	DBLP DOI BibTeX RDF
17	Mark Birman, George Chu, Larry Hu, John McLeod, N. Bedard, F. Ware, L. Torban, C. M. Lim	Design of a high-speed arithmetic datapath.	ICCD	1988	DBLP DOI BibTeX RDF
17	Peter Pfahler	Automated datapath synthesis: a compilation approach.	Microprocess. Microprogramming	1987	DBLP DOI BibTeX RDF
17	Yau-Hwang Kuo, Jang-Pong Hsu, Ling Yeung Kung	A graph-based algorithm for the automated datapath synthesis of ASM.	Microprocess. Microprogramming	1987	DBLP DOI BibTeX RDF
17	Alice C. Parker, Jorge T. Pizarro, Mitch J. Mlinar	MAHA: a program for datapath synthesis.	DAC	1986	DBLP DOI BibTeX RDF
9	Rupesh S. Shelar, Marek Patyra	Impact of local interconnects on timing and power in a high performance microprocessor.	ISPD	2010	DBLP DOI BibTeX RDF	CAD, delay, interconnects, power, microprocessor
9	Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken	The challenges of implementing fine-grained power gating.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating
9	Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li 0001, Gi-Joon Nam, Charles B. Winn	Detecting tangled logic structures in VLSI netlists.	DAC	2010	DBLP DOI BibTeX RDF	congestion prediction, rent rule, tangled logic, clustering
9	Huynh Phung Huynh, Tulika Mitra	Runtime Adaptive Extensible Embedded Processors - A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF
9	Nainesh Agarwal, Nikitas J. Dimopoulos	Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing.	SAMOS	2009	DBLP DOI BibTeX RDF
9	Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik	Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.	CAV	2009	DBLP DOI BibTeX RDF
9	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
9	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
9	David Sheldon, Frank Vahid	Making good points: application-specific pareto-point generation for design space exploration using statistical methods.	FPGA	2009	DBLP DOI BibTeX RDF	configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments
9	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction router: Yet another low latency on-chip router architecture.	HPCA	2009	DBLP DOI BibTeX RDF
9	George Michelogiannakis, James D. Balfour, William J. Dally	Elastic-buffer flow control for on-chip networks.	HPCA	2009	DBLP DOI BibTeX RDF
9	Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using NoC routers as processing elements.	SBCCI	2009	DBLP DOI BibTeX RDF	SoC, system-on-chip, network-on-chip, routing algorithm, NoC, MP-SoC
9	Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	TotalProf: a fast and accurate retargetable source code profiler.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	source code profiling, architecture description language, performance estimation, instruction set simulation
9	Xu Guo 0001, Patrick Schaumont	Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.	ARC	2009	DBLP DOI BibTeX RDF
9	Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak	Exploiting residue number system for power-efficient digital signal processing in embedded processors.	CASES	2009	DBLP DOI BibTeX RDF	compiler, power, processor, residue number system, per-
9	Chetan Murthy, Prabhat Mishra 0001	Bitmask-based control word compression for NISC architectures.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	no instruction set computer, compression
9	Yang Sun 0001, Joseph R. Cavallaro	High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	mimo detection, VLSI architecture, ASIC design
9	Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner	AnySP: anytime anywhere anyway signal processing.	ISCA	2009	DBLP DOI BibTeX RDF	fully programmable architecture, high-end signal processing, single-instruction multiple-data parallelism, software defined radio, low-power architecture, simd
9	Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel	A Compact and Accurate Gaussian Variate Generator.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet	Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Sabyasachi Das, Sunil P. Khatri	A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design
9	Fabrice Urban, Ronan Poullaouec, Jean-François Nezan, Olivier Déforges	A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
9	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
9	Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal	Presynthesis Area Estimation of Reconfigurable Streaming Accelerators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
9	Zhi Guo, Walid A. Najjar, Betul Buyukkurt	Efficient hardware code generation for FPGAs.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	FPGA, high-level synthesis, VHDL, Reconfigurable computing, data reuse
9	Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev	Reducing register pressure in SMT processors through L2-miss-driven early register release.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	register file, Simultaneous multithreading
9	Sabyasachi Das, Sunil P. Khatri	Resource sharing among mutually exclusive sum-of-product blocks for area reduction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF
9	Thomas Lenart, Mats Gustafsson, Viktor Öwall	A Hardware Acceleration Platform for Digital Holographic Imaging.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	digital holography, flexible FFT, data scaling, hybrid floating-point, burst oriented memory, matrix transpose
9	Rohit Saraswat, Brandon Eames	On the Use of DesertFD to Generate Custom Architectures for H.264 Motion Estimation.	ECBS	2008	DBLP DOI BibTeX RDF	Architecture derivation, DesertFD, Motion Estimation, Design Space Exploration, H.264, Algorithm selection
9	Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah	Reveal: A Formal Verification Tool for Verilog Designs.	LPAR	2008	DBLP DOI BibTeX RDF
9	Ralf König 0001, Timo Stripf, Jürgen Becker 0001	A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.	DATE	2008	DBLP DOI BibTeX RDF
9	Yonghyun Hwang, Samar Abdi, Daniel Gajski	Cycle-approximate Retargetable Performance Estimation at the Transaction Level.	DATE	2008	DBLP DOI BibTeX RDF
9	Huiju Cheng, Howard M. Heys, Cheng Wang	PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems.	DSD	2008	DBLP DOI BibTeX RDF
9	Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto	High performance current-mode differential logic.	ASP-DAC	2008	DBLP DOI BibTeX RDF
9	Swaroop Ghosh, Kaushik Roy 0001	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
9	Yang Sun 0001, Joseph R. Cavallaro	Unified decoder architecture for LDPC/turbo codes.	SiPS	2008	DBLP DOI BibTeX RDF
9	Chun Jason Xue, Tiantian Liu 0001, Zili Shao, Jingtong Hu, Zhiping Jia, Weijia Jia 0001, Edwin Hsing-Mean Sha	Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.	ICASSP	2008	DBLP DOI BibTeX RDF
9	Johan Eilert, Di Wu 0003, Dake Liu	Implementation of a programmable linear MMSE detector for MIMO-OFDM.	ICASSP	2008	DBLP DOI BibTeX RDF
9	Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola	On Evolutionary Synthesis of Linear Transforms in FPGA.	ICES	2008	DBLP DOI BibTeX RDF
9	Saar Drimer, Tim Güneysu, Christof Paar	DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
9	Filipe Oliveira, Castro M. P. Silva Santos, Fernando A. Castro, José Carlos Alves	A Custom Processor for a TDMA Solver in a CFD Application.	ARC	2008	DBLP DOI BibTeX RDF
9	Samar Yazdani, Joel Cambonie, Bernard Pottier	Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems.	ARC	2008	DBLP DOI BibTeX RDF	coarse-grain architecture, shared-memory programming model, embedded systems, multimedia applications
9	Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan	Verification of arithmetic datapaths using polynomial function models and congruence solving.	ICCAD	2008	DBLP DOI BibTeX RDF
9	Xu Wang, Ge Gan, Joseph B. Manzano, Dongrui Fan, Shuxu Guo	A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor.	ICPADS	2008	DBLP DOI BibTeX RDF
9	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
9	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh	Systematic design of high-radix Montgomery multipliers for RSA processors.	ICCD	2008	DBLP DOI BibTeX RDF
9	Ashur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev	Conversion driven design of binary to mixed radix circuits.	ICCD	2008	DBLP DOI BibTeX RDF
9	Nainesh Agarwal, Nikitas J. Dimopoulos	FSMD partitioning for low power using simulated annealing.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Weining Hao, Martin Radetzki	A data traffic efficient H.264 deblocking IP.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Akashi Satoh	ASIC hardware implementations for 512-bit hash function Whirlpool.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Yang Liu 0016, Fei Sun, Tong Zhang 0002	Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling.	ISCAS	2008	DBLP DOI BibTeX RDF