Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Victor J. Lam, Kunle Olukotun |
DCP: an algorithm for datapath/control partitioning of synthesizable RTL models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 442-449, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Allen C.-H. Wu |
Datapath Optimization Using Layout Information: An Empirical Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 5(2), pp. 195-209, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin |
DP-Gen: a datapath generator for multiple-FPGA applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 563-568, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Masayuki Yamaguchi, Akihisa Yamada 0001, Toshihiro Nakaoka, Takashi Kambe |
Architecture evaluation based on the datapath structure and parallel constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 503-508, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Wolfram Drescher, Kay Bachmann, Gerhard P. Fettweis |
VLSI architecture for datapath integration of arithmetic over GF(2 m) on digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '97, Munich, Germany, April 21-24, 1997, pp. 631-634, 1997, IEEE Computer Society, 0-8186-7919-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | I. Chakrabarti, Dipankar Sarkar 0001, Arun K. Majumdar |
Inductive Verification of Sequential Circuits with a Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 226-231, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Young-No Kim, Hae-Dong Lee, Sun-Young Hwang |
An interconnect Allocation Algorithm for Performance-Driven Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 6(4), pp. 403-424, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Carl Ebeling, Darren C. Cronquist, Paul Franklin |
RaPiD - Reconfigurable Pipelined Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings, pp. 126-135, 1996, Springer, 3-540-61730-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Christos A. Papachristou, Mehrdad Nourani |
False path exclusion in delay analysis of RTL-based datapath-controller designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 336-341, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji |
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 3(1), pp. 21-36, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Ramin Hojati, Robert K. Brayton |
Automatic Datapath Abstraction In Hardware Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 98-113, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Tsuyoshi Isshiki, Wayne Wei-Ming Dai |
High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 167-173, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Hae-Dong Lee, Sun-Young Hwang |
A scheduling algorithm for multiport memory minimization in datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995, 1995, ACM, 0-89791-766-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Andrew A. Duncan, David C. Hendry |
Area efficient DSP datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 130-135, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman |
Floorplanning with Datapath Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 41-44, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Kyumyung Choi, Steven P. Levitan |
Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 1049-1052, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Norman Yeung, Barbara Zivkov, Gülbin Ezer |
Unified Datapath: An Innovative Approach to the Design of a Low-Cost, Low-Power, High-Performance Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPCON ![In: Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28 - March 4, 1994, pp. 32-37, 1994, IEEE Computer Society, 0-8186-5380-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Tsuyoshi Isshiki, Wayne Wei-Ming Dai |
Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, pp. 373-384, 1994, Springer, 3-540-58419-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Steve C.-Y. Huang, Wayne H. Wolf |
How datapath allocation affects controller delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLSS ![In: Proceedings of the 7th International Symposium on High Level Synthesis, HLSS'94, Niagra-on-the-Lake, ON, Canada, May 18-20, 1994, pp. 158-163, 1994, ACM, 0-8186-5785-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | D. Sreenivasa Rao, Fadi J. Kurdahi |
Controller and datapath trade-offs in hierarchical RT-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLSS ![In: Proceedings of the 7th International Symposium on High Level Synthesis, HLSS'94, Niagra-on-the-Lake, ON, Canada, May 18-20, 1994, pp. 152-157, 1994, ACM, 0-8186-5785-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Hitomi Sato, Michihiro Yamazaki, Masahiro Fujita |
YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 527-530, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Baher Haroun, Behzard Sajjadi |
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 587-589, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | John Paul Neil |
Simulated annealing based datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1994 |
RDF |
|
17 | Andrew A. Duncan, David C. Hendry |
DSP datapath synthesis eliminating global interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993, pp. 46-51, 1993, IEEE Computer Society, 0-8186-4350-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey |
High level synthesis for reconfigurable datapath structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, pp. 26-29, 1993, IEEE Computer Society / ACM, 0-8186-4490-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji |
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 192-197, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Vincent Olive, R. Airiau, J. M. Bergé, Anne Robert |
Using VHDL for datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992, pp. 732-737, 1992, IEEE Computer Society Press, 0-8186-2780-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Goro Suzuki, Tetsuya Yamamoto, Kyoji Yuyama, Kotaro Hirasawa |
MOSAIC: a tile-based datapath layout generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers, pp. 166-170, 1992, IEEE Computer Society / ACM, 0-8186-3010-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Masahiro Fujita |
RTL Design Verification by Making Use of Datapath Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 592-597, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Biswadip Mitra, Parimal Pal Chaudhuri |
Combined Synthesis of Easily Testable Datapath and Control Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 187-192, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | C. Safina, Régis Leveugle |
Clocking scheme selection for circuits made up of a controller and a datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Synthesis for Control Dominated Circuits ![In: Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992, pp. 293-308, 1992, North-Holland, 0-444-81479-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
17 | Steve C.-Y. Huang, Wayne H. Wolf |
Timing-Driven State Assignment for Controller-Datapath Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Synthesis for Control Dominated Circuits ![In: Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992, pp. 19-31, 1992, North-Holland, 0-444-81479-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
17 | Lotfi Ben Ammar, Alain Greiner |
FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Synthesis for Control Dominated Circuits ![In: Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992, pp. 133-151, 1992, North-Holland, 0-444-81479-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
17 | Amnon Baron Cohen, Michael Shechory |
Pathway: A datapath layout assembler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Synthesis for Control Dominated Circuits ![In: Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992, pp. 119-131, 1992, North-Holland, 0-444-81479-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
17 | David W. Knapp |
Datapath optimization using feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991, pp. 129-134, 1991, EEE Computer Society, 0-8186-2130-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
17 | Allen C.-H. Wu, Daniel D. Gajski |
Glue-logic partitioning for floorplans with a rectilinear datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991, pp. 162-166, 1991, EEE Computer Society, 0-8186-2130-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
17 | Amnon Baron Cohen, Michael Shechory |
Track Assignment in the Pathway Datapath Layout Assembler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 102-105, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | C. Y. Roger Chen, Michael Z. Moricz |
Datapath Scheduling for Two-Level Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 603-606, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | S. J. Harrold |
Gate array implementation of a multichannel accumulator using a serial datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 14(4), pp. 205-209, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Neerav Berry, Barry M. Pangrle |
SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 78-82, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | David Knapp |
Feedback-Driven Datapath Optimization in Fasolt. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 300-303, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Donald Curry |
Schematic specification of datapath layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989, pp. 28-34, 1989, IEEE, 0-8186-1971-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | N. S. H. Brooks, R. J. Mack |
A novel approach to the synthesis of practical datapath architectures using artificial intelligence techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 388-391, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Mark Birman, George Chu, Larry Hu, John McLeod, N. Bedard, F. Ware, L. Torban, C. M. Lim |
Design of a high-speed arithmetic datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 214-215, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Peter Pfahler |
Automated datapath synthesis: a compilation approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 21(1-5), pp. 577-584, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
17 | Yau-Hwang Kuo, Jang-Pong Hsu, Ling Yeung Kung |
A graph-based algorithm for the automated datapath synthesis of ASM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 21(1-5), pp. 647-654, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
17 | Alice C. Parker, Jorge T. Pizarro, Mitch J. Mlinar |
MAHA: a program for datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 461-466, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
9 | Rupesh S. Shelar, Marek Patyra |
Impact of local interconnects on timing and power in a high performance microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 145-152, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CAD, delay, interconnects, power, microprocessor |
9 | Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken |
The challenges of implementing fine-grained power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 361-364, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating |
9 | Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li 0001, Gi-Joon Nam, Charles B. Winn |
Detecting tangled logic structures in VLSI netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 603-608, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
congestion prediction, rent rule, tangled logic, clustering |
9 | Huynh Phung Huynh, Tulika Mitra |
Runtime Adaptive Extensible Embedded Processors - A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 215-225, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Nainesh Agarwal, Nikitas J. Dimopoulos |
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 108-117, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik |
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 414-429, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 277, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd |
9 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 43-52, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
9 | David Sheldon, Frank Vahid |
Making good points: application-specific pareto-point generation for design space exploration using statistical methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 123-132, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments |
9 | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga |
Prediction router: Yet another low latency on-chip router architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 367-378, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | George Michelogiannakis, James D. Balfour, William J. Dally |
Elastic-buffer flow control for on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 151-162, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva |
Using NoC routers as processing elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SoC, system-on-chip, network-on-chip, routing algorithm, NoC, MP-SoC |
9 | Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
TotalProf: a fast and accurate retargetable source code profiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 305-314, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
source code profiling, architecture description language, performance estimation, instruction set simulation |
9 | Xu Guo 0001, Patrick Schaumont |
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 169-180, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak |
Exploiting residue number system for power-efficient digital signal processing in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 19-28, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler, power, processor, residue number system, per- |
9 | Chetan Murthy, Prabhat Mishra 0001 |
Bitmask-based control word compression for NISC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 321-326, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
no instruction set computer, compression |
9 | Yang Sun 0001, Joseph R. Cavallaro |
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 445-450, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mimo detection, VLSI architecture, ASIC design |
9 | Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner |
AnySP: anytime anywhere anyway signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 128-139, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fully programmable architecture, high-end signal processing, single-instruction multiple-data parallelism, software defined radio, low-power architecture, simd |
9 | Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel |
A Compact and Accurate Gaussian Variate Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 517-527, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet |
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1454-1464, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu |
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 376-387, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Sabyasachi Das, Sunil P. Khatri |
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(3), pp. 326-331, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli |
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(5), pp. 672-685, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design |
9 | Fabrice Urban, Ronan Poullaouec, Jean-François Nezan, Olivier Déforges |
A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 18(12), pp. 1781-1785, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1761-1774, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal |
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2027-2038, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Zhi Guo, Walid A. Najjar, Betul Buyukkurt |
Efficient hardware code generation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(1), pp. 6:1-6:26, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, high-level synthesis, VHDL, Reconfigurable computing, data reuse |
9 | Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev |
Reducing register pressure in SMT processors through L2-miss-driven early register release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(3), pp. 13:1-13:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register file, Simultaneous multithreading |
9 | Sabyasachi Das, Sunil P. Khatri |
Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 51:1-51:7, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Thomas Lenart, Mats Gustafsson, Viktor Öwall |
A Hardware Acceleration Platform for Digital Holographic Imaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 297-311, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
digital holography, flexible FFT, data scaling, hybrid floating-point, burst oriented memory, matrix transpose |
9 | Rohit Saraswat, Brandon Eames |
On the Use of DesertFD to Generate Custom Architectures for H.264 Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 15th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2008), 31 March - 4 April 2008, Belfast, Northern Ireland, pp. 359-368, 2008, IEEE Computer Society, 978-0-7695-3141-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Architecture derivation, DesertFD, Motion Estimation, Design Space Exploration, H.264, Algorithm selection |
9 | Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah |
Reveal: A Formal Verification Tool for Verilog Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LPAR ![In: Logic for Programming, Artificial Intelligence, and Reasoning, 15th International Conference, LPAR 2008, Doha, Qatar, November 22-27, 2008. Proceedings, pp. 343-352, 2008, Springer, 978-3-540-89438-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Ralf König 0001, Timo Stripf, Jürgen Becker 0001 |
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 604-609, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yonghyun Hwang, Samar Abdi, Daniel Gajski |
Cycle-approximate Retargetable Performance Estimation at the Transaction Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 3-8, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Huiju Cheng, Howard M. Heys, Cheng Wang |
PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 383-390, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto |
High performance current-mode differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 720-725, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Swaroop Ghosh, Kaushik Roy 0001 |
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 635-640, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yang Sun 0001, Joseph R. Cavallaro |
Unified decoder architecture for LDPC/turbo codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2008, October 8-10, 2008, Washington, D.C. Metro Area, USA, pp. 13-18, 2008, IEEE, 978-1-4244-2924-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Chun Jason Xue, Tiantian Liu 0001, Zili Shao, Jingtong Hu, Zhiping Jia, Weijia Jia 0001, Edwin Hsing-Mean Sha |
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 1453-1456, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Johan Eilert, Di Wu 0003, Dake Liu |
Implementation of a programmable linear MMSE detector for MIMO-OFDM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 5396-5399, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola |
On Evolutionary Synthesis of Linear Transforms in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 141-152, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Saar Drimer, Tim Güneysu, Christof Paar |
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 99-108, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Filipe Oliveira, Castro M. P. Silva Santos, Fernando A. Castro, José Carlos Alves |
A Custom Processor for a TDMA Solver in a CFD Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 63-74, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Samar Yazdani, Joel Cambonie, Bernard Pottier |
Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 15-26, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coarse-grain architecture, shared-memory programming model, embedded systems, multimedia applications |
9 | Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan |
Verification of arithmetic datapaths using polynomial function models and congruence solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 122-128, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Xu Wang, Ge Gan, Joseph B. Manzano, Dongrui Fan, Shuxu Guo |
A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 689-696, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
VESPA: portable, scalable, and flexible FPGA-based vector processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 61-70, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor |
9 | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
Systematic design of high-radix Montgomery multipliers for RSA processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 416-421, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Ashur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev |
Conversion driven design of binary to mixed radix circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 410-415, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Nainesh Agarwal, Nikitas J. Dimopoulos |
FSMD partitioning for low power using simulated annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1244-1247, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Weining Hao, Martin Radetzki |
A data traffic efficient H.264 deblocking IP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3430-3433, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Akashi Satoh |
ASIC hardware implementations for 512-bit hash function Whirlpool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2917-2920, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yang Liu 0016, Fei Sun, Tong Zhang 0002 |
Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 740-743, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|