Search results for "jitter"

Hits ?▲	Authors	Title	Venue	Year	Link
12	Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang	A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
12	Yuan Zhang, Jiliang Zhang 0002	A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
12	Zida Chen, Ziran Zhang, Haoying Li, Menghao Li, Yueting Chen, Qi Li, Huajun Feng, Zhihai Xu, Shiqi Chen	Deep Linear Array Pushbroom Image Restoration: A Degradation Pipeline and Jitter-Aware Restoration Network.	CoRR	2024	DBLP DOI BibTeX RDF
12	Yushi Koyasako, Takahiro Suzuki, Tomoya Hatano, Tatsuya Shimada, Tomoaki Yoshida	Demonstration of real-time jitter-buffered architecture that collects network information for deterministic optical communication.	J. Opt. Commun. Netw.	2024	DBLP DOI BibTeX RDF
12	Florent Bernard, Arturo Mollinedo Garay, Patrick Haddad, Nathalie Bochard, Viktor Fischer	Low Cost and Precise Jitter Measurement Method for TRNG Entropy Assessment.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2024	DBLP DOI BibTeX RDF
12	Min-Ji Kim, Won-Young Lee	Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation.	ICEIC	2024	DBLP DOI BibTeX RDF
12	Kyuyeon Lee, Chungyong Lee	Adaptive Antenna Activation for UAV Communication with Jitter.	ICEIC	2024	DBLP DOI BibTeX RDF
12	Zida Chen, Ziran Zhang, Haoying Li, Menghao Li, Yueting Chen, Qi Li, Huajun Feng, Zhihai Xu, Shiqi Chen	Deep Linear Array Pushbroom Image Restoration: A Degradation Pipeline and Jitter-Aware Restoration Network.	AAAI	2024	DBLP DOI BibTeX RDF
12	Hironao Abe, Hideo Kawata, Yuhei Kawakami, Shinichi Yoshihara, Tomoaki Yoshida	TAS Rescheduling Using Different Amounts of Allowable Jitter.	CCNC	2024	DBLP DOI BibTeX RDF
12	Yuankang Zhao, Qinghua Wu, Gerui Lv, Furong Yang, Jiuhai Zhang, Feng Peng, Yanmei Liu, Zhenyu Li 0001, Ying Chen, Hongyu Guo, Gaogang Xie	JitBright: towards Low-Latency Mobile Cloud Rendering through Jitter Buffer Optimization.	NOSSDAV	2024	DBLP DOI BibTeX RDF
12	Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi	10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi	10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Haoran Li, Tailong Xu, Xi Meng, Jun Yin 0001, Rui Paulo Martins, Pui-In Mak	10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada	10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino	10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin	10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Yunbo Huang, Yong Chen 0005, Zunsong Yang, Rui Paulo Martins, Pui-In Mak	7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Byeong-Taek Moon, Hyun-Chul Park, Sang-Gug Lee 0001	10.8 A 281GHz, -1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Jennifer C. Saldanha, Malini Suvarna, Dayakshini Sathish, Cynthia Santhmayor	Jitter as a quantitative indicator of dysphonia in Parkinson's disease.	Int. J. Intell. Syst. Technol. Appl.	2023	DBLP DOI BibTeX RDF
12	Geunyeong Jang, Byungha You, In-Ho Lee, Haejoon Jung, Hyundong Shin	Secrecy Rate Degradation of Ground-to-Air Collaborative Beamforming Due to UAV Jitter.	IEEE Trans. Veh. Technol.	2023	DBLP DOI BibTeX RDF
12	Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo	A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Yao-Chia Liu, Wei-Zen Chen, Yuan-Sheng Lee, Yu-Hsiang Chen, Shawn Ming, Ying-Hsi Lin	A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Wei-Jhih Jian, Wei-Zen Chen	A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi	A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho	A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Yu Zhao, Mahdi Forghani, Behzad Razavi	A 20-GHz PLL With 20.9-fs Random Jitter.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Yizhuo Wang, Jiahe Shi, Hao Xu 0005, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao 0001, Hao Min, Na Yan	Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi	A 56-GHz Fractional-N PLL With 110-fs Jitter.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
12	Xiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb	Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud.	ACM Trans. Reconfigurable Technol. Syst.	2023	DBLP DOI BibTeX RDF
12	Milad Mehri	Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk.	Integr.	2023	DBLP DOI BibTeX RDF
12	Kai Li 0018, Xugang Lu, Masato Akagi, Masashi Unoki	Contributions of Jitter and Shimmer in the Voice for Fake Audio Detection.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Kenji Miyamoto, Yoshihito Sakai, Tatsuya Shimada, Tomoaki Yoshida	Traffic Shaping With Optical-Wireless Cooperative Control to Reduce Uplink Jitter Due to Radio Transmission.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Dong-Jun Lee	Incremental Routing and Scheduling Using Multipath and Nonzero Jitter Bound for IEEE 802.1 Qbv Time Aware Shaper.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Xiangyu Meng 0003, Wang Xie, Jiaqi Zhang, Zhao Zhang 0004	A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
12	Dengyu Ran, Xiao Chen, Lei Song	Agile: A high-scalable and low-jitter flow tables lifecycle management framework for multi-core programmable data plane.	Comput. Commun.	2023	DBLP DOI BibTeX RDF
12	S. Vishwa Kiran, S. Raghuram, J. Thriveni, K. R. Venugopal 0001	Reduction of jitter in 3D video by transmitting over multiple network paths.	Int. J. Adv. Intell. Paradigms	2023	DBLP DOI BibTeX RDF
12	Alessio Cortiula, Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri	A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
12	Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins	A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
12	Xu Wang, Michael Peter Kennedy	Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
12	Kshitiz Tyagi, Behzad Razavi	Performance Bounds of ADC-Based Receivers Due to Clock Jitter.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
12	Lukas Schramm, Peter Baumgartner 0005, Jasmin Aghassi-Hagmann	On-Chip Quantization- and Correlation-Robust Jitter Measurement for Low Phase Noise and High Frequency Oscillators.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
12	Mateus Bernardino Moreira, Francois Rivet, Magali De Matos, Hervé Lapuyade, Yann Deval	A (0.75-1.13) mW and (2.4-5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
12	Enrico Bini, Paolo Pazzaglia, Martina Maggio	Zero-Jitter Chains of Periodic LET Tasks via Algebraic Rings.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
12	Zhen Li 0037, Zhenrong Li, Xudong Wang, Zeyuan Wang, Yiqi Zhuang	A low jitter sub-sampling phase-locked loop with sampling thermal noise cancellation technique.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
12	George Souliotis, Andreas Tsimpos, Spyridon Vlassis	Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization.	IEEE Open J. Circuits Syst.	2023	DBLP DOI BibTeX RDF
12	Panagiotis J. Gripeos, D. Oreinos, Dimitris Kriempardis, Andreas D. Tsigopoulos, Efstratios C. Kapotis, Athanassios Katsis, Hector E. Nistazakis	Dispersive FSO Performance Estimation with Gaussian Pulses and Laplace Modeled Time Jitter.	Comput.	2023	DBLP DOI BibTeX RDF
12	Jin Wu, Minwei Hu, Xudong Wu, Yang Zuo, Chenggong Wan, Lixia Zheng, Weifeng Sun	A low jitter fractional PLL with offset current charge pump.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
12	Ding Qiu, Xiangjian Kong, Mingchao Jian, Jiwei Zheng, Chunbing Guo	A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
12	Kejun Wu, Yangchen Xie, Shubo Tao, Zhong Zhang 0002, Ning Ning 0002, Jing Li 0022, Qi Yu 0002	A 3-5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
12	Shaorong Lu, Sheng Xie, Luhong Mao, Ruiliang Song, Naibo Zhang	A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
12	Waseem Sheikh	Jitter-sensitive data communication in emerging wireless networks.	Trans. Emerg. Telecommun. Technol.	2023	DBLP DOI BibTeX RDF
12	Abhisek Panda, Smruti R. Sarangi	FaaSched: A Jitter-Aware Serverless Scheduler.	CoRR	2023	DBLP DOI BibTeX RDF
12	Makoto Takeuchi, Haruo Saito	A method for analyzing sampling jitter in audio equipment.	CoRR	2023	DBLP DOI BibTeX RDF
12	Ricardo Cayssials, Edgardo Ferro	Analysis of real-time jitter in cyber-physical applications using frequency domain perturbation.	Int. J. Gen. Syst.	2023	DBLP DOI BibTeX RDF
12	Kenji Miyamoto, Yoshihito Sakai, Tatsuya Shimada, Tomoaki Yoshida	Demonstration of mobile backhaul uplink jitter reduction with optical-wireless cooperative control for multiple traffic flows.	JOCN	2023	DBLP DOI BibTeX RDF
12	Kai Schoos, Sergej Meschkov, Mehdi B. Tahoori, Dennis R. E. Gnad	JitSCA: Jitter-based Side-Channel Analysis in Picoscale Resolution.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2023	DBLP DOI BibTeX RDF
12	Boyuan Bian, Feng Zhou, Xiaoman Li	Jitter-Caused Clutter and Drift-Caused Clutter of Staring Infrared Sensor in Geostationary Orbit.	Sensors	2023	DBLP DOI BibTeX RDF
12	Anil Ufuk Batmaz, Wolfgang Stuerzlinger	Rotational and Positional Jitter in Virtual Reality Interaction in Everyday VR.	Everyday Virtual and Augmented Reality	2023	DBLP DOI BibTeX RDF
12	Geetha Chandrasekaran, Gustavo de Veciana, Vishnu V. Ratnam, Hao Chen 0010, Charlie Zhang 0002	Delay and Jitter Constrained Wireless Scheduling with Near-Optimal Spectral Efficiency.	PIMRC	2023	DBLP DOI BibTeX RDF
12	Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx	A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET.	MWSCAS	2023	DBLP DOI BibTeX RDF
12	Ping Lu, Bupesh Pandita, Minhan Chen	Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface.	MWSCAS	2023	DBLP DOI BibTeX RDF
12	Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang 0001, Dongbin Lv	Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications.	ICCEIC	2023	DBLP DOI BibTeX RDF
12	Xiuqiang Song, Weijian Xie, Jiachen Li, Nan Wang, Fan Zhong, Guofeng Zhang 0001, Xueying Qin	Minilag Filter for Jitter Elimination of Pose Trajectory in AR Environment.	ISMAR	2023	DBLP DOI BibTeX RDF
12	Muhammad Twaha Ibrahim, M. Gopi 0001, Aditi Majumder	Self-Calibrating Dynamic Projection Mapping System for Dynamic, Deformable Surfaces with Jitter Correction and Occlusion Handling.	ISMAR	2023	DBLP DOI BibTeX RDF
12	Hope Lutwak, T. Scott Murdison, Kevin W. Rio	User Self-Motion Modulates the Perceptibility of Jitter for World-locked Objects in Augmented Reality.	ISMAR	2023	DBLP DOI BibTeX RDF
12	Sen Xu, Yu Fu, Fangfang Li, Hua Zhang, Jincan Xin	Impact of Jitter and Packet loss on Enhanced Voice Serviced for Voice over NR.	CCEAI	2023	DBLP DOI BibTeX RDF
12	Chen Wang, Chengting Yu, Aili Wang 0002	A Biological Population Threshold Coding with Robust Feature Extraction and Neuronal Jitter for SNN-based Speech Recognition.	ICCAI	2023	DBLP DOI BibTeX RDF
12	Baojia Yu, Jinlong Zhang, Jiayi Chen, Yicheng Xu, Ruifeng Gao, Jue Wang 0006	Aerial RIS-Enabled Wireless Coverage Enhancement Under UAV Jitter.	ICCT	2023	DBLP DOI BibTeX RDF
12	Zalfa Jouni, Theo P. Rioufol, Siqi Wang, Aziz Benlarbi-Delaï, Pietro M. Ferreira	Jitter Noise Impact on Analog Spiking Neural Networks: STDP Limitations.	SBCCI	2023	DBLP DOI BibTeX RDF
12	Leandro Passetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda	Evaluation of the Performance Impact of Clock Jitter and Phase Noise in a Two-Band Frequency-Interleaved ADC.	ICECS	2023	DBLP DOI BibTeX RDF
12	Tianshu Xu, Wen Gu, Koichi Ota, Shinobu Hasegawa	A Low-Jitter Hand Tracking System for Improving Typing Efficiency in Virtual Reality Workspace.	TENCON	2023	DBLP DOI BibTeX RDF
12	Andreas Depold, Christian Dorn, Robert Weigel, Fabian Lurz	A Simple Low Jitter Wireless Triggering and Unidirectional Communication System.	WiSNeT	2023	DBLP DOI BibTeX RDF
12	Hongzhuo Liu, Wei Deng 0001, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi	A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter.	ESSCIRC	2023	DBLP DOI BibTeX RDF
12	Xinyu Shen, Zhao Zhang 0004, Guike Li, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.	ESSCIRC	2023	DBLP DOI BibTeX RDF
12	Takumi Ishida, Chedlia Ben Naila, Hiraku Okada, Masaaki Katayama	Performance of Intelligent Reflecting Surface Based-FSO Link Under Strong Turbulence and Spatial Jitter.	ISCC	2023	DBLP DOI BibTeX RDF
12	Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu	An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
12	Li Wang, Zilu Liu, C. Patrick Yue	A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and -248.6-dB FoMjitter.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
12	Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi	A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
12	Jaehong Jung, Kyungmin Lee, Gunwoo Kong, Baekmin Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee	A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
12	Zhao Zhang 0004, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
12	Utku Arda Akinci, Muhammed Salih Inneci, Zeynep Duygu Sütgöl, Faik Baskaya, Günhan Dündar	Jitter Modeling for High Precision Frequency Measurements in Oscillator Circuits.	SMACD	2023	DBLP DOI BibTeX RDF
12	Ankush Mamgain, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Jai Narayan Tripathi	A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA.	NEWCAS	2023	DBLP DOI BibTeX RDF
12	Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff	Correcting ADC jitter using DPLL timing error signal.	NEWCAS	2023	DBLP DOI BibTeX RDF
12	Shizen Nakayama, Tomoki Tsuji, Masayuki Makino, Saki Fujimura, Tsuyoshi Konishi	GHz-class Photonic Tunable Interleaver with Timing Jitter Compression Below 100 fs Based on a MHz-Class Low-Frequency Arbitrary Waveform Generator Upgraded by Optical Time Compression.	PSC	2023	DBLP DOI BibTeX RDF
12	Woosong Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong	A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces.	CICC	2023	DBLP DOI BibTeX RDF
12	Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin	A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL.	CICC	2023	DBLP DOI BibTeX RDF
12	Hoyong Seong, Donghyun Youn, Injun Choi, Junghyup Lee, Sohmyung Ha, Minkyu Je	A 0.9V 2MHz 6.4x-Slope-Boosted Quadrature-Phase Relaxation Oscillator with 164.2dBc/Hz FoM and 62.5ppm Period Jitter in 0.18μm CMOS.	CICC	2023	DBLP DOI BibTeX RDF
12	Shiwei Zhang, Wei Deng 0001, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi	A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.	CICC	2023	DBLP DOI BibTeX RDF
12	Xinlin Geng, Zonglin Ye, Yao Xiao, Oian Xie, Zheng Wang 0050	A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels.	CICC	2023	DBLP DOI BibTeX RDF
12	Hironao Abe, Hideo Kawata, Takahiro Kubo, Natsuki Yasuhara, Yuhei Kawakami, Shinichi Yoshihara, Tomoaki Yoshida	Improvement of accommodation efficiency by TAS scheduling considering jitter caused by transmission period.	CCNC	2023	DBLP DOI BibTeX RDF
12	Yongchun Han, Bin Lin 0001, Lin Liu	Anti-jitter Beamforming Design for UAV-Assisted Maritime Monitoring Networks.	ICCC	2023	DBLP DOI BibTeX RDF
12	Jie Li, Haiming Ma, Xiang Zhang, Xianhuan Wu, Zhangwei Chen, Xueying Li, Naisheng Li, Zhiyong Cheng 0007	Measurement and Application of Industrial Robot Jitter.	ICIRA (8)	2023	DBLP DOI BibTeX RDF
12	Hongfei Zu, Mingxu Zhao, Zhangwei Chen, Jianxin He, Jun Zhou 0017	Measurement and Analysis of End Jitter of Six-Axis Industrial Robots.	ICIRA (9)	2023	DBLP DOI BibTeX RDF
12	Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi	A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces.	ISSCC	2023	DBLP DOI BibTeX RDF
12	Byeong-Taek Moon, Sang-Gug Lee 0001, Jaehyouk Choi	A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL.	ISSCC	2023	DBLP DOI BibTeX RDF
12	Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Chanwoong Hwang, Hangi Park, Jaehyouk Choi	A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier.	ISSCC	2023	DBLP DOI BibTeX RDF
12	Subhashish Mukherjee, Yogesh Darwhekar, Jayawardan Janardhanan, Peeyoosh Mirajkar, Raghavendra Reddy, Harish Ramesh, Bichoy Bahr, Jagdish Chand, Uday Meda, Baher Haroun, Shankar Karantha, Ernest Ting-Ta Yen, Keegan Martin, Daniel Gan, Amin Sijelmassi, Sankaran Aniruddhan	A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter.	ISSCC	2023	DBLP DOI BibTeX RDF
12	Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim	A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.	ISSCC	2023	DBLP DOI BibTeX RDF