Search results for "multiprocessing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Branislav Meandzija	Archetype: A Unified Method for the Design and Implementation of Protocol Architectures.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	data-driven concurrent execution model, abstract protocol architecture specifications, performance constraints, X.25-level 3-like protocol, protocols, data structures, data structures, natural languages, automatic programming, automatic programming, protocol design, automated design, multiprocessing programs, simulation languages, protocol architectures, specification technique, Archetype
13	Alexander Thomasian, Paul F. Bay	Analytic Queueing Network Models for Parallel Processing of Task Systems.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	Computer system performance, parallel processing, Markov chain, task scheduling, multiprogramming, graph model, multiprocessing, queueing network model, hierarchical decomposition, data allocation, task system, occurrence graph
13	Woei Lin, Chuan-lin Wu	Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	connection conflicts, reconfigurable multiprocessors, Parallel processing, interconnection networks, multiprocessing, circuit switching, mapping problems
13	Steven R. Vegdahl	A Survey of Proposed Architectures for the Execution of Functional Languages.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	demand-drive architectures, programming languages, functional programming, Computer architecture, data flow, multiprocessing, data-driven architectures
13	Tsutomu Hoshino, Toshio Kawai, Tomonori Shirakawa, Jun'ichi Higashino, Akira Yamaoka, Hachidai Ito, Takashi Sato, Kazuo Sawada	PACS: A Parallel Microprocessor Array for Scientific Calculations	ACM Trans. Comput. Syst.	1983	DBLP DOI BibTeX RDF	highly parallel processors, multimicroprocessors, nearest neighbor communication, scientific calculation, distributed systems, parallel algorithms, synchronization, multiprocessors, performance measurement, supercomputer, parallel language, processor architecture, MIMD, array processors, multiprocessing, parallel processors
13	Suchai Thanawastien, Victor P. Nelson	Interference Analysis of Shuffle/Exchange Networks.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	shuffle/exchange networks, interconnection networks, performance modeling, Markov modeling, interference, Blocking probability, memory bandwidth, multiprocessing, loading
13	Yih-Chyun Jenq	Digital Convolution Algorithm for Pipelining Multiprocessor Systems.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	digital convolution algorithm, pipelining, multiprocessing, Dedicated processor, tree machine
13	Ellis Horowitz, Alessandro Zorat	The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	VLSI, networks, parallelism, Binary trees, multiprocessing
13	James R. McGraw	Data Flow Computing - Software Development.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	VAL, concurrency, data flow, multiprocessing, Applicative programming
13	Leslie Lamport	How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	hardware correctness, parallel processing, multiprocessing, concurrent computing, Computer design
13	David B. Lomet	A Practical Deadlock Avoidance Algorithm for Data Base Systems.	SIGMOD Conference	1977	DBLP DOI BibTeX RDF	data base systems, resource allocation, operating systems, deadlock, multiprocessing
13	Robert M. Graham	Protection in an information processing utility.	Commun. ACM	1968	DBLP DOI BibTeX RDF	controlled access, information processing utility, reliable operation, shared information, security, privacy, segmentation, protection, multiprogramming, multiprocessing, multi-user, time-sharing
13	Edsger W. Dijkstra	The Structure of "THE"-Multiprogramming System.	Commun. ACM	1968	DBLP DOI BibTeX RDF	cooperating sequential processes, input-output buffering, multiprogramming system, real-time debugging, system hierarchy, operating system, program verification, multiprogramming, multiprocessing, processor sharing, system structure, synchronizing primitives, system levels
13	Earl C. Van Horn	Three criteria for designing computing systems to facilitate debugging.	Commun. ACM	1968	DBLP DOI BibTeX RDF	computer design criteria, computer systems design, computing reliability, deterministic computers, input equipment, input equipment design, multiprogrammed system design, multiprogrammed systems, parallel processing, parallel programming, parallel, debugging, operating systems, programming, programming languages, information security, program testing, determinism, program debugging, protection, multiprogramming, multiprocessing, repeatability, computer systems, memory protection, reproducibility, programming language semantics, programming language design, virtual computers, computer design, information privacy, program semantics, operating systems design, multi processing
13	Peter J. Denning	The Working Set Model for Program Behaviour.	Commun. ACM	1968	DBLP DOI BibTeX RDF	general operating system concepts, scheduling, resource allocation, operating systems, program models, multiprogramming, storage allocation, multiprocessing, program behavior
12	Simona Perri, Francesco Ricca, Marco Sirianni	A parallel ASP instantiator based on DLV.	DAMP	2010	DBLP DOI BibTeX RDF	parallelism, answer set programming, grounding, instantiation
12	Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala	Programmable and Scalable Architecture for Graphics Processing Units.	SAMOS	2009	DBLP DOI BibTeX RDF	TTA, GPU, GPGPU, VLIW, OpenGL, GLSL, LLVM
12	Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	HW/SW methodologies for synchronization in FPGA multiprocessors.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, synchronization, multiprocessors
12	P. Ezudheen, Priya Chandran, Joy Chandra, Biju Puthur Simon, Deepak Ravi	Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines.	PADS	2009	DBLP DOI BibTeX RDF	OSCI, Core affinity, SoC, SystemC, SMP, TLM
12	Michael D. Black	Build an operating system from scratch: a project for an introductory operating systems course.	SIGCSE	2009	DBLP DOI BibTeX RDF	education, operating systems
12	Jingnan Yao, Jiani Guo, Laxmi N. Bhuyan	Ordered Round-Robin: An Efficient Sequence Preserving Packet Scheduler.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
12	Keqin Li 0001	Performance Analysis of Power-Aware Task Scheduling Algorithms on Multiprocessor Computers with Dynamic Voltage and Speed.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
12	Sébastien Bilavarn, Cécile Belleudy, Michel Auguin, T. Dupont, Anne-Marie Fouilliart	Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations.	DSD	2008	DBLP DOI BibTeX RDF
12	Natalia Kryvinska, Christine Strauss, Lukas Auer, Peter Zinterhof	Hierarchical Modelling and an Approximate Analysis of Parallel Queues Models to the NGN SCEs.	FIS	2008	DBLP DOI BibTeX RDF	Next Generation Network (NGN), Queuing theory, Hierarchical modeling, Parallel queues, Service Creation Environment (SCE)
12	Hagit Attiya, Eshcar Hillel	Highly-Concurrent Multi-word Synchronization.	ICDCN	2008	DBLP DOI BibTeX RDF
12	Satoshi Yamada, Shigeru Kusakabe	Effect of context aware scheduler on TLB.	IPDPS	2008	DBLP DOI BibTeX RDF
12	Christof Pitter, Martin Schoeberl	Performance evaluation of a java chip-multiprocessor.	SIES	2008	DBLP DOI BibTeX RDF
12	Tony Degroot, Robert M. Ferencz, Mark Havstad, Neil Eugene Hodge, Jerry Lin, Dennis Parsons, Michael Puso, Jerome Solberg, Edward Zywicz	Accomplishments and Challenges in Code Development for Parallel and Multimechanics Simulations.	VECPAR	2008	DBLP DOI BibTeX RDF
12	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
12	Yan Luo, Jia Yu 0008, Jun Yang 0002, Laxmi N. Bhuyan	Conserving network processor power consumption by exploiting traffic variability.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	scheduling, low power, Network processor, clock gating
12	Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan	ILP and heuristic techniques for system-level design on network processor architectures.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	multiprocessor, block multithreading
12	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	PACT	2007	DBLP DOI BibTeX RDF
12	Yi Li, Kamal Gupta 0001	Motion Planning of Multiple Agents in Virtual Environments on Parallel Architectures.	ICRA	2007	DBLP DOI BibTeX RDF
12	Christof Pitter, Martin Schoeberl	Time Predictable CPU and DMA Shared Memory Access.	FPL	2007	DBLP DOI BibTeX RDF
12	Daniel L. Wang, Charles S. Zender, Stephen F. Jenks	Server-Side Parallel Data Reduction and Analysis.	GPC	2007	DBLP DOI BibTeX RDF
12	Dean M. Tullsen	HCW Keynote Address Holistic Design of Multi-Core Architectures.	IPDPS	2007	DBLP DOI BibTeX RDF
12	Frederica Darema	The Next Generation Software Workshop - IPDPS'07.	IPDPS	2007	DBLP DOI BibTeX RDF
12	Peng Li, Steve Zdancewic	Combining events and threads for scalable network services implementation and evaluation of monadic, application-level concurrency primitives.	PLDI	2007	DBLP DOI BibTeX RDF	scalability, networking, concurrency, programming, implementation, haskell, event, thread, monad
12	Minyeol Seo, Ha Seok Kim, Ji Chan Maeng, Jimin Kim, Minsoo Ryu	An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Master-slave, remote invocation, kernel configuration, multiprocessor, design issues
12	Christof Pitter, Martin Schoeberl	Towards a Java multiprocessor.	JTRES	2007	DBLP DOI BibTeX RDF	Java, multiprocessor, shared memory
12	Davy Genbrugge, Lieven Eeckhout	Statistical simulation of chip multiprocessors running multi-program workloads.	ICCD	2007	DBLP DOI BibTeX RDF
12	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors.	PPAM	2007	DBLP DOI BibTeX RDF	dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
12	Xiaofang Wang, Sotirios G. Ziavras	Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.	ISQED	2007	DBLP DOI BibTeX RDF
12	Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju	A Throughput-Driven Task Creation and Mapping for Network Processors.	HiPEAC	2007	DBLP DOI BibTeX RDF	Intel IXP, Task Creation and Mapping, Throughput, Network Processors, Dataflow Programming
12	David K. Tam, Reza Azimi, Michael Stumm	Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors.	EuroSys	2007	DBLP DOI BibTeX RDF	cache behavior, detecting sharing, performance monitoring unit, single-chip multiprocessors, thread placement, resource allocation, CMP, multithreading, sharing, SMP, simultaneous multithreading, SMT, shared caches, cache locality, thread scheduling, thread migration, hardware performance monitors, hardware performance counters, affinity scheduling
12	Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha	Transactional programming in a multi-core environment.	PPoPP	2007	DBLP DOI BibTeX RDF	parallel programming, transactional memory, atomicity, hardware architecture
12	Francisco Ortiz	Real-Time Elimination of Brightness in Color Images by MS Diagram and Mathematical Morphology.	CAIP	2007	DBLP DOI BibTeX RDF	brightness elimination, color mathematical morphology, connected vectorial filters
12	Xiaoqi Yang 0003, Qilong Zheng, Guoliang Chen 0001, Shujuan Liu, Jun Luan	Transactional Memory Execution for Parallel Multithread Programming without Lock.	PDCAT	2007	DBLP DOI BibTeX RDF
12	Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo 0002, Giovanni Beltrame, Vincent Gagné, Gabriela Nicolescu	Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna	UML-based multiprocessor SoC design framework.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	design flow, architecture exploration, UML 2.0
12	Abhijit Sarkar, Nabil Benabbou, Roger G. Ghanem	Domain Decompostion Of Stochastic PDEs and its Parallel.	HPCS	2006	DBLP DOI BibTeX RDF
12	Ryan Eccles, Deborah A. Stacey	Understanding the Parallel Programmer.	HPCS	2006	DBLP DOI BibTeX RDF
12	Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco	POSIX modeling in SystemC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Dimitrios S. Nikolopoulos	Facing the challenges of multicore processor technologies using autonomic system software.	IPDPS	2006	DBLP DOI BibTeX RDF
12	Amir Hossein Ghamarian, Marc Geilen, Sander Stuijk, Twan Basten, Bart D. Theelen, Mohammad Reza Mousavi 0001, A. J. M. Moonen, Marco Bekooij	Throughput Analysis of Synchronous Data Flow Graphs.	ACSD	2006	DBLP DOI BibTeX RDF
12	Pawel Gepner, Michal Filip Kowalik	Multi-Core Processors: New Way to Achieve High System Performance.	PARELEC	2006	DBLP DOI BibTeX RDF
12	Rajarshi Mukherjee, Seda Ogrenci Memik	Physical aware frequency selection for dynamic thermal management in multi-core systems.	ICCAD	2006	DBLP DOI BibTeX RDF	dynamic thermal management, multi-core system
12	Guy Amit, Yaron Caspi, Ran Vitale, Adi Pinhas	Scalability of Multimedia Applications on Next-Generation Processors.	ICME	2006	DBLP DOI BibTeX RDF
12	Björn Jäger, Mario Porrmann, Ulrich Rückert 0001	Bio-inspired massively parallel architectures for nanotechnologies.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Tim Brecht, G. John Janakiraman, Brian Lynn, Vikram A. Saletore, Yoshio Turner	Evaluating network processing efficiency with processor partitioning and asynchronous I/O.	EuroSys	2006	DBLP DOI BibTeX RDF	asynchronous I/O, TCP/IP, network processing
12	Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Chi Cao Minh, Ben Hertzberg	McRT-STM: a high performance software transactional memory system for a multi-core runtime.	PPoPP	2006	DBLP DOI BibTeX RDF	atomic constructs, two-phase locking and read-versioning, software transactional memory, runtime environment
12	Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie 0001, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.	ISCA	2006	DBLP DOI BibTeX RDF
12	Franklin E. Powers Jr., Gita Alaghband	Introducing the hydra parallel programming system.	SPAA	2006	DBLP DOI BibTeX RDF
12	Peter H. Welch, Fred R. M. Barnes, Fiona Polack	Communicating Complex Systems.	ICECCS	2006	DBLP DOI BibTeX RDF
12	Xinping Zhu, Wei Qin	Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery.	DAC	2006	DBLP DOI BibTeX RDF	fault-tolerance, system-on-chip, network-on-chip, multiprocessor system, run-time verification, retargetable simulation
12	Kyung-suk Lhee, Steve J. Chapin	Detection of file-based race conditions.	Int. J. Inf. Sec.	2005	DBLP DOI BibTeX RDF	Time-of-check-to-time-of-use (TOCTTOU) flaws, Security, Race condition
12	Venkata Krishnan, David Mayhew	Localized Congestion Control in Advanced Switching Interconnects.	IEEE Micro	2005	DBLP DOI BibTeX RDF
12	Monk-Ping Leong, Chi Chiu Cheung, Chin-Wang Cheung, Polly P. M. Wan, Ivan K. H. Leung, Winnie M. M. Yeung, Wing Seung Yuen, Kenneth S. K. Chow, Kwong-Sak Leung, Philip Heng Wai Leong	CPE: A Parallel Library for Financial Engineering Applications.	Computer	2005	DBLP DOI BibTeX RDF	Clustertech parallel environment, Financial engineering, CPE architecture, Finite-difference calculation, Parallel computing, Monte Carlo simulation
12	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
12	JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy	High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	schedulers, Computer-aided design, performance modeling, system modeling, heterogeneous multiprocessors
12	Ejub Kajan, Leonid Stoimenov	Toward an ontology-driven architectural framework for B2B.	Commun. ACM	2005	DBLP DOI BibTeX RDF
12	Luiz André Barroso	The price of performance.	ACM Queue	2005	DBLP DOI BibTeX RDF
12	Thomas C. S. Cheah, Kok-Why Ng	A Practical Implementation of a 3-D Game Engine.	CGIV	2005	DBLP DOI BibTeX RDF
12	Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham	Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor.	MICRO	2005	DBLP DOI BibTeX RDF
12	Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
12	Lawrence Spracklen, Santosh G. Abraham	Chip Multithreading: Opportunities and Challenges.	HPCA	2005	DBLP DOI BibTeX RDF
12	Scott Schneider 0001, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Factory: An Object-Oriented Parallel Programming Substrate for Deep Multiprocessors.	HPCC	2005	DBLP DOI BibTeX RDF	Multithreading substrate, Object-oriented parallel programming, Deep parallel architectures, Multiparadigm parallelism, Portability, Programmability
12	Yuxing Tang, Kun Deng, Xingming Zhou	The Design Space of CMP vs. SMT for High Performance Embedded Processor.	ICESS	2005	DBLP DOI BibTeX RDF
12	Michael Goldweber, Renzo Davoli, Mauro Morsiani	The Kaya OS project and the muMPS hardware emulator.	ITiCSE	2005	DBLP DOI BibTeX RDF	education, operating systems, emulation, hardware
12	Robert L. McGregor, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Annie P. Foong, Gary L. McAlpine, Dave B. Minturn, Greg J. Regnier, Vikram A. Saletore	An Architecture for Software-Based iSCSI on Multiprocessor Servers.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Vikram A. Saletore, Paul M. Stillwell Jr., John A. Wiegert, Phil Cayton, Jeff Gray 0001, Greg J. Regnier	Efficient Direct User Level Sockets for an Intel XeonTM Processor Based TCP On-Load Engin.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Jiani Guo, Jingnan Yao, Laxmi N. Bhuyan	An efficient packet scheduling algorithm in network processors.	INFOCOM	2005	DBLP DOI BibTeX RDF
12	Björn Jäger, Jörg-Christian Niemann, Ulrich Rückert 0001	Analytical approach to massively parallel architectures for nanotechnologies.	ASAP	2005	DBLP DOI BibTeX RDF
12	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Li Zhao 0002, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. Iyer 0001	Design and Implementation of a Content-Aware Switch Using a Network Processor.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
12	Yan Luo, Jia Yu 0008, Jun Yang 0002, Laxmi N. Bhuyan	Low power network processor design using clock gating.	DAC	2005	DBLP DOI BibTeX RDF	low power, network processors
12	Li Zhao 0002, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer 0001	SpliceNP: a TCP splicer using a network processor.	ANCS	2005	DBLP DOI BibTeX RDF	TCP splicing, network processors
12	Doug Burger, Todd M. Austin, Stephen W. Keckler	Recent extensions to the SimpleScalar tool suite.	SIGMETRICS Perform. Evaluation Rev.	2004	DBLP DOI BibTeX RDF
12	Serdar Tasiran, Yuan Yu, Brannon Batson	Linking Simulation with Formal Verification at a Higher Level.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
12	José Antonio Martínez, Leocadio G. Casado, José A. Alvarez, Inmaculada García	Interval Parallel Global Optimization with Charm++.	PARA	2004	DBLP DOI BibTeX RDF
12	Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow	FPGA-based supercomputing: an implementation for molecular dynamics.	FPGA	2004	DBLP DOI BibTeX RDF
12	R. Sharmila, M. V. Lakshmi Priya, Ranjani Parthasarathi	An Active Framework for a WLAN Access Point Using Intel's IXP1200 Network Processor.	HiPC	2004	DBLP DOI BibTeX RDF
12	Michael Wolfe	Supercompilers, the AMD Opteron, and Your Cell Phone.	IPDPS	2004	DBLP DOI BibTeX RDF
12	Alexandra Fedorova, Christopher Small 0001, Daniel Nussbaum, Margo I. Seltzer	Chip multithreading systems need a new operating system scheduler.	ACM SIGOPS European Workshop	2004	DBLP DOI BibTeX RDF
12	Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes	The energy efficiency of CMP vs. SMT for multimedia workloads.	ICS	2004	DBLP DOI BibTeX RDF	multimedia, energy efficiency, CMP, SMT
12	Christopher D. Rickett, Sung-Eun Choi, Bradford L. Chamberlain	Compiling High-Level Languages for Vector Architectures.	LCPC	2004	DBLP DOI BibTeX RDF
12	Chain-Wu Lee, Laurence Tianruo Yang, Chun-Hsi Huang, Sanguthevar Rajasekaran, D. Frank Hsu	Distributed Path-Based Inference in Semantic Networks.	ISPAN	2004	DBLP DOI BibTeX RDF
12	Anthony S. Fong	A computer architecture with access control and cache option tags on individual instruction operands.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF	operand descriptor, optional encaching, system attributes, access control, data coherency